Dual-damascene Cu-interconnect is fabricated in a low-k, divinylsiloxane-benzocyclobuten (DVS-BCB) film to reduce signal transmission delay among circuit-blocks on a chip. One of difficulties is how to make the patterns of via-holes and interconnect-trenches in the DVS-BCB films using photo-resist masks precisely. We have developed a new BCB patterning process such as 'Simultaneous resist-etch-back' (SRECK) process, in which both of the patterned photo-resist film and the DVS-BCB film are etched back simultaneously to transfer the resist-patterns to the BCB film. Since the DVS-BCB film contains siloxane-group, the intensity of Si-related Emission Light (SEL) abruptly increases just after complete pattern transfer to the DVS-BCB. Using the SRECK process with SEL- monitoring, the dual-damascene Cu-interconnects are fabricated in the DVS-BCB film with precise dimension control. Finally, the BCB/Cu-interconnects are demonstrated in the top-layered global interconnects on the advanced MPUs.

Performance of advanced integrated circuit (IC) technology is becoming dominated by interconnect RC propagation delays making the introduction of lower capacitance insulators very attractive. The use of low dielectric constant (low-k) materials will be a key challenge for future interconnect technologies. In the case of BiCMOS technology for RF applications, an additional consideration is to minimize parasitic capacitance of passive components such as inductors, buses, and bond pads. The use of hydrogen silsesquioxane (HSQ) with a dielectric constant of about 3.0 allowed the construction of high quality spiral inductors in a 0.5 micrometer BiCMOS technology. In addition to its low-k properties, the HSQ spin-on dielectric was used for planarization of three polycrystalline silicon layers and four levels of metal interconnects. The HSQ layer was applied in a single coat application in a non-etchback process that achieved excellent planarity with good crack resistance. The stability of blanket HSQ films was shown using FTIR spectra, film stress, and capacitance data. Immunity of devices to hot carrier lifetime degradation was demonstrated. Low resistance and high yield for long metal via chains were obtained by careful integration of the via etch, resist strip and metal deposition processes. Thus we demonstrated the integration of HSQ planarization into an advanced BiCMOS process to take advantage of its excellent planarity and its low dielectric constant.

Low density materials, such as hydrogen silsesquioxane (HSQ), can offer lower dielectric constants. With HSQ, a low value of K can be achieved if the density of Si-H bonding is maintained at a high level. However, the quality of HSQ films are degraded by the damage of oxygen plasma and hygroscopic behavior during photoresist stripping. In addition, the thermal stability of as-cured HSQ films are about 400 degrees Celsius. Both leakage current and dielectric constant of HSQ films rapidly increase with increasing annealing temperature. In this work, we have studied the use of hydrogen plasma to improve the quality of HSQ. The leakage current of HSQ decreases as the H₂ plasma treatment time is increased. The role of hydrogen plasma is to passivate the surface of porous HSQ. In addition, the enhancement of the thermal stability of the HSQ film by fluorine ion implantation treatment was investigated. The implantation step can reduce the leakage current of HSQ with high annealing temperature.The enhancement of thermal stability of the HSQ film is due to the film densification by ion implantation treatment.

Metal films (Al, Cu-1%Al, Cu) were deposited on fluorinated silicon oxide (FSG) of varying fluorine (F) content, obtained from plasma-enhanced chemical vapor deposition, either directly or with a barrier layer (Ta, TaN, TiN) in between. Compositional analysis was done with FTIR and nuclear reaction analysis (NRA), and depth profiles were performed with XPS and NRA. The dielectric constant of the FSG films is shown to be a combined function of film density and F content. This points to structural differences between FSG and undoped SiO₂ films. For Al and Cu-1%Al on FSG, rapid diffusion of F atoms through the metal occurs at typical annealing conditions. With Al, the diffused F accumulates on the top metal surface, and practically no F is present in the bulk of the film. With Cu- 1%Al, surface accumulation and an appreciable bulk concentration of F are observed. With Cu, no significant F diffusion was detectable. Neither Ta nor TaN are good barriers against F diffusion into the metals. On the other hand, TiN may be a useful barrier, as it shows no significant F diffusion but some reaction with F at the Al/TiN interface. A suitable plasma treatment of the FSG before metal deposition can inhibit substantially F diffusion.

Filling of high aspect ratio vias with electroplated copper requires smooth and continuous seed layer whereas prevention of copper diffusion into the adjacent dielectric requires adequate coverage of the barrier along the via sidewalls. Conventional PVD DC magnetron techniques were found to be inadequate for this application, because of insufficient step coverage especially that of Cu on the sidewalls of the high aspect ratio vias, and its agglomeration into discontinuous islands. Ionized metal plasma (IMP) based PVD technology provided superior step coverage of Ta and Cu because of the directionality of the deposited atoms and utilization of ion bombardment to sputter material from the bottom of the via to the sidewalls, thus yielding continuous and conformal barrier and seed layers. Furthermore, the seed layer morphology especially the roughness of the film on the sidewall was found to be quite sensitive to the deposition temperature. The seed layer thickness and film morphology, as well as other deposition parameters as the ratio of coil RF & target DC plasma powers, Ar sputtering pressure, wafer bias and the Ar sputter etch prior to barrier deposition, were all found to affect the subsequent via filling by electroplating. Optimization of the processes enabled filling of high aspect ratio vias. Manufacturability and the process window for the barrier/seed layer processes was evaluated by extended runs and DOEs. The technology was successfully integrated into a multilevel interconnect scheme utilizing Cu plugs, and Cu damascene lines. The via resistance of the Cu plug using this metallization scheme, was found to be significantly lower than that of W plug currently used for Al interconnects. The cost of ownership (COO) of the IMP Ta/Cu seed layer was determined to be significantly lower compared to the current state-of- the-art IMP Ti/CVD TiN liner for W plug.

Electroless barrier deposition for copper metallization potentially provides many advantages, among which are the selectivity to dielectrics, possibility of an amorphous alloy deposition, binary alloy properties enhancement by an addition of a third component, high conformity and low cost. Electroless cobalt-rich CoWP ternary alloys with high phosphorus content (approximately 11 weight percent) and a low weight percent of the third component, tungsten (approximately 2 percent), were deposited in basic solution onto copper and cobalt in integrated circuit structures. A capability of the electroless CoWP deposition to form thin selective and conformal barrier/protection films was demonstrated. Extendibility of these thin films to extremely small, nano- scale dimensions was observed. Conformal 10 nm thick CoWP layer was formed on the sidewalls of 30 - 40 nm wide seam of aspect ratio about 5:1 on the top of 0.4 micrometer wide in- laid Cu line. Thermal stability of electroless CoWP/Cu films investigated by Rutherford Backscattering Spectroscopy (RBS), Auger Electron Spectroscopy (AES) and Secondary Ion Mass Spectroscopy (SIMS) was extended to 500 degrees Celsius for 15 nm thick barrier. Atomic Force Microscopy (AFM) images of the electroless CoWP film surface and sectional analysis showed small grain sizes of CoWP on either electroless or Physical Vapor Deposited (PVD) Cu films. Several passivation schemes to protect the exposed Cu surface and adhesion promotion/barrier layers to stabilize the Cu/dielectric interface in a damascene process were demonstrated.

A key challenge for 0.18 micrometer technology is the interconnect RC delay time, which becomes the limiting factor for device performance. This delay can be reduced by combining the use of a material of low dielectric constant between metal lines and the use of copper, which is a better conductor than aluminum. In this paper some of the difficulties of integrating these types of interconnects are discussed, and a new strategy for post dielectric etch cleaning is presented.

The corrosion of aluminum metal from chlorine plasma etching causes major backend interconnects failure especially when the metal line-width shrinks to sub-half micron geometry. The reason for the corrosion is related to the low volatility and the insufficient removal of residual chlorine by-products which leads to the galvanic attack of the etched metal lines. In this paper, a systematic Capillary Electrophoresis analysis of the residual chlorine on wafer surfaces is presented, the experimental results and analysis show that the amount of chlorine residues on wafer surfaces is strongly dependence on the metal pattern density and the metal stack composition.

The accomplishment of low-resistance interconnecting high- density ULSI integrated devices depends on the cleanliness of the via holes before metal deposition. This paper studies the polymer removal of via cleaning after etching and oxygen ashing using hydroxylamine-based organic solvent on an on-axis spray processor. An investigation into the effect of different process parameters such as spray pressure, rotational speed, cleaning duration and cleaning temperature was carried out. While the variation of spray pressure and rotational does not produce significant changes in the via resistance, the variation in the cleaning duration sees a lower via resistance as the duration is decreased. Additionally, the variation in cleaning temperature produces a process window between 75 degrees Celsius and 85 degrees Celsius (inclusive). The bypassing of isopropyl alcohol in the cleaning sequence gives comparable electrical resistance but suffers from high particle counts. There is no significant difference in via resistance for wafers processed on both Semitool Magnum and the wet bench. High resistance of zero and negative enclosed vias is found to be linked to the attack of titanium in the overlying metal stack.

The downscaling in ULSI devices incorporating self-aligned titanium silicide (salicide) has led to the high sheet resistance and junction leakage. Silicon implantation through metal (ITM) and pre-amorphization implantation (PAI) have been investigated to address the concerns. The selective wet chemical stripping of unreacted titanium and/or titanium nitride after salicide formation (salicide etchback) is an important process and is investigated in this paper on an off- axis spray processor. The etching rates of titanium and titanium nitride that were subjected to a rapid thermal annealing (RTA) are about half that of their non-RTA counterparts. The flow rate of the components in SC-1 is found to have the most impact on the etching rates of the titanium nitride and titanium silicide. The variation of the temperature and ratio of ammonium hydroxide, hydrogen peroxide and deionized water in SC-1 produced different etching selectivity of titanium nitride and titanium to silicon dioxide and titanium silicide. The graphical profile of the both salicidation schemes in the active and field regions correlates the distinct slope patterns to the etching of different film materials, and provides a qualitative assessment in the absence of analytical depth profiling. Electrical tests reveal similar gate-to-source drain leakage values for both PAI and ITM salicide schemes using the standard SC-1 cleaning.

This paper presents the work done to develop a self-aligned, dual-damascene etch in a medium-density (approximately X 10¹⁰ ion/cm³) oxide etch reactor. The systematic study of etch results was guided by the process performance criteria (See Table 1) and wafer material provided by Texas Instruments. This work was performed on a Lam Research Corporation 4520XLE^TM dual-frequency Reactive Ion Etch (RIE) tool. As shown in Figure 1, RF power applied to the upper electrode at a frequency of 27 MHz primarily serves to generate the medium-density plasma. RF applied to the lower electrode at a frequency of 2 MHz primarily controls the relative ion energy. The final process results indicate feasibility using a process with discrete steps for trench, via and nitride removal portions of the dual damascene structure. (See Figure 2)

It is important and critical to obtain reasonable removal rate, low polish non-uniformity, scratchless polished surface and no metal dishing and ILD erosion for aluminum damascene process with CMP. It is difficult to meet these requirements in a single-step polishing process because lower removal rate of titanium, known as polish-inert metal, results in significant over-polish of the aluminum features and severe metal dishing and ILD erosion should be obtained. Here we evaluate a novel 2-step polishing process to accomplish the damascene process more efficiently. First, the overburden aluminum was removed fast and uniformly. In our study, more than 3,000 nm/min removal rate, less than 10% polish non- uniformity and scratchless finished surface could be obtained. Next, by adjusting slurry pH, the removal rate of Al could be about as the same as that of Ti and that of SiO₂ unchanged in the meantime. By this way, it relaxes the process window to overcome the problems of the pattern geometry effects.

CMP, which has been accepted by users mainly as oxide planarization process of ILD in 200 mm/0.25 (mu) design rule, will be applied in 300 mm/0.18 (mu) - 0.13 (mu) design rule. Big features in this new stage are that in mechanical wise 'dry-in dry-out concept' is fully adopted and in process wise, various applications such as STI, metal damascene with Cu, low K materials etc. will be introduced. Accordingly, CMP is not anymore special process and higher performances like other dry processes will be required. The present situation and future points are herein reported.

Development of Chemical Mechanical Polishing (CMP) tools and CMP processes are proceeding in parallel, but are not independent. Advanced processes require more flexibility and high throughput than available on present production CMP tools. This paper illustrates the development of a new CMP tool where both maximum flexibility and highest throughput are being designed in from the very beginning conceptual design. The tool includes capability to meet the predicted future need for copper/low-k dielectric CMP as one primary process model. This specification has led to a four-spindle, three-table tool with multi-step capability on each table. This flexibility allows (for example) for optimized copper CMP on table one, tantalum barrier CMP on table two, and a cleanup buff on table three before passing off to on-board metrology then to the post-CMP cleaner. Independent motions allow for high throughput even when the three process steps are of different time durations. The multitude of CMP processes development and chemistry requirements translate into complex control software and hardware solutions. The paper will describe how meeting these requirements for such flexibility and complexity add cost and delay the tool development process, but lead to a tool which is expected to better serve the microelectronics industry needs for CMP on larger wafer sizes (300 mm), smaller critical dimensions (less than 0.18 micron), and new materials (like Cu). The tool described to illustrate these principles is the Symphony-CMP by Strasbaugh.

Metal Chemical Mechanical Planarization (CMP) and post CMP cleaning have continued to increase in importance in semiconductor manufacturing. The introduction of copper metallization into semiconductor manufacturing processes has created a need for integrating CMP and cleaning tools, as well as a demand for the development of novel cleaning solutions. One system designed for integrated CMP processing and cleaning, commonly referred to as dry-in/dry-out CMP, is the SpeedFam Auriga C. The Auriga C integrates a widely used polishing tool together with a proven cleaning technique. The key to the operation of the Auriga C cleaning process is the effective operation of the PVA brush cleaners, water track transport, final jet rinse and high-speed spinner dryer. The effective operation of the cleaning mechanism for copper post- CMP cleaning requires the use of new chemical solutions. Typical solutions used for post process cleaning of more mature CMP processes are either ineffective for cleaning or chemically incompatible with the copper process. This paper discusses the cleaning mechanism used in an integrated dry- in/dry-out tool and demonstrates an effective and novel cleaning solution for use with this type of post-CMP cleaning process.

A novel 'hot only' AlCu(0.5) fill approach for via applications is presented. It combines an IMP Ti/TiN/Ti liner/wetting layer with a modified Al-fill process. The maximum wafer temperature during deposition is approximately 420 degrees Celsius. The unique filling characteristics allows via filling from bottom up without bridging or overhang formation at the top corners. The different influences of integration issues and hardware on the filling process are discussed. Electrical data (via resistance, product yield) are presented and compared to the standard cold/hot Al-fill and W- plug fill respectively.

The 'explosive phenomenon' of AlCu/TiN metal line (explosive defect) always be observed posterior to deposit oxide film by Plasma Enhanced Chemical Vapor Deposition (PECVD) and their profile look like distorted bamboo structure. From the Tunneling Electronic Microscope (TEM) analysis result and the defect distribution on the wafer, the defects were enhanced by the compressive stress of oxide film. The tungsten (W) etch back process which will remain the impurities such as sulfur (S) and fluorine (F) from the etch gas during the over-etch period has been found to cause the damage of TiN barrier layer. The explosive defect also show the strong 'F' signal not only in the AlCu metal line but on the interface between AlCu and TiN barrier layer by the Energy-Dispersive Spectrometer (EDS) analysis of TEM. In this study, the explosive defect was duplicated successfully by CF4/CHF3 chemical plasma treatment after Tungsten (W) etch back step. The more CF4/CHF3 chemical plasma treated, the more explosive defects were found. This treatment process shown that there were very strong correlation between explosive defect and fluoric impurity. Two effective methods have been demonstrated to reduce the explosive defect. The first one was Argon (Ar) plasma treatment after W etch back. This method could remove the impurity on the TiN surface. Another one was reduced the moisture on the TiN barrier metal surface. No explosive defect was observed after PECVD oxide deposited. The two methods had been proven to be useful methods to solve the explosive phenomenon on AlCu/TiN metal line without the concern of reliability.

The application of Forcefill^®, the high pressure holefill technique for 0.5 micrometer device production is discussed in this paper. For process optimization holefill characteristics are presented as function of Forcefill^® pressure, temperature and process time. Holefill analysis is performed by SEM plan view and cross section. SEM results are correlated to resistance measurements. The productivity of the Forcefill^® process is discussed also. Data are presented showing the very low particle additions achievable with this technique.

As metal pitch requirements for 0.18 micrometer generation logic shrink to 0.50 micrometer pitch and below, the capability of 248 nm deep ultraviolet (DUV) lithography is challenged, especially for isolated narrow lines. Standard illumination methods and binary masks do not give acceptable performance on both dense and isolated 0.25 micrometer structures simultaneously. Two methods available to reliably pattern isolated structures with enough depth of focus (DOF) for high volume manufacturing are Optical Proximity Correction (OPC) techniques such as scattering bars and serifs or the addition of a selective size adjust that sizes all isolated narrow leads up to a width with acceptable DOF. The present work will discuss a manufacturable 0.50 micrometer pitch metallization scheme for leading edge logic applications incorporating DUV lithography, an inorganic silicon oxy- nitride (SION) anti-reflective coating (ARC) layer and standard etch chemistries, with a comparison of the performance of scattering bars and selective size adjusts on isolated lines. Results were characterized by SEM cross sections and electrical data extracted from parametric test structures. Also discussed will be a general methodology of implementing elements of OPC with an eye towards robustness, manufacturability and simplicity of implementation.

Tight interconnect design rules associated with 0.25 micrometer technology and below introduces a number of challenges in backend integration in the course of developing an appropriate process architecture. In this paper, the effect of the underlying metallization on via electrical performance and the attendant integration issues are discussed. For a Ti/TiN/Al-based metal stack, increasing the TiN cap thickness was found to significantly reduce via resistance. Since high density plasma CVD is commonly used to deposit gap-fill oxide after metal patterning, the effect on via resistance of oxygen plasma exposure of the underlying metal stack was also evaluated. A layer of Ti sandwiched between Al and cap TiN was found to give consistently low via resistance values due to reduction of the interfacial resistance contribution from the via/bottom metal interface. In some cases, where W remained exposed after dry etching of the subsequent metal level, complete corrosion of W was observed during solvent strip, for certain structures. Based on these results, various via integration options for current and future multilevel metal interconnect architecture are considered.

BARC technology, originally developed for gate level has now to be applied to interconnection one's. Requirements for dielectric interconnection levels are different from gate level. In the case of gate level ARC has to minimize reflectivity at resist/substrate interface due to notching and resist swing curve effects. Whereas ARC for interconnections has to minimize reflectivity variation at resist/substrate interface due to swing curve effect in the dielectric layer. For interconnections, ARC must be as absorbent as possible at stepper exposure wavelength, and two ways are foreseen: ARC layer with high k value at 248 nm, and ARC layer with high thickness. For a reflectivity variation minimum criteria, we can find a couple values (k, minimum thickness). Experiments give us for a reflectivity variation below 5% the following couples: (k equals 0.7, 1200 Angstrom thickness) and (k equals 1.1, 850 Angstrom). In this paper we describe different applications of SiOxNy for interconnection levels: via, contact and damascene line level. Improvements depending of the SiOxNy thickness are seen in CD dispersion. To conclude SiOxNy ARC can be used for interconnection levels, and its performances depends on ARC couple values (k, thickness).

Historical microprocessor product trends show an increase in product frequency of 1.25X per year and a transistor count increase of 1.4X per year since the early 70s. This trend is forecast to continue over the next decade to the 0.07 micrometer generation. To support the trend, challenges in lithography, transistor definition, interconnect system, and manufacturability must be overcome. Solutions to the lithography challenge, will require successful implementation of 157 nm optical or next generation lithography (NGL). The transistor solution will require integration of sub 2.0 nm gate oxides with improved gate electrode materials, improved low resistance shallow source-drain technology, advanced channel dopant engineering and operation at or below 1.0 v. Interconnect challenges will require support of 10 or more interconnect layers using low resistivity metalization and reduced epsilon dielectric. Manufacturing challenges require support of larger die sizes, integrated at higher technology complexity, while maintaining lowest possible cost.

Recently, IBM announced the first silicon integrated circuit technology that incorporates copper on-chip wiring. This technology, which combines industry-leading CMOS ULSI devices with 6 levels of hierarchically-scaled Cu metallization, has reached the point of manufacturing, after passing the qualification tests required to prove feasibility, yield, reliability, and manufacturability. The discussion of the change from Al To Cu interconnects for ULSI encompasses a wide variety of issues. This paper attempts to address these by way of example, from the broad range of detailed studies that have been performed in the course of developing these so-called 'copper chips.' Motivational issues are covered by comparative modeling of performance aspects and cost. The technology parameters and features are shown, as well as data relating to the process integration, electrical yield and parametric behavior, early manufacturing data, high-frequency modeling and measurements, noise and clock skew. The viability of this technology is indicated by results from reliability stressing, as well as the first successful demonstrations of fully functional SRAM, DRAM, and microprocessor chips with Cu wiring. The advantages of integrated Cu wiring may be applied even more broadly in the future. An example shown here is the achievement of very high-quality integrated inductors; these may help prospects for complete integration of RF and wireless communications chips onto silicon.

This paper gives an overview of the foundry model and foundry technology trend in the future. The foundry model is a part of the natural trend toward the vertical dis-integration (or horizontal specialization) of the semiconductor industry. Foundry technology is already in the leading pack, and will be on the leading edge from now on. Foundry technology will be market driven toward low voltage (core), low power, high performance, high density, and system on chip (SOC). Examples of leading-edge 0.25 micrometer logic and 0.18 micrometer and beyond process features will be used to illustrate this trend.

ULSI circuit performance is constantly increasing, in speed, functionality and device density. This performance increase is supported by the constant development of new processes and new materials, on new equipment platforms, which support the demand for improved defect density and throughput. A key challenge for equipment infrastructure to continue to support this performance acceleration is the shortening of cycle time for equipment development and new material acceptance.