Lithography overlay refers to the measurement of the alignment of successive patterns within the manufacture of semiconductor devices. Control of overlay has become of great importance in semiconductor manufacturing, as the tolerance for overlay error is continually shrinking in order to manufacture next-generation semiconductor products. Run-to-run control has become an attractive solution to many control problems within the industry, including overlay. The term run-to-run control refers to any automated procedure whereby recipe settings are updated between successive process runs in order to keep the process under control. The following discussion will present the formulation of such a controller by examining control of overlay. A brief introduction of overlay will be given, highlighting the control challenge overlay presents. A data management methodology that groups like processes together in order to improve controllability, referred to as control threads, will then be presented. Finally, a discussion of linear model predictive control will show its utility in feedback run-to-run control.

It is a common practice in today's microelectronics manufacturing facilities to have many different products and processes run on each processing tool. This is caused mainly by the high capital costs associated with the tools and the limited capacity of the facility. A run-to-run controller relies on having a model that is consistent from run to run. When the different processes run on the tool are significantly different, the controller may behave unexpectedly because each change to a new process can appear as a large disturbance. In addition, it may take several successive runs of a given process for the controller to stabilize, but this cannot happen if the processes change too often. Ideally, the controller should be able to determine optimal settings for all processes that must run on the tool, regardless of the order in which they appear. In an adaptive control strategy, an online system identification scheme runs along with the controller and constantly adjusts the model so that it mimics the true behavior of the system. One very difficult task in this situation is determining whether observed errors in the output are due to errors in accounting for tool differences or for product differences. This discussion will outline a scheme for deciding which model parameters are in error and performing the correct model updates.

Feed-forward and feedback control are used to compensate for variations caused by processes or equipment. The variations may be due to e.g. aging or shift and they may occur within a single process step or within a process sequence. The application of advanced process control methods offer the possibility to reduce deviation of process centering and, therefore, improving process capability. In this work, we investigated the feed-forward concept applied for a lithography/etch sequence to control the deviation of the critical dimension of polysilicon wires and also the implementation of feed-forward control into existing manufacturing execution systems.

One of the major problems for DUV resists is linewidth change owing to Post Exposure Delay (PED). Linewidth is mainly induced by acid diffusion during exposure and baking. Based on the mechanism of the neutralization of organic base and photo generated acid, a model had been generate din our previous study to describe the linewidth variation for different PED times. The derived equation can calculate the minimum elapse time, which will cause linewidth variation to exceed the specification of a specific CD. This work concludes that the smaller CD received a higher percentage of CD variation under PED for an isolated line pattern. Therefore, the minimum acceptable time for the smallest CD can be obtained based on +/- 10 percent of the nominal CD.

This presentation describes the introduction of a fault detection and predictive maintenance strategy into the Diffusion area of a semiconductor manufacturing facility. The goal of the fault detection and predictive maintenance strategy is to maximize tool availability for production while minimizing the risk to product. The predictive maintenance methods allow the user to increase the elapsed time between maintenance activities while minimizing the risk of unexpected equipment failure. The predictive maintenance methods are based on the use of a statistically based fault detection system. The selected equipment parameters are monitored throughout the run for drift beyond established threshold limits. Fault detection is reported directly to a maintenance planning and scheduling application which in turn sends a message to the operating personnel. An option is available which will inhibit the use of the tool until the maintenance activity has been completed. A major part of this project was the identification of equipment parameters for monitoring, the statistical methods used in the analysis and the determination of the threshold values at which t originate a maintenance activity. The decision process leading to the definition of these factors is discussed.

As the line-width goes sub-100 nm, process windows for al lithographic processes become smaller. Process control and monitoring of the process parameters become increasingly important and necessary as small variation in process variables such as exposure dose, temperature, resist thickness, developer concentration, etc. may cause the final critical dimension to differ from the specification.

Wafer-charging monitors based on MOS capacitor antennas are a popular tool to assess the ion-implantation induced charging in IC manufacturing. We have found that silicidation of polysilicon antennas prior to ion implantation exposure simplifies the test tasks and shortens the cycle time for tool monitoring. The paper presents comparison of ion-implantation charging obtained on polysilicon as well as polycide gate capacitors. For polysilicon antennas a rapid thermal treatment was applied to reinstate polysilicon conductivity and enable electrical testing. The silicided gate electrode offers better protection of the thin oxide against direct ion bombardment and displacement damage in the oxide. The data shows that silicided capacitors suffer less charging under the same implantation process. This makes polycide MOS sensors less sensitive and requires additional calibration with respect to real charging levels occurring during implantation of bare polysilicon gates. The effect is further studied with respect to real charging levels occurring during implantation of bare polysilicon gates. The effect is further studied with respect to charge generation through the emission of secondary electrons from the surface of polysilicon and polycide under ion beam bombardment.

Small signal non-contact ac-SPV method for monitoring near surface doping (NSD) in silicon has recently been introduced in commercial diagnostic tools. This technique has the advantage of producing fast, non-destructive full wafer measurements. High chopping frequency light with a submicron penetration depth is used to generate small SPV signal and this signal is in turn monitored using a transparent pickup electrode. Under certain conditions, the magnitude of this ac-SPV signal is inversely proportional to the depletion layer capacitance. If a depletion layer barrier height is known, this allows the calculation of the concentration of ionized donors or acceptors in the depletion layer. NSD measurements by ac-SPV method were typically done for doping concentrations up to about 10¹⁶ cm^-3. Only recently this range has been extended to 10¹⁸ cm^-3, making it a very attractive technique for monitoring low and medium dose implants and especially for wafer scale mapping of implant uniformity and implant activation efficiency. This paper addresses three issues that are critical for extending this technique to monitoring of production wafers in IC-processing, namely: 1) a quantitative correction for oxide reflectivity, 2) the fundamental and practical problems in reduction of the SPV probing site to below 100 micrometers , and 3) sensitivity of the technique to small variations in the implantation dose.

Thermocouples are a widely used sensor in Semiconductor manufacturing because of their relatively low cost and ease of use. Most users in an attempt to improve measurement accuracy, purchase pre-calibrated thermocouples and establish replacement or re-calibration schedules. Unfortunately, these processes are often not based on actual thermocouple drift data, but most likely base don historical practice, opinion, or misinformation. This paper addresses the simple, but often misunderstood physics behind how thermocouples 'feel' temperature, and models the various sources of error that can occur with this sensor. Using this information, this paper outlines a procedure for ensuring accurate measurement in a production environment. The electronics used to convert the thermocouple signal to a temperature is discussed, along with how thermocouples are calibrated and why in-situ calibration in the field is not practical. Sources of measurement error are modeled including incoming calibration error, manual data-entry error of calibration data, tool or electronically induced error, and drift over time. These sources of error are described and modeled for 'type R' thermocouples, the most widely used thermocoupled for high temperature diffusion applications, using over five years of manufacturing data from over 70 horizontal and vertical diffusion furnaces.

Accurate and reliable CD measurement is one of the most important goals of CD metrology. Today, most CD measurements are performed utilizing the SEM. One of the most commonly employed measurement detection algorithms is the Threshold method. This method is most useful for measuring CD when the structure begin measured consistently produces stable peaks in the secondary electron induced image intensity profile. However, the intensity profile becomes more complicated when there are multiple peaks whose peak heights are neither stable nor fixed in position. In this case, accurate and reliable CD measurements are difficult to achieve. In this paper, a novel technique of pre-dose and re-dose electrical beam treatment will be described. The technique is effective in producing reliable intensity profiles resulting in accurate CD measurements, and the recipe developed using the technique runs fully automated. The technique has been applied in our factory with success.

The success of advanced IC interconnect schemes using copper depends on control of CU surface oxidation, since even a few monolayers of Cu_xO can dramatically increase Cu via resistance and reduce Cu-to-dielectric film adhesion. This level of control requires an accurate, in-line method of determining Cu oxidation state and Cu_xO film thickness. In this paper, we apply spectroscopic ellipsometry to characterize Cu films that were oxidized and then reduced under controlled thermal and plasma conditions representative of IC processing. Oxidation and reduction was carried out on single layers of sputter-deposited Cu as well as on Cu films deposited as part of multilayer thin film stacks. Ellipsometer models were developed and optimized for application to both Cu and copper oxide films. The correlation of ellipsometric data with Rutherford backscattering spectroscopy and x-ray fluorescence analysis of similar films is also discussed.

X-ray reflectometry (XRR) has been used in R and D for many years to provide thickness, density and interface roughness measurements of thin films and thin film stacks, independent of other material properties. However, because obtaining data with conventional XRR is very time consuming, it has not until recently been viewed as a practical tool for semiconductor material and process development. In this study, a new rapid x- ray reflectometry (RXRR) technique, capable of obtaining thin film structural data from blanket or patterned wafers in seconds, was used to optimize process development of various materials used for Cu Damascene processing. CU seed and Ta/Tan barrier films were measure din as-deposited film stacks, and the result used to optimize deposition rate and cross-wafer deposition uniformity for various PVD processes. Correlation with Rutherford backs-scattering (RBS) measurements demonstrated that the RXRR measurements provided accurate thickness measurements independently for both the Cu seed and underlying Ta/Tan films. Next, thickness and density measurements were obtained for reactively sputtered TaN and TiN films, and then correlated to the CMP properties of the films., Thickness measurements were used to calibrate the CMP rate for each film, while density differences were correlated to the reactive PVD process conditions, including gas flow rate and wafer temperature. Finally, the densities of various low-k dielectric materials were measured and used to estimate percentage residual porosity, which can be used to predict k value for the film.

This paper reports progress on the integration of spectroscopic ellipsometry (SE) in the cool-down chamber of an applied materials Epi Centura Cluster System. It has been shown that new spectroscopic ellipsometer can measure wafers through a window with non-normal incidence. Correction procedures have been established and tested with measurements on standard oxide samples. Strained SiGe layers can be characterized in terms of Ge content and layer thickness indicating the feasibility of the integrate metrology technique. Further measurements are in progress with the system installed in a fully operating cluster tool. Future work will focus on improving the throughput by, for instance, rapid spectral data acquisition and application of novel algorithms to extract layer parameters during the automatic cool-down sequence.

The thickness and complex refractive indices of the thin films on a silicon wafer during lithographic imaging are critical factors affecting the processing of integrated circuits. The inorganic materials involved, such as the silicon substrate and inorganic anti-reflection coatings, are usually well characterized or present few difficulties. The optical properties of organic materials, such as photoresists and anti-reflection coatings have been more difficult to determine with confidence. In general, for each material on the substrate, three values need to be determined; they include the thickness and the real and imaginary parts of the refractive index at the exposure wavelength. Single measurements of reflectance or ellipsometric parameters do not provide sufficient degrees of freedom for determining these three unknowns. Typically, this problem is resolved by collecting reflectance or ellipsometric data over a range of wavelengths. However, because n and k functions of wavelength, two additional unknowns are present for each additional wavelengths. This problem is typically resolved by fitting n and kn to various spectral functions in order to reduce the number of unknowns. Unfortunately, the functional forms used are frequently inappropriate for the organic materials of interest. The essence of the new method is the use of data from coatings having different thicknesses in order to provide the degrees of freedom necessary for a solution. This is achieved at a single wavelength and thereby avoids the spectral model fits that are frequently fraught with problems. The new method is demonstrated by determining thicknesses and n and k values at the exposure wavelength for a photoresist and an anti-reflection coating designed to be used with 193 nm exposures. The optical properties of two 248 nm anti-reflection coatings are also determined over a spectral range.

Processing two consequent layers on the same exposure tool had long time been considered to be the terminated solution for overlay control by photolithography process engineers. Such measure would take advantage of excluding Lens distortion contribution to overlay performance and lead to only mask error, alignment accuracy, stage accuracy consume the overlay main budget. But in practice, large overlay error still could be observed even single machine run on scanner that could not be tolerable by current device requirement. How come. Reticle interference effect with alignment laser beam had been demonstrated to dominate such large overlay error contribution. Solutions to control and eliminate this effect on CI foundry fab were also presented. An advanced feedforward/feedback control system would compensate such error in advance. Also ARC coating on mask quartz side that would eliminate the interference effect will be mentioned and proved to be effective way for better overlay control performance.

A wealth of advantages arise form breaking down the overall yield into yield components that are easier to work and closer to the manufacturing line environment. We present in this paper our strategy to attempt the 100 percent yield explanation on our fab and the process of building a pareto that quantifies the impact of each yield component. The most critical one, the defect related, is accounted by a set of knowledge-based automatic software tools that operate in our fab. They quantify it and break it down into the by layer, by defect size and type contributions. The step forward of communication and deployment of this yield strategy is a key topic also discussed in the paper. On our way towards the 100 percent understanding of yield we have learned how to better manage it and taken advantage of many more opportunities to improve it. The strategy has shown to work both for new and mature technologies in our manufacturing line in Lucent Technologies Madrid.

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Q_bd, and breakdown electric field, E_bd, at parametric level and E_bd and interface states density, D_it during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

In this work, plasma induced damage resulting from high density plasma undoped silicate glass and fluorinated silicate glass (FSG) deposition processes was studied. The extent of the plasma damage due to the two HDP processes were characterized based on 0.18 micrometers transistor test structures with different antenna ratios. Our results show that the plasma-induced damage from HDP FSG is greater than that from HDP USG. We have developed a novel integration scheme that is effective in reducing the damage from HDP FSG down to levels comparable to that of USG.

Integration of both extremely small-dimensioned metal lines and large-dimensioned metal structures may cause reliability problems due to thermomechanical stress between the intermetal dielectric and the multi-level-metalization. The paper reports a case study and shows a problem solution approach: due to thermomechanical mismatch of aluminum and Si-oxide, metalization processing should not be used for both small and large structures. This may cause cracks and generate intermetallic shorts as a reliability problem.

Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

Metastability has been long documented as a problem in digital systems with asynchronous inputs. This problem has been analyzed in CMOS latches using a 2nd order small signal model. However, uses of a third order model taking into account that the effect of the feedback transistor. While second order models are helpful in understanding how to model the circuit in the region, they do not provide sufficient information to accurately predict the essential parameter (tau) the maximum time at which the circuit may leave the metastable state. The only way to analyze such a circuit is to simulate it, using a simulator that combines small signal and large signal analysis. Future work on metastability will include modeling the feedback transistor as a resistor, and determining whether such a model is a reasonable simplification. The simulator can be modified easily to model small transistor geometries devices and to study the effect of large signal noise, such as ground and power supply bounce, on metastability. The model may also be applied to an interconnect model to improve delay and cross-talk simulations.

Beginning at observation that if a Goldthwaite diagram is draw a line (lambda) equals constant, all the curves of this diagrams are cutes in a point that are a value equal with that constant. If the constant is choose the maximum admissible value of failure rate multiplied by time of qualified life, the intersection of (lambda) line with the different (sigma) _i curves, corresponding for a certain semiconductor devices, can determinate the value of median time t_mi that corresponds t functioning temperature. In the laboratory was achieved accelerated aging for some semiconductor devices types. Parameters of accelerated aging were chosen so that they are not introducing any new failure mechanism non typical for normal functioning. Necessary time for accelerated aging test of this device was determinate using Arrhenius equation, for acceptance quality level 5 percent. For those devices, the time accelerated aging was determinate around on hundred hours. The value of failure rate certification was 10²-10³ Fits. The obtained results were validated therefore comparing then the results obtained using classical method for reliability testing, having the duration of 1000-200h. In this mode we can solve the problems of a long and expensive testing time before launching on the market a new devices.

Metal shorts are the second burn-in failure cause in our production line. Stainless Steel (SS) particles are found in most of the analyzed metal shorts. This work presents the corrective actions implemented to detect, prevent and correct SS particle sources in our production line. The SS particle corrective actions cover from in-line KLA-ADC detection, to hardware/process modification and new wafer backside contamination controls. The main sources are due to 1) the lack of some final point filters in some NEW/old machines; 2) damaged SS mobile pieces; 3) wafer backside contamination. The back-side contamination comes form SS hardware pieces that need to be replaced by other with SS-free surfaces; as the standard LAM-TCP APM-chick. A positive impact in the burn-in failure rate has bene seen after implementing those corrective actions.

Electronic packaging is increasingly becoming a vital part of the electronics industry, representing a key barrier to cost reduction and performance improvement. Flip-chip joining using conductive polymeric adhesives have been identified as a key technologies for future electronics assembly and manufacturing. The purpose of this study is to investigate optimum conditions to achieve the best electrical performance in conductive adhesive joints. Therefore, the quality and reliability tested in conductive adhesive joints were performed at various current densities with different curing conditions. Differential scanning calorimetry and resistance measurement were used to monitor curing condition in conductive adhesives. Accelerated life testing of conductive adhesive joints made of the selected conductive adhesive using different curing conditions was performed with various current densities. The current-induced degradation of conductive adhesive joints was investigated through optical microscope and resistance measurements. Results show a shift in contact resistance depending on curing condition and current density. The contact resistance shift is found to be due to the migration of conducting particles in the adhesive joint.

Memories are especially convenient for defect analysis and yield improvement studies because large portions of a memory die are arrange din a regular array that is connected for external testing in such a manner as to facilitate determination of the physical location of failing memory elements. It is frequently desirable to compare the physical location of failing elements with the location of defects identified with in-line inspection equipment as well as to compare the locations of in-line defects identified on different process layers. This process of comparison is often referred to as creating overlay plots, or frequently just overlays. A practical obstacle to the creation of overlays is that the absolute position of locations on wafers is not accurate in typical inspection equipment with the result there are offsets between the same defect as it propagates between layers and between the reported defect location and resultant location of failing bits on a die.

We have established several applications for the use of Raman spectroscopy in the microelectronics-manufacturing environment. The two primary applications are 1) monitoring thin films and 2) analyzing contaminants. Thin film applications include monitoring cobalt silicide phase transformation and thickness, and crystallinity changes in polysilicon. The same instrument has been used to collect fingerprint Raman spectra of contaminants that can be identified by matching to library or bulk materials spectra.

The detection of surface particles is an important part of contamination control in semiconductor manufacturing. However, the minimum particle size required to be detected has been becoming smaller as integrated-circuit geometries shrink. Current visible-light detection systems can detect particles down to around 50 nm in polystyrene-latex-equivalent size and so are adequate for current geometries, but in the near future even particles as small as around 20 nm in diameter will become significant contaminants. This is beyond the capability of current visible-light scanners, but previous work has shown that deep UV scattering by such particles should be sufficient to enable their detection. Consequently, we have constructed a deep/vacuum UV scatterometer capable of measuring scattering from semiconductor samples.

This paper describes the application of model-based principal component analysis (MBPCA) to the identification and isolation of faults in CMOS manufacture. Some of the CMOS fabrication processing steps are well understood, with first principles mathematical models available which can describe the physical and chemical phenomena that takes place. The fabrication of the device using a known industrial process is therefore first modeled 'ideally', using ATHENA and MATLAB. Detailed furnace models are used to investigate the effect of errors in furnace control on the device fabrication and the subsequent effect on the device electrical properties. This models the distribution of device properties resulting from processing a stack of wafers in a furnace, and allows faults and production errors to be simulated for analysis. The analysis is performed using MBPCA. which has been shown to improve fault-detection resolution for batch processes. The diagnosis method is demonstrated on an industrial NMOS transistor fabrication process with faults introduced in places where they might realistically occur.

Sub-micron defects seen on Si wafers mainly in Electrically- Alterable-Read-Only-Memory products were investigated. These surface defects are detected by KLA2133 inspection tool only after Poly-Si decoration, and appear in a drying spot shape or scattered. These defects are seen in the CMOS parts of the device only. SEM and EDS analysis showed these defects are Poly-Si residues. The drying spot shape appearance of the defects seen in KLS2133 and optical microscope show these defects initiated form wet operations followed by drying. An experimental simulation was carried out to locate the source and mechanisms of these defects, which repeatedly appear during the fall. A strong correlation of these defects formation to excess humidity is shown in this paper. The experimental results indicate these defects are related to CMOS operations, resulting from micro masking.

Discolored bondpads and poor adhesion or non-stick failure during bonding was investigated. The bondpads looked either brown in color at corners or just discolored without brownish corners. SEM inspection showed such bondpads had porous surface that was worse at corners. EDX, FIB and Auger Electron Spectroscopy (AES) were used to analyze and identify the root cause. Failure analysis showed that the discolored bondpads were caused by the formation of aluminum hydroxide. This process was an oxidation or corrosion process that could not be avoided when bondpads were exposed to atmospheric environment. EDX analysis further confirmed the existence of Al-O chemical bonding. FIB/SEM analysis showed clearly the porous layer grew thicker towards the bondpad edge by consuming more aluminum. The layer of aluminum hydroxide on the bondpads created a barrier for good bonding. It is the responsibility of both fab and assembly plant to take preventative action to avoid the excessive exposure of bondpads to moisture during manufacturing.

The reduced depth of focus (DOF) caused by higher numerical aperture (NA) is making the accuracy of best focus measurement increasingly important. A new overlay pattern is developed herein to precisely measure the best focus of lithographic tools. Specially designed 'bar-in-bar' (BIB) was employed to obtain the best focus by using the opposite shifting direction of inner and outer bars when defocused. The inner and outer bars are composed of various pattern sizes. When defocused, the shrinkage of the smaller patterns is more significant than that of the larger patterns, thus causing the center of gravity to shift. The distribution and pattern sizes are optimized to obtain high reproducibility and sensitive position shifting for various defocus conditions. Employing the special BIB pattern, the best focus, tilting and field curvature can be easily measured via the conventional overlay measurement tool. By adding the special BIB to the scribe lanes of the production wafers, the best focus and tilting of the stepper can be obtained when measuring a layer-to- layer overlay shift, and can then be fed back to the stepper as a reference for following processing wafers.

Interest in SiC nanopowders has been growing due to the possibilities for using their nonlinear optical properties. The objective of the present work was to investigate these properties through PISHG and photo transparency measurements taken on structures consisting of nanopowders deposited onto quartz surfaces. The relation between structural parameters, such as hexagonality and external forcing signals, such as pressure, PISHG and photo transparency was established. The high sensitivity of SHG to pressure suggests that the material investigated may be suitable for application in contactless pressure measurements.

This paper presents new technology sensors - helical sensitive elements (HSE) with layered filling. The use of HSE for RF- measurement transducers makes it possible quite efficiently to monitor and measure parameters of various industrial processes and materials. Difficulties arise when monitoring and measuring parameters of liquids such as the conductivity and the continuity of flow, and also the properties of materials with a large relative permittivity (epsilon) or permeability (mu) , such as ferrites. This is caused by the strong screening action of the monitored material or medium having high values of (epsilon) and (mu) on electromagnetic field of the slowed wave in the HSE. As the conductivity increases, the screening becomes even stronger, and this leads to a reduction in the sensitivity and measurement accuracy. The solution of such problems requires the creation and modeling of more complex designs of sensitive elements in which the screening action is weakened. Such an effect can be achieved by matching the field of a hybrid slowed wave to the medium being monitored, utilizing HSE base don layered magnetic and dielectric structures with a smooth variation of the electrodynamic parameters.

Film planarization process, of importance in semiconductor IC manufacturing, results from mutual competition between three forces: capillary, viscous, and gravitation. In this communication we compare, using simple geometric arguments, the order of magnitudes between the capillary force and a generalized centrifugal/gravitational force acting perpendicular to the surface. For patterns of sub-micron dimension and conditions similar to BPSG reflow and photo-resist coating we found that, within instrumental accessibility, the centrifugal term is much smaller than the capillary term. We conclude that the centrifugal/gravitational forces affect global patterns, i.e., with dimension larger than 1000 micrometers , while the capillary force dominates the sub-micro leveling process.

A dual polysilicon gate structure is required to increase the circuit speed and the packing density, as well as the low-power operation as the design rule of CMOS scales down to sub- 0.25micrometers . In order to get the superior device performance of 0.18micrometers logic device, we need to do the gate implantation prior to polysilicon etch. The critical dimensions (CD) different between NMOS and PMOS during polysilicon gate etching needs to be reduced for matching the design drive current of NMOS and PMOS. In this work, the pressure, the bias power, the total flow of CF₄ and Cl₂ and the N₂ flow are used for the investigation of 0.18micrometers device during the dual gate etch. After optimizing all etch parameters, the CD offset is small between NMOS and PMOS. The vertical profile, the small bias, and CD micro-loading are obtained using in-situ BARC and polysilicon etching. The result of pitting free, stringers free and notching free after dual polysilicon etching is achieved, and the remaining thickness of deep UV photoresist at shoulder is about 800-880A. From this study, both good performance device and the process controllability are obtained with in-situ bottom anti- reflective coating and dual polysilicon gate etching.

Oxide and dielectric etch, polysilicon etch, and metal etch, in situ strip and stand-alone ash processes for 300mm wafers were developed on a tool ste in SEMICONDUCTOR300 and tested for robustness using a 0.25(mu) 64Mb DRAM device. The process recipes were developed from reference scaled-up recipes. The oxide and dielectric etch tools used magnetically-enhanced reactive ion etching. They polysilicon etch tool chambers were high density plasma configurations. The metal etch tools used high-density plasma chambers and have an in-line resist strip module to prevent corrosion. Stand-alone ash tools were used for all other photoresist strip processes. For each application, at least two 300mm tools from different suppliers were tested. This paper discusses process and tool interactions affecting operational robustness and stability. Process and hardware evaluations were also done during extensibility testing using smaller linewidth features.

As the semiconductor industry begins its transition to its next wafer size threshold of 300mm, several key factors are becoming significant. Solving the problems surrounding these factors is critical to achieving a 30-40 percent cost savings over 200mm wafer integrated circuit manufacturing. These problematic areas involve automation, equipment readiness, and process performance. 300mm factories will differ from 200mm versions due to the automation level, lot size choices, and factory sizing targets in terms of wafer starts. This paper discusses these areas from data acquired at SEMICONDUCTOR300 in processing a 0.25 micrometers 64Mb DRAM device. Current performance is discussed for each semiconductor manufacturing tool functional group. These data include performance cost of ownership, on automation and computer integrated manufacturing, and process capability.

This paper presents the implementation of Triant Model Ware on Tegal 90X series etchers to reduce wafer scarp on technologies associated with this tool set. Triant Model Ware becomes an integrated process control module of the Tegal etcher by means of a tool side computer interfaced to the Tegal system. Interface hardware provides the necessary communications interconnect for monitoring various sensor outputs associated with wafer processing values. Data acquisition hardware is implemented to provide real-time sensor information to support alarming conditions during signal monitoring. Models, associated with Triant Model Ware, monitor pertinent sensor conditions during wafer processing to identify possible process deviations attributable to scrap. Triant Model Ware examines process signatures on the Tegal etch system capturing potential equipment and process deviations reducing scrap on material on this tool set.

Conventional methods of CD-limited yield and process capability analysis either completely ignore the intra-die CD variability caused by the optical and process proximity effects or assume it is normally distributed. We show that these assumptions do not hold for the aggressive subresolution designs. The form and modality of intra-die poly-gate CD variability strongly depend on the defocus and exposure values. We study the influence of process parameters on strong phase shifted and binary mask designs. A definition of a CD-based process window is proposed to capture the 'proximity signature' of the design and its dependence on process parameters.

Split-Gate Flash Device, the poly-to-poly FN Tunneling for erasing and programming with poly gape, is good structure to eliminate the stacked gate issue of 'over-erase' by additional selected gate which is isolating each memory cell from the bit line. However, the overlay error is more concerned, since they require more accuracy in registrations of P1 to Nitrid and P2 to P1. The registration error, including sampling error, mask error and proximity effect, especially at edge pattern of die, result in the field related low yield because of cell leak issue and cell punch-through. From experiment result, different SERIF design shape, the additional OPC, make different CD performance to improve the different direction of registration error. Mask error and proximity error can contribute overlay shift between cell and box-in-box of overlay monitor frame, so the layer shift addition should be considered those intrinsic error and we add scaling and sampling monitor to avoid the registration error of site to site or wafer to wafer.

In this work, we describe some of the problems that can affect the yield at Wafer Probe, and at the checks performed by a software that we have developed to ensure the good quality of the wafer probing. Most of the problems at Wafer Probe appear in the same way and by detecting their pattern, even not knowing the exact source of the problem, we can prevent the product and its yield form being affected. The most common patterns of failures are: a certain category failing consecutively, a certain test failing above statistical limits expected, based on the historical results of that product, same wafers yielding different in two different testers, and results in a lot going worse wafer by wafer. For addressing these issues, we run in real time a set of programs at the end of every wafer tested. These programs generate alarms and tell actions to the operator when the above problems are detected.

Three types of photo developing and developing-like defect on DUV process were presented in this paper. Scumming of photoresist on nitride film during developing process which was resulted from interaction between by-product of nitride film deposition process and resists that could not be removed by developer and water rinse. Those scumming developing defect would lead to bamboo shoots-like residue after etching that could cause microscratch during STI CMP. Either film treatment with HF vapor clean before photoprocess or adding extra rinse after hard baking can effectively eliminate those scumming defect. Splash from developer cup during water rinse process which appearance on non- resist area were crown-like on hydrophobic film could be reduced by extra rinse process after hard baking. Also owing to high contact angle between surfactant type developer and resist, discolor appearance on resist are would be formed after developing. Method to solve this issue was to apply developer as pre-wet before developing process.

Despite considerable progress achieved over the past few years in understanding ultrathin oxynitrides, several fundamental questions, in particular the oxynitridation mechanism, and the mechanisms behind the beneficial role of nitrogen, are still not well understood. To better understand the explanations which have been proposed for the phenomena specific to silicon oxynitride and for the nature of the defects, a study of the electron structure of a MOS system using silicon oxynitrides as the gate oxide and based on a first-principle molecular dynamic method, was carried out.

An investigation of effects of variables of LPCVD process and subsequent processes on residual stresses in highly doped polysilicon film is carried out. A pre-annealing process for as- deposited polysilicon film was introduced before boron doping in order to be able to change magnitude of residual stress in a larger range. The influence of the pre-annealing on the residual stresses in boron doped polysilicon film was studied. The test results show that boron doping process induces significant residual stress only in LPCVD polysilicon films which are deposited at lower process temperature. There will not be significant doping stress in the polysilicon films if the deposition temperature is higher than 620 degrees C or pre- annealing temperature before the doping is higher than 1000 degrees C. The larger change range of the film stress can be obtained by to change pre-annealing temperature before doping. This method will be useful in the stress control of a multi-layer diaphragm structure.