In semiconductor manufacturing there is a requirement to control the production processes in order to safeguard the final product electrical performance and wafer yield. As technology increases the number of photo and metal layers increase and the number of production processes to control increases proportionately. It is very important that engineers have the appropriate level of SPC in place at each process such that an alarm is raised and production stopped if a real process excursion takes place. Over control, on the other hand, can actually induce variation or lead to a situation where processes are often stopped due to false alarms. Too little or too much control is unacceptable and either could lead to failure due to yield busts or high production costs. This paper describes how a robust SPC model can be installed and, just as importantly, maintained, in an environment where few engineers are required to manage thousands of process control charts.

Time to market is the major driver for today's semiconductor products. Technology and product development must occur in parallel if a competitive time to market is to be obtained. Correct use of Technology Computer Aided Design (TCAD) tools can reduce the effort of technology development by quickly examining the process design space and highlighting the more favorable process options. An example of the use of TCAD tools within technology development is illustrated here in the development of a high voltage module for a Smart Power process. The major challenge in any Smart Power process is the trade-off between maximum breakdown voltage and minimizing the on-resistance of the process. The technology uses an N Channel Vertical Double Diffused MOSFET with a breakdown voltage of 50 Volts and an on- resistance of 0.224 (Omega) .mm². The high voltage module must sustain a breakdown voltage of 80 Volts with minimum increase in the on-resistance. A Design of Experiment approach to both device layout and process technology development is used to ensure that both layout and process sensitivities are rigorously considered in designing-in the manufacturability of the technology at the development stage.

In the modern VLSI manufacture, the process control to eliminate yield loss can not be over-emphasized in multilevel integration circuit manufacture. The scrubber clean is widely used to remove the particles for yield improvement. When the wafers run through SOG-CUR(SOG curing) process, SOG film will crack at wafer edge and produce flake type particles dropping on the processing wafers, which will cause the yield loss dramatically. The scrubber clean was applied to remove these particles, however, it was found that there were some production lots suffering CP yield loss in IDDQ failure caused by the problem scrubber clean machines at SOG-CUR scrubber clean stage. It was suspected that the wafers after processing SOG-CUR is easily damaged by the ESD charge induced from scrubber clean process. The possible root cause as well as the in-line monitor procedure for the ESD charge damage is studied in this investigation. After improving the scrubber clean process, the yield and IDDQ failure is recovered.

Manufacturing is typically limited to fabrication of parts at a single location, with some sites assembling components from parts made elsewhere. The age of ubiquitous information transfer has made it conceivable to distribute manufacturing geographically, in order to provide access to unique manufacturing capabilities in a flexible manner. If the overhead of a distributed manufacturing network can be adequately reduced, it has the potential to make previously cost ineffective low volume and custom applications economically feasible. The MEMS-Exchange is an infrastructural service available to the domestic microelectromechanical systems community that provides an interface between MEMS designers and microfabrication facilities (academic, commercial, and government labs) which allows designers to develop and exercise custom process sequences in order to realize their devices.

In general process, there is a polymer removal step by CR-SPM (Caros' acid clean) or STD clean (Standard Clean) after spacer etching. Sometimes the particles are found by KLA scan right after CR/STD clean, but not found after spacer etching. After studying the characteristics of particles, the formation of particles is due to the polarity of OD area (active area) surface changed from hydrophilic to hydrophobic and hydrophobic particles that contained in CR/STD tank are attached on OD area surface. In this report, a whole new in-situ polarity modification concept that changing hydrophobic Si surface to hydrophilic SiO surface by adding a very short O₂ plasma treatment right after spacer etch is presented. The concept is evaluated in bare silicon and TEOS control wafers, and the results reveal that O₂ plasma treatment can avoid particle attachment not only effectively but also efficiently. By the experiment, in-situ five seconds' O₂ plasma is implanted in spacer etching recipe and two products are split to test. The WAT (Wafer Acceptance Test) and yield of split are comparable with standard condition.

We present in this paper a new in-situ technique we have developed to monitor and to control broad ion beam processes. The base of this technique is to capture, with a Peltier-cooled CCD camera, the light emitted when the ions hit the surface of the wafer during the process. The intensity of the light and its distribution across the irradiated area is calculated from the CCD camera picture. In our processes, we measure the intensity level of the light emitted to monitor the growth or the etching of silicon oxide films by ultra slow single and multicharged ions. We also measure the intensity distribution of the light emitted from the irradiated area to control and monitor the broad ion beam uniformity. The possibility to use an in-situ monitoring system is an advantage for the equipment we develop for semiconductor manufacturing, as it will give an immediate control on the quality of every processed wafer.

Precise characterization of high k gate dielectrics becomes a challenging task due to the very thin thicknesses (< 3 - 4 nm), which will be needed in the next generation integrated circuits. Conventional techniques such as spectroscopic ellipsometry in the visible range becomes difficult to use alone because of the great correlation between thickness and optical indices. To overcome this problem the following strategy is applied. First, grazing x- ray reflectance is used on all the samples to extract the different layer thickness using a simple model. Second, spectroscopic ellipsometry is applied and the results fitted with the structural models deduced from the x-ray results. In this conditions a precise structural model is built which can take into account the interface and surface behavior all factors that become critical for this range of thickness. This approach is applied to various types of oxide nitride gate dielectrics and ZrO₂ films. In the fist case, the nitrogen content of the films can be precisely determined and also the inhomogeneity in depth of the layers in some cases. Interface problems can also be detected on ZrO₂ films. Results are compared to x-ray photo-emission measurement in some cases.

Thermal processing of photoresist are critical steps in the microlithography sequence. The post-expose bake steps for current DUV chemically-amplified resists is especially sensitive to temperature variations. Requirements call for temperature to be controlled to within 0.1 degree(s)C at temperature between 70 degree(s)C and 150 degree(s)C. The problem is complicated with increasing wafer size and decreasing feature size. Conventional thermal system, which utilizes single or dual zone heating, is no longer able to meet these stringent requirements. The reason is that the large thermal mass of conventional hot plates prevents rapid movements in substrate temperature to compensate for real-time errors during transients. The implementation of advanced control systems with conventional technology cannot overcome the inherent operating limitation. A spatially-programmable thermal processing module for the baking of 300 mm wafers has been developed.

Aluminum nitride piezoelectric films have been grown by reactive sputtering technique on different substrates, chosen according to their attractive properties such as high acoustic wave velocity (Al₂O₃, MgO, Si) and possibility to integrate the acoustic device with the electric circuitry (Si, GaAs). We have studied the AlN properties within a thickness range of 2.1 - 6.3 micrometers by means of X-ray diffraction analysis and piezoelectric d₃₃ constants measurements, in order to define the best sputtering parameters that ensure the best quality of the AlN films.

The silicon nitride spacer technology is widely used in split gate non-volatile memory device sand flash EPROM. A tiny spacer structure is formed on tunnel oxide layer adjacent to the sidewall of floating gate electrode to prevent write disturbance that caused by reverse tunneling. But the processing is very critical for such flash EPROM devices since the dimension the SN spacer are so small. It was influenced not only by SN spacer dry etching but also later photo-resistance strip process of implantation for threshold voltage adjustment. A new method of forming tiny SN spacer by using anisotropic dry etching and isotropic wet etching was presented in this paper.

A new method for creating deep junctions extending through the whole thickness of a wafer has recently been demonstrated. Applications are in the field of high power devices. The method uses the thermomigration of melted Al/Si droplets in silicon and allows function electrical isolation. This process requires a specific Rapid Thermal Processing equipment. The purpose of this paper is to discuss the control of the process by end-point detection, that is the optical in situ detection of the emergence of the melted alloy once thermomigration is completed. For this purpose, in situ laser reflectometry and video observation have been used. Experimental results are presented and discussed.

Lithography is plagued by variations in critical dimensions and alignment. Both parameters contribute to the total overlay of one layer to the previous one. In the past, we had the luxury of using additive techniques to figure total overlay budget. Now circuit patterns have shrunken to the point that if we design a chip by adding errors, we would no longer be able to make anything. Designers today use the root mean square (RMS) of the errors to figure the spec. In turn the Process Engineer must adapt to this by finding new techniques to maintain CDs and alignment. Measuring total overlay, using statistics and RMS, we can continue to produce chips beyond the presumed capability of our tools. Measurements for CDs and alignment are fed forward to the next masking step, combined with the CDs and alignment at that step to calculate the total overlay and spec satisfaction. Using this method, parameters that may be beyond your process capability can be judged based on their electrical impact.

Traditionally, lithography critical dimension (CD) measurements with stepper de-focus and deltas in sidewall angle do not correlate well with the ultimate product measurement, namely electrical performance. It is important in etch bias control, therefore, to control more than just the physical CD. It is at a minimum, important to show how the changes in sidewall angle control at lithography relate to etch biases. This is especially important as chip geometries shrink, and the size and shape of the sidewall becomes a larger portion of the line width geometry. This makes precise CD measurements coupled with slope angle measurements, in real time, important to process control in lithography so that ultimately the desired dimension is achieved at the post etch step, and therefore electrical performance can be gauged. We will present data taken from Focus/Exposure Matrices in the form of CD measurements, in-line sidewall angle reconstruction, and electrical measurements. We hope to correlate electrical performance to post develop CD and slope sidewall angle as measured without destructive cross sections.

Rule tables for describing optical proximity correction can be derived either from practical measurements or by means of lithography simulation. This paper shows that one set of rules may not adequately apply across the whole of the image field depending on CD uniformity across the lens field. Example measurements illustrate the problem and proposals are made for its solution.

This paper examines the relative etching rates of doped and thermal silicon dioxide when using NSSL etchant, comprising of a mixture of ammonium fluoride, water and ammonium dihydrogen phosphate [(NH₄)H₂PO₄] and investigates their dependence on both temperature and mixture composition. The possible reaction mechanism is discussed and compared with the known mechanism for standard buffered oxide etchants (BOE). The observed etch selectivity and mechanisms of BOE and NSSL are also compared with the behavior of a third chemical formulation, referred to as mixed oxide etchant, which comprises of ammonium fluoride (NH₄F) solution, diammonium hydrogen phosphate [(NH₄)₂HPO₄] and orthophosphoric acid (H₃PO₄). It is concluded that no major change in oxide selectivity is observed if either BOE or NSSL etchants are used in the metal pre-clean process.

The use of junction isolation in linear bipolar ICs substantially consumes silicon area. The replacement of junction isolation with trench isolation has the potential to significantly reduce device area while maintaining high voltage operation. Deep trench isolation has been implemented on a conventional non- complementary 40V (NPN BV_ceo) linear IC process. A fully functional lower power operational amplifier has been fabricated as a technology driver. Device characterization shows that transistor leakage currents (I_ceo) and leakage between trench tubs can be made comparable with junction isolated devices. The NPN buried layer can successfully be butted against the trench sidewall without device degradation, although this is currently not possible with the NPN base. An NPN device shrink of 3X has been achieved and further development is underway to increase this towards the 4X level, where the base diffusion front touches the trench sidewall.

Environment friendly processing becomes more and more important in the semiconductor industry. One of the main targets is PFC emission reduction where, at the 0.5 to 0.25 micrometers technology node one of the main generators, beside CVD chamber cleans, is tungsten etch back using SF₆ based chemistries. This process was re characterized by a detailed three level design of experiment with special emphasis on SF₆ consumption reduction. Within the experiment, plasma power and SF₆ flow were identified as the key parameters to double that utilization, indicating that the process is dominated by dissociation of SF₆. Additionally a lower pressure process turned out to remove tungsten very effective during over etch, decreasing gas consumption further. The main issue with the new process was the formation of tungsten residues, which are attributed to micro masking by material sputtered from the upper electrode. The tungsten residue problem could be overcome by adjusting Ar/SF₆ ratio. The new process revealed not only lower SF₆ consumption by a factor of two, but also higher throughput. This means sometimes environmental protection can be also combined with economic benefits. Actually the new process is ramped up in mass production.

In the manufacture of integrated circuit device, it is necessary to maintain an ultra clean wafer surface in order to obtain high quality device. NH4OH-H2O2(APM), HCL- H2O2(HPM), and H2SO4-H2O2(SPM) are efficient in removing organic or metallic impurities, but these cleaning processes will leave the surface of wafers in a hydrophilic state due to the oxidizing nature of peroxide (H2O2). There are at least two problems associated with this fact. If the surface of the wafer is an un-densified tetraethoxysilane (TEOS) film, this film will absorb moisture hydrogen from the ambient or the wet cleaning process. Also, the hydrophilic surface could retain some impurities from the cleaning chemicals. The moisture and impurities will be converted into volatile defect and act as a mask during the subsequent polysilicon etching process and the polysilicon residue is resulted.

This work describes assessment of `long range' and `short range' developer depletion using production and test reticles respectively. Long range developer depletion refers to the case where development of large unpatterned field areas remote from critical dimensions influences their size, whether the field areas are exposed or unexposed. Results show no significant effect at the 0.35 micron scale. Short range developer depletion refers to the case, on test reticles, where single lines are defined in large open field areas or in a small open box set within a dark field area. Differences in CD's can be readily measured on test reticles and attributed to the effects of developer depletion.

New results of high pressure investigations of semiconductor compounds PbX (X-S, Se, Te) and novel data of thermoelectric power S of high pressure phases are presented. In vicinity of metal-semiconductor phase transformations at high pressure P above approximately 2.5, 4.5 and 6.5 GPa, respectively, where samples became a mixture of phase inclusions, disproportional variations of electrical resistance and S were observed. Analysis of properties changing was made by using of oriented inclusions model with variable phase configuration. The using of high pressure set up with sintered diamond plungers made it possible to investigate as electronic and also configuration parameters of phases for heterophase systems at high pressures.