Paper
24 July 2001 Configuration subsystem design exploration for domain-specific reconfigurable technologies
Milan Vasilko
Author Affiliations +
Proceedings Volume 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III; (2001) https://doi.org/10.1117/12.434384
Event: ITCom 2001: International Symposium on the Convergence of IT and Communications, 2001, Denver, CO, United States
Abstract
This paper presents an example of using a reconfigurable systems CAD tool (DYNASTY Framework) for the design exploration of various configuration subsystems in a specific reconfigurable technology. Given a set of application domain benchmarks, it is possible to examine whether a selected device configuration subsystem provides performance suitable for the targeted application domain. The approach is based on a `plug-in' technology server, implemented in the DYNASTY Framework, which allows for many different configuration subsystems to be modelled at high level. The feasibility of using a specific configuration subsystem for the selected application domain can be assessed without the need to produce transistor-level device models. As an example, the paper presents an evaluation of partial reconfiguration performance for a simple design with two arithmetic modules. The design reconfiguration performance is evaluated for three different configuration subsystems (parallel random-access, frame-based and context-switched) implemented on top of the Xilinx XC6200 device architecture.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Milan Vasilko "Configuration subsystem design exploration for domain-specific reconfigurable technologies", Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); https://doi.org/10.1117/12.434384
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KEYWORDS
Computer aided design

Logic

Instrument modeling

Switches

Algorithm development

Detection and tracking algorithms

Field programmable gate arrays

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