Variable length decoder on dynamically reconfigurable cell array processor

Kiyotaka Komoku; Takayuki Morishita; Fumihiro Hatano; Iwao Teramoto

doi:10.1117/12.434377

24 July 2001 Variable length decoder on dynamically reconfigurable cell array processor

Kiyotaka Komoku, Takayuki Morishita, Fumihiro Hatano, Iwao Teramoto

Proceedings Volume 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III; (2001) https://doi.org/10.1117/12.434377
Event: ITCom 2001: International Symposium on the Convergence of IT and Communications, 2001, Denver, CO, United States

Abstract

Three kinds of basic Variable Length Decoder were implemented on Dynamically Reconfigurable Cell Array Processor. Traditional method, Leading zeros method, Generated unique address method were discussed. The number of required resources for each Decoder was described. Especially, in Generated unique address method, the Variable Length Decoder circuit size on Dynamically Reconfigurable Cell Array Processor was quite small.

Citation Download Citation

Kiyotaka Komoku, Takayuki Morishita, Fumihiro Hatano, and Iwao Teramoto "Variable length decoder on dynamically reconfigurable cell array processor", Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); https://doi.org/10.1117/12.434377

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