This paper overviews and implements the transfer-field method applied to the calculation of electronic noise in small semiconductor structures. Two basic schemes are used and developed in detail. The former considers velocity fluctuations and the latter acceleration fluctuations as microcopic noise sources. We show that the latter scheme has several advantages with respect to the former one. Indeed, starting from Markovian noise sources, the latter scheme separates the time and spatial evolution of the local noise sources. In this way, the dual representation of the noise spectral density in terms of impedance and admittance fields is recovered. A remarkable achievement is that from the knowledge of the bulk Langevin sources at a hydrodynamic level it is possible to calculate the noise spectra of non-homogeneous structures even for nanometric devices. The method is validated by comparing the results of the present scheme with those obtained from self-consistent Monte Carlo approaches for different structures of interest.

Characteristic potential method (CPM) for noise calculation has been developed for multi-terminal semiconductor devices under the drift-diffusion scheme. Merit of the CPM is that clear cut definitions of the terminal thermal noise currents and the terminal excess noise currents can be made for unipolar devices and homogeneous resistors. We prove that the terminal thermal noise currents and the terminal excess noise currents are uncorrelated for unipolar devices even when they come from the same local noise sources. We also suggest a way to define thermal noise and excess noise in bipolar devices using the derived formulas from the CPM. As applications of the CPM, we show that the high frequency excess noise observed in homogenous semiconductor resistors is really shot noise whose noise generating mechanism is just the same as that of vacuum diodes. We also show that the dominant high frequency noise in long-channel MOSFETs is thermal noise in the linear region, but the excess noise is getting more significant as the drain bias increases, and is important in the saturation region. The excess noise in the saturation region of the long-channel MOSFETs is shown to be shot noise. Finally, we try to explain the shot noise-like behaviors observed in forward-biased pn junction diodes by the conventional corpuscular theory of shot noise even though the impedance field method confirms that the shot noise behaviors are caused by the local noise sources in the neutral regions, not in the depletion regions.

We discuss the current noise characteristics of nano-scale devices by employing the quantum transport models based upon the nonequilibrium Green's function model (NEGF) and the Monte Carlo (MC) device simulation. In this paper the NEGF is used to study the shot noise suppression caused by the quantum mechanical correlations of electrons in semiconductor nano-scale devices, so that the current noise is discussed at low temperature. On the other hand, the quantum corrected MC model is developed to simulate practical semiconductor devices at normal temperatures, and the current noise spectral density of a nano-scale Si-MOSFET structure is presented.

This paper presents a thorough description of the high-frequency noise characterization and modeling of CMOS transistors for radio frequency (RF) integrated circuit (IC) design. It covers two main topics: high-frequency noise characterization and physics-based noise models. In the first section, two de-embedding procedures are presented for noise and scattering parameter de-embedding to get rid of the parasitic effects from the probe pads and interconnections in the device-under-test (DUT). With the intrinsic noise parameters, two extraction methods to obtain the channel noise, induced gate noise and their correlation in MOSFETs are discussed and experimental results are presented. Based on the noise information obtained in the first section, the second part of the paper presents physics-based noise models for the noise sources of interest in deep submicron MOSFETs. It discusses the model derivation, channel noise enhancement in deep submicron MOSFETs and impact of channel length modulation (CLM) effect. Finally a simple and accurate analytical model for channel noise calculation will be presented.

With the recent advances in CMOS technologies, the MOSFETs offer competitive low noise performance at high frequencies comparable with their bipolar counterparts and become attractive candidates even for challenging high frequency applications with their low cost and high integration level. Therefore, the transistor model accuracy becomes a crucial factor for predicting the RF circuit performance accurately in a broad frequency range. An overview of a high frequency noise modeling approach based on a direct parameter extraction technique is presented in this paper. Moreover, the presented parameter extraction methods are evaluated by means of broadband noise parameter and S-parameter measurements. A temperature noise model predicts all four noise parameters at any frequency and can be used to determine the dominant noise source of the small-signal equivalent circuit. The model can be verified by comparing the measured noise parameters with the simulation results over a broad frequency range. Finally, a practical circuit example of an amplifier using a 0.12 μm CMOS technology at 24 GHz is given.

We study the thermal noise characteristics of the scaled MOSFET devices using the hydrodynamic transport model and the Green's function technique. We compare the result of the hydrodynamic model with that of the drift-diffusion model and study the effect of the nonlocal transport on the drain noise current for the NMOSFET with the L_met (determined by the metallurgical junctions) about 40 nm. It is found that the nonlocal transport effect broadens the effective vector Green's function and increases the responses of the electrostatic potential and the electric field at the entrance of the channel, which can directly influence the drain noise current. We also study the effect of the spatially nonuniform energy relaxation time on the noise characteristics and find that the region with larger energy relaxation time is less sensitive to the velocity fluctuation noise.

This paper revisits the fundamental theory of thermal noise in the MOS transistor. It has been recognized quite early that carrier velocity saturation and eventually also carrier heating degrades the thermal noise performance of short-channel MOS devices. This degradation is evaluated in terms of the delta thermal noise parameter defined initially by van der Ziel as the ratio between the thermal noise conductance at the drain and the channel conductance at V_DS=0. For long-channel devices this factor is equal to 2/3. Today, there is still a controversy about what the value of this factor actually is for short-channel devices. Some authors measured a significant degradation of up to 7, attributing it mainly to carrier heating. Some other measured values that where always smaller than 2 on several devices over several technologies and pretend that there is no need of carrier heating to explain this moderate degradation, assuming that velocity saturation only can explain it. More recently, some other authors attribute this degradation to the effect of channel-length modulation. Based on a truly physical charge-based model, this paper tries to clarify the contribution of these different effects on δ. It also highlights the fact that for circuit designers, the real important parameter is not so much the δ factor but rather the ratio of the thermal noise to the transconductance at the same bias point defined as the γ thermal noise excess factor.

In this work, we have performed an investigation of the consequences of dowscaling the bulk MOSFET beyond the 100 nm range by means of a particle-based Monte Carlo simulator. Taking a 250 nm gate-length ideal structure as the starting point, the constant field scaling rules (also known as “classical” scaling) are considered and the high-frequency dynamic and noise performance of transistors with 130 nm, 90 nm and 60 nm gate-lengths are studied in depth. The analysis of internal quantities such as electric fields, velocity and energy of carriers or conduction band profiles shows the increasing importance of electrostatic two-dimensional effects due to the proximity of source and drain regions even when the most ideal bias conditions are imposed. As a consequence, a loss of the transistor action for the smallest MOSFET and the degradation of the most important high-frequency figures of merit is observed. Whereas the comparative values of intrinsic noise sources (SID, SIG) are improved when reducing the dimensions and the bias voltages, the poor dynamic performance yields an overall worse noise behaviour than expected (especially for Rn and Gass), limiting at the same time the useful bias ranges and conditions for a proper low-noise configuration.

The progress of SiGe strained layer heteroepitaxy on virtual buffer substrates has opened up the opportunities for Si-based n- and p-channel HFETs with excellent RF performance. These devices have been reached outstanding high frequency figures of merit with f_MAX of 188 GHz and 135 GHz, for the n-HFET and the p-HFET, respectively. The Si/SiGe n-HFET exhibits a minimum noise figure NF_min of 0.3 dB with associated gain G_ass of 19 dB at 2.5 GHz, while for the Ge/SiGe p-HFET a NF_min of 0.5 dB with G_ass of 14 dB at 2.5 GHz have been reached. High frequency noise properties were simulated using Pospieszalski's and PRC-Van Der Ziel's noise models. Good agreement is obtained between experimental data and modelling owing to the investigation of the main contributions to n-HFET noise properties. Furthermore, coupled with experimental results at different gate length, hydrodynamic simulations with Silvaco software have been carried out to predict further RF and noise performance improvements when shrinking the gate length down to 70 nm. The low frequency noise of SiGe FETs is reported. All the preliminary result show that the noise level and corner frequency are in the same range as in III-V HEMTs.

This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.

In this paper, the noise properties of transistors on 90 nm silicon on insulator (SOI) and bulk CMOS technologies are investigated. At 20 GHz, the SOI and bulk devices have minimum noise figures of 1 dB and 2.3 dB, respectively, demonstrating the superior performance of the SOI technology. The corresponding maximum available gain is 13 dB and 12 dB, respectively. For the first time, the drain and gate noise coefficients of shortchannel SOI devices are extracted yielding values of 2.15 and 1.7, respectively. Theoretical aspects are discussed to identify the main noise sources and to gain insights for optimizations. Furthermore, examples of analog monolithic integrated circuits fabricated on SOI technology are presented. Measured results are a noise figure of 4 dB for a low noise amplifier (LNA) at 40 GHz, a single side band noise figure of 9 dB for a passive mixer at 40 GHz and a phase noise of -90 dBc at 1 MHz offset for an voltage controlled oscillator (VCO) at 60 GHz. To the knowledge of the authors, these are the best noise performances achieved to date for CMOS based transistors and circuits at millimeter wave frequencies.

A novel graded band gap channel Si-SiGe MOSFET structure has been suggested and its characteristics has been investigated. The investigations indicated that the suggested structure reduces the short-channel effects, increases the cutoff frequency, and hence makes it usage at high frequency and Low noise applications prefeable. To show the superior performance of the suggested structure at GHz frequencies, and as an example, the noise behavior of the structure is thoroughly investigated. First the device noise model parameters are calculated from D.C. and A.C. characteristics. The extracted noise model parameters are then used to determine the minimum noise figure and minimum noise temperature at GHz frequencies. The effects of the different device parameters on the noise performance are determined. Finally, the results are compared with those of conventional MOSFET structure to show the superior performance of graded band gap Si-SiGe MOSFETs at these frequency ranges.

Bias dependent microwave noise characteristics of high-speed 150 GHz SiGe HBTs as well as AlGaAs and InGaP HBTs were measured in the 2-26 GHz frequency range. The characteristics are compared with the compact bipolar transistor models HICUM and VBIC. For noise source analysis and decomposition, a detailed small-signal model with corresponding parameters is employed which is based on a compact model. In particular, the influence of the various noise sources and mechanisms on the minimum noise figure is investigated. As predicted by Van der Ziel, correlation between base and collector current shot noise in SiGe and AIIIBV HBTs is found to reduce NFmin for the frequency range of investigation. AIIIBV HBTs exhibit strong reduction of collector shot noise due to the conduction band peculiarity, what is not the case for SiGe based HBTs.

The influence of base layer structure of InGaAs/InP and GaAsSb/InP double heterojunction bipolar transistors in terms of rf-performance and rf-noise behaviour was investigated in detail. With the use of a combined small-signal and rf-noise model it is possible to localize the noise-phenomena to specific device regions. With this knowledge, the transistor can be optimised in terms of the layer-structure achieve improved rf-performance.

The accuracy of the SPICE and unified compact noise models is assessed in the RF range by comparison with the hydrodynamic device model for a state-of-the-art SiGe HBT with a low base resistance. Despite the low base resistance, as a general result, it turns out that the noise is dominated by the thermal fluctuations of the holes within the base and the exact determination of the base noise resistance is a prerequisite for accurate compact noise modeling. It is shown that the base noise resistance equals the base resistance and can be evaluated with standard parameter extraction schemes. Based on an accurate base resistance the SPICE model yields good results as long as the frequency is considerably below the peak cutoff frequency. The unified model, on the other hand, is found to yield good results even at frequencies comparable to the peak cutoff frequency. But this is achieved at the expense of an additional parameter which is difficult to determine without physics-based numerical noise simulation. Moreover, it is shown that the drift-diffusion model should not be used to assess the accuracy of compact noise models, because it yields erroneous noise results for state-of-the-art SiGe HBTs.

This paper describes the design of noise-critical circuits for radio-frequency and high-speed digital applications in a SiGe:C BiCMOS technology. Starting with a figure of merit for the high-frequency noise behavior of bipolar transistors, challenges in the transistor design are formulated. It is shown that the addition of carbon to the base of a SiGe-HBT results in an excellent high-frequency noise behavior of the transistors. A first design of a differential three-stage low-noise amplifier for 60 GHz applications is presented having a gain of 18 dB at 50 GHz. Furthermore, a 60 GHz voltage-controlled oscillator is presented with a phase noise of -90 dBc/Hz at 1 MHz offset from the oscillation frequency. Using a first-order PLL model, we predict an rms jitter contribution to a 5 MHz-bandwidth PLL as low as 0.4 percent of the oscillation period. Possible applications include wireless and wired broadband communication as well as automotive radar.

As further enhanced functionalities of mobile equipment are predicted, the development of a CMOS technology that provides low-power, high-speed, and low-noise performance has become an urgent and hot issue. For these application driven technologies the complexity must be tackled at different levels to insure the optimisation of the area, the power consumption, the speed and the reliability. Therefore this paper present a review of the solutions implemented at different levels from system down to technology in order to reduce the contribution of the low frequency noise. These achievements are illustrated by experimental results from literature and are inserted in the general context of system design strategies for reducing the 1/f noise contribution. In a first part dedicated to high-level system and circuit design, we introduce the noise reduction by switching techniques and the methodology for including the noise dispersion in scaled devices for the early design of analogue/RF circuits. In the second part, the 1/f noise is tackled at its origins i.e. the choice of the gate oxide and other critical process steps.

In this paper, some new front-back coupling noise effects are described. They have been revealed in partially-depleted SOI MOSFETs under conditions where an accumulating voltage is applied to the back gate. The first effect consists in the appearance of a Lorentzian component in the noise spectra of the front channel current. The time constant for such Lorentzians which are observed in weak and strong inversion decreases with increasing amplitude of the back-gate voltage and is independent of the front-gate voltage. The second effect is the decrease of the amplitude and the turn-over frequency of the LKE noise Lorentzians that are present in the noise spectra due to the EVB tunneling currents. It is shown that the Lorentzians generated under conditions of an accumulating back-gate voltage and the LKE Lorentzians are analogous by their nature. A model is considered whereby the source of the Lorentzians entering the noise spectra in the presence of an accumulating back-gate voltage is the Nyquist noise voltage generated across the p⁺-n⁺ junction induced by the back-gate voltage at the source/back gate. The capacitive character of the source-body impedance is the reason for the Lorentzian shape of the noise component generated by those Nyquist fluctuations

The SiGeC ternary alloy seems to be an attractive material system for Si-based device applications, because the incorporation of a small amount of C in the high-mobility SiGe layer offers an additional degree of freedom for tuning the bandgap, band offsets and the lattice strain in group IV heterostructures. In this work, detailed low-frequency noise (LFN) results in SiGeC pMOSFETs are presented. Our experimental results in saturation regime of the SiGe MOSFET show that the noise in SiGeC MOSFETs at gate bias |V_GS-V_T|<0.4V can be referred to the gate terminal as a noise voltage S_VG=V_G², which implies (ΔN) fluctuation with correlated noise in the cap and SiGeC channel currents. Overall, the trend shows that the gate referred noise voltage scales inversely with the gate area, and that the variation of the noise level has log-normal distribution. Therefore, the noise in SiGeC MOSFETs can be expressed as S=S_avg*exp(t*σ_Np), where t=±1,...,±3 is a coefficient selected for desired confidence probability of 0.6,...,0.99 respectively, and σ is the standard deviation of the log-normal distribution of the noise level around its average S_avg, later given by (ΔN-Δμ) fluctuation in the cap layer and SiGeC channel of pMOSFET.

Realization of the full potentials of heterostructure bipolar devices with high gain and low noise performance requires qualitatively reliable and quantitatively precise predictive process and performance simulation models. In this review article, the details of the recently proposed extended drift-diffusion model is presented for determining the effect of band offsets on the static current and 1/f noise properties of heterojunction bipolar transistors (HBTs). The model satisfies boundary conditions that govern the carrier transport across the heterointerface and satisfy the current continuity by coupling the electron-hole recombination current across the space charge region to the minority diffusion current in the bulk regions. It is shown that the intrinsic junction resistance to the diffusing minority electrons across the heteroemitter depletion region is stronger (weaker) at small (high) forward biases as compared with that to the recombined electrons and holes. Increasing bias causes a change of nature of 1/f noise from recombination to diffusion type in HBTs. The model should be useful in understanding the effects of interface properties on current transport and 1/f noise performance of HBTs.

This work presents low frequency noise results in high-speed Si/SiGeC heterojunction bipolar transistors (HBTs). In this new generation of HBTs carbon doping is processed during of the deposit of the epitaxial SiGe base layer in order to suppress boron out-diffusion. Low frequency noise study is performed on three type of transistors that differ by the thickness of the Si cap layer. The Si Cap layer is a non intentional doped Si layer deposit after the SiGeC base layer and prior the contact emitter structure. Thus, the results on the three different Si Cap HBTs allow us to study the influence of the Emitter-Base junction depth on the low frequency noise of these HBTs. Measurements of the equivalent input noise spectral density (Si_B) showed that spectra are composed of a 1/f component and the white noise is always reached at low bias. For the smallest transistors we observed the presence of Lorentzian(s) component(s). The excess noise sources are mainly located at the intrinsic emitter-base junction. Concerning the 1/f noise level, a quadratic dependence on base current bias and an inverse dependence on the emitter area are found. The normalized figure of merit, K_b = K_fxA_E, is ranging between 1.7 and 2.1 10^-9 μm² and is among the best results published concerning SiGe HBTs, this shows that the incorporation of carbon do not have any consequence for the 1/f noise level and more generally for the LF noise characteristics. In the Si Cap thickness range used in this work, no noise degradation is observed when the electrical emitter-base junction is getting closer to the poly/mono emitter interface. Hence DC and AC characteristics could be optimized without changing the LF noise performances. Finally, from measurements at the input and at the output, the emitter series resistance is extracted and is found to be proportional to the Si Cap thickness.

Low frequency noise in 4H-SiC BJTs with the current gain β ≈ 10^-15 and unity current gain frequency f_T of about 1.5 GHz has been investigated. The corner frequency f_c was found to be f_c = 2×10⁴ Hz. The value of the coefficient K_B, which is the figure of merit for the low frequency noise in the region of noise proportional to squared current, was found to be 6×10^-7 μm². This value is only an order of magnitude higher than the typical values for high-frequency Si-BJTs.

This paper presents results of ageing tests performed on InP/InGaAs DHBT on InP substrate. An extrinsic current path between measurement pads is shown to be responsible for leakage current evolution. The analysis of low frequency base current noise is used to identify pre-eminent noise sources and evaluate the stability of intrinsic HBT.

In this paper, we present some results on low frequency noise of GaN HEMTs grown either on sapphire, SiC or Si. The evolution of LF drain and gate current noise is analysed in ohmic and saturation regime. Devices on sapphire grown either by MOCVD or by MBE present α_H value in ohmic regime as low as 10^-4, whereas for devices grown by MOCVD on SiC, α_H extends from 5x10^-4 to 10^-2. Low frequency gate current noise and coherence function have been measured to discuss possible correlation between drain and gate current noise. Devices with high reverse gate current exhibit high gate current noise. The coherence function increases when the I_g/I_d ratio becomes higher than 10^-5 which results in increase of the drain current noise due to contribution of gate current fluctuations.

The I-V characteristics of GaN/AlGaN HFET and 1/f noise at 4K have been measured in strong magnetic fields, where the electron mobility is affected by geometric magnetoresistance. The magnetic field dependence of the 1/f noise shows that the number of electrons fluctuations is the dominant mechanism of the 1/f noise and precludes the mobility fluctuations mechanism. The channel mobility extracted from the magnetoresistance data first increases with gate bias reaching the maximum value of ~(0.9-1.0) m²/Vs at the 2D electron concentration of 5x10¹² cm^-2. This maximum value is close to the estimated ballistic mobility limit of 1.2 m²/Vs determined by the electron transit time with the Fermi velocity.

In this paper, we report low frequency noise (LFN) data obtained on passivated AlGaN/GaN HEMT’s grown by MBE on a silicon substrate. In order to localize the LFN sources, we have measured all the extrinsic gate and drain current noise generators and their coherence versus bias in the linear regime. We have found that the gate noise sources result from leakage phenomena at gate-source and gate-drain regions. Drain noise sources are mostly located in the active channel below the gate and they feature an equivalent Hooge coefficient of about 10^-3. Secondly, in order to build a LFN model that fits the requirements of a CAD simulator, we have measured the LFN sources for numerous bias points in the saturation region and therefore we have studied the bias dependence of the different noise sources under normal operating conditions. Results show that the gate terminal noise current impacts heavily the overall LFN of the transistor contrary to others III-V HEMTs, and that specific bias conditions are needed in order to reduce the LFN.

The paper reviews the physics-based approach to the frequency conversion and noise analysis of semiconductor devices operating in forced large-signal (quasi) periodic regime. Noise analysis under large-signal operation is presented as a direct extension of the classical physics-based noise simulation technique where the modulated microscopic noise sources are propagated to the external device terminals through Green's functions. A complete discussion of a simple yet significant case study is presented with reference to a junction diode, which allows for an analytical cyclostationary noise model. To complete the paper, we include an analysis of the validity of two widely exploited approximated system-oriented cyclostationary noise modelling approaches, based on the modulation of small-signal stationary noise spectra.

We report Monte Carlo particle (MCP) simulations of the current response and noise spectrum in heavily doped nanometric GaAs Schottky-barrier diodes (SBDs) operating under static, cyclostationary and resonant-circuit conditions in the forward bias region. Main attention is paid to the SBDs application in the THz frequency region. General features of the regular response and noise as well as their modifications under various operation modes are obtained from MCP simulations and analyzed in the framework of a simple analytical model based on the static I-V and C-V relations obtained from simulations.

The basic features of the recently proposed Charge-Controlled Non-linear Noise (CCNN) model for the prediction of low-to-high-frequency noise up-conversion in electron devices under large-signal RF operation are synthetically presented. It is shown that the different noise generation phenomena within the device can be described by four equivalent noise sources, which are connected at the ports of a “noiseless” device model and are non-linearly controlled by the time-varying instantaneous values of the intrinsic device voltages. For the empirical identification of the voltage-controlled equivalent noise sources, different possible characterization procedures, based not only on conventional low-frequency noise data, but also on different types of noise measurements carried out under large-signal RF operating conditions are discussed. As an example of application, the measurement-based identification of the CCNN model for a GaInP heterojunction bipolar microwave transistor is presented. Preliminary validation results show that the proposed model can describe with adequate accuracy not only the low-frequency noise of the HBT, but also its phase-noise performance in a prototype VCO implemented by using the same monolithic GaAs technology.

A complete analysis of the low-frequency (LF-) noise is performed on resistive FET mixers, where LF-noise is created due to the self-mixing process of the local oscillator. First, a new scaleable noise model for field-effect transistors in ohmic channel bias regime (U_ds ≈ 0V) has been developed, which uses fluctuating resistances, instead of noise voltage or noise current sources. Measurements on a hybrid, single-ended mixer prove a good accuracy of the proposed model and reveal a method to distinguish between the different noise sources. Almost complete cancellation of the low frequency noise can be achieved by proper operation.

Oscillators are key components of many kinds of systems, particularly electronic and opto-electronic systems. Undesired perturbations, i.e. noise, in practical systems adversely affect the spectral and timing properties of the signals generated by oscillators resulting in phase noise and timing jitter, which are key performance limiting factors, being major contributors to bit-error-rate (BER) of RF and possibly optical communication systems, and creating synchronization problems in clocked and sampled-data electronic systems. In this paper, we review our work on the theory and numerical methods for nonlinear perturbation and noise analysis of oscillators described by a system of differential-algebraic equations (DAEs) with white and colored noise sources. The bulk of the work reviewed in this paper first appeared in [1], then in [2] and [3]. Prior to the work mentioned above, we developed a theory and numerical methods for nonlinear perturbation and noise analysis of oscillators described by a system of ordinary differential equations (ODEs) with white noise sources only [4, 5]. In this paper, we also discuss some open problems and issues in the modeling and analysis of phase noise both in free running oscillators and in phase/injection-locked ones.

Designing oscillator circuits at RF and microwaves requires specific knowledge in extremely varied fields of electronics. The following items will be the core of the presentation: - The physical processes leading to low-frequency noise in semi-conductor devices and the nonlinear behavior of the noise sources in large signal operating conditions will be detailed - Transistor modeling: A special emphasis will be put on the low-frequency noise modeling associated to the nonlinear transistor models. - Simulations tools: In order to simulate accurately the phase noise in free-running nonlinear oscillator circuits, the frequency domain approach based on the conversion matrices formalism which is related to the harmonic balance formalism will be detailed. - Design rules for low phase noise operation Theoretical conditions to be fulfilled by the circuit will be detailed on the basis of the Leeson analysis revisited. The need of new characterizations and extraction methods of noise sources in actual transistors, for a better prediction of noise performances of nonlinear circuits will be recalled.

Phase noise of microwave free running sources has always been an important problem in various applications. This noise generates an increased bit error rate in a telecommunication link and degrades the sensitivity of a radar (particularly in the case of Doppler or FM-CW radar). Reducing this noise contribution is a difficult challenge for microwave engineers and circuit designers. The main contributor to this noise is well known to be the microwave transistor and finally an improvement of the oscillator phase noise will result from an optimization of the transistor phase noise. The 10 kHz to 1 MHz offset frequency range is the most important frequency range for many microwave oscillators applications. An improvement of the transistor (or oscillator) phase noise in this frequency range cannot be obtained without a good knowledge of the noise mechanisms involved in the device. In this frequency range, two different mechanisms may be at the origin of the phase noise. The first one involves the conversion to high frequencies of the transistor baseband noise (or 1/f noise) through the devices nonlinearities. The second one is due to the direct superposition of the transistor high frequency noise. This noise is simply added to the carrier, and this contribution may be described using the amplifier noise figure. In this paper, the evidence of the transistor high-frequency noise contribution in residual phase noise data is demonstrated. This behavior is observed in several bipolar devices in which the low-frequency noise contribution has been carefully minimized using an optimized bias network. Then, the phase noise behavior is correlated to nonlinear noise figure measurements. This study has been carried on numerous different microwave transistors, including FET and bipolar devices. An increase of the noise figure with the microwave signal level has been observed in each case.

Applications like radio astronomy and space communications require ultimate sensitivity and make use of very particular receivers with state-of-the-art devices. Usually the receivers are cooled at cryogenic temperatures to reduce the noise even further. Noise temperatures of only a few times the quantum limit can be obtained in these conditions. During the past decade, Indium Phosphide HEMTs have demonstrated the best noise performance at cryogenic temperatures in the microwave frequency range of all active semiconductor devices, together with extremely low power consumption. For certain applications noise is not the only factor affecting the sensitivity. For example, gain fluctuations may play a dominant role in wide band radiometers. Unfortunately some of the factors that have contributed to improve the noise temperature have degraded the gain fluctuations. The operation at cryogenic temperatures also increases the fluctuations. This paper describes the experimental results obtained at the Centro Astronomico de Yebes (CAY) in the development of wide band cryogenic amplifiers. Special attention is paid to the influence of the bias point in noise and gain fluctuations. InP HEMTs from different foundries were tested. The amplifiers developed will be used in the Herschel ESA mission radiometers and the Atacama Large Millimeter Array (ALMA) receivers.

The main objectives of this work concerns the on-wafer high frequency noise measurements of low noise transistors (GaAs and InP HEMTs) at cryogenic temperature. We propose a new approach to de-embed the measured noise figure or noise power by taking into account the temperature distribution of the whole bench. For measurements at 77K, the gradient of temperature between the DUT and the receiver or the noise source is greater than 200K and the temperature distribution along the probes and cables is non uniform. This temperature distribution has to be accurately known to de-embed the measured noise figure and especially for low noise device like lattice-matched or metamorphic HEMTs. The temperature distribution along the probes and cables is obtained using a 3-D thermal modeling (ANSYS) and has been checked through thermal sensors measurements. The inputs of the thermal simulations are the material composition and associated thermal properties of the probes, connectors and cables. This temperature distribution associated to a RLCG transmission line are afterwards implemented in CAD tool (ADS). In order to check the validity of such model, we have measured the noise power of a 50 Ω resistance for different temperatures (77 K to 295 K). At 77 K, after a de-embedding procedure using the distributed temperature model, we obtain an equivalent noise temperature of the resistance of 77 K ± 10 K. This de-embedding method will be applied to extract the noise parameters of cooled down HEMTs.

An on-wafer noise parameter measurement method has been developed on a 2.8-18 GHz frequency band. The test bench mainly consists of a probe station, a vector network analyzer and a noise figure meter (NFM). Five noise power measurements and a time- and frequency-domain analysis are used to extract the bench and the device under test (DUT) characterisitics. The method is fitting for any DUT with no assumption on its characteristics and without an impedance-tuner. The aim of this study is to extend the method to a wider frequency band. The main problem is due to the change in the frequency band of the NFM and consists in the incompatibility of the use of direct and inverse Fourier transforms with discontinued characteristics. Discontinuities might provide parasitic additionnal terms, which could invalidate the method. Only a finer analysis of the method can conclude to its accuracy, depending on the kind of discontinuities. In the 0.1-18 GHz frequency band, only our receiver characterics present discontinuities at 1.6 GHz and 2.4 GHz. The problem is easily summarized to the discontinuities of the intercorrelation power sources terms. A deepen study concludes on the effects of these discontinuities and allows an increase of the frequency band. Experimental results on an active two-port are given.

A method for a reliable characterization of the small-signal equivalent circuit and the noise model of Heterojunction Bipolar Transistors (HBTs) is presented. It allows the device equivalent circuit elements (in T-topology) and its noise parameters (NPs) to be extracted simultaneously, using only the measurements of its S-parameters and its noise figure (measured for a well-matched impedance). The procedure is based on a simultaneous estimation of the device S-parameters and noise figure, by fitting to the corresponding measurements. The NPs estimated from the device model are compared to the NPs estimated from the measured noise figure, providing an additional term in the error function to be minimized that guarantees physical results. Thus, the error function is composed by three terms: the root-sum of squares (RSS) of the differences between measured and estimated S-parameters, noise figure and NPs, respectively. Experimental verification of the extraction of the equivalent circuit elements and NPs of an HBT, up to 8 GHz, are presented, and the NPs are compared to those measured with an independent (tuner-based) method.

LNA's (Low Noise Amplifier) are widely used in wireless portable personal communication systems; the LNA noise directly affects the overall system performances. Here it is shown how the Noise Figure of a RF (Radio Frequency) Receiver can be reduced while satisfying the common constraints of impedance matching at the input, low power consumption and good linearity. The proposed Noise Figure reduction technique is based on the cold resistance approach and negative or positive feedback; a single BJT LNA, derived from the common base configuration, is considered. The Noise Figure reduction is obtained over a wide frequency band of operation, and is thus suitable for Multistandard applications. Different LNA feedback topologies are compared. It is shown that a Noise Figure lower than the limit of the common base configuration can be achieved, along with a current consuption of a few mA, over a wide frequency band of operation. Noise Figure calculations and circuit simulation results are presented and compared.

In this work we present a method to characterize broadband noise circuit-models of on-wafer microwave noise sources. The models are used to estimate the device noise temperature, and therefore to characterize its Excess Noise Ratio (ENR). Two types of devices are considered: a cold-FET (V_ds=0V) with the gate reverse-biased, and an unmatched avalanche noise diode. As a first step, a noise analysis is performed from noisy networks theory to derive an expression for the device output noise-current spectral density as a function of the intrinsic noise sources. Then, using the device measured reflection coefficient (or S-parameters in the case of a cold-FET) and measured noise temperatures, a regression technique is applied for the best frequency-fit between the measured and estimated 'multiplier' factor M (for which a smooth frequency dependence is assumed) associated to the intrinsic noise sources, thus reducing the measurement uncertainty. The resulting estimation of the device ENR features a sensible reduction in the measured 'ripple', without loss of the inherent 'slow' frequency variations due to variations of the device output impedance. As an application, the characterized devices are used as on-wafer noise sources to fully calibrate noise measurement systems.

In this paper we propose a model of noisy oscillator to describe the effects of white noise sources on amplitude and phase noise spectrum that can be applied to linear and non-linear structures. This work proposes an extension of previous works to take into account deeper considerations about Analytical Signal and Averaging methodologies to extract a new model for oscillator dynamics. The Noisy Oscillator model has shown an excellent agreement to literature works, and results obtained with the proposed model have been compared to simulations performed with SpectreRF in Cadence 4.4.3 on a LC oscillator, in order to provide model validation.

An indirect approach for estimating the long term stability of DC electrical sources from low frequency noise measurements is presented and discussed. In particular, it is demonstrated that once the unity frequency magnitude and the frequency exponent of the flicker noise component are determined, an overestimate of the variance of repeated measurements of the source output (averaged over a time interval τ) taken ΔT seconds apart can be readily obtained. The proposed approach is validated with reference to actual experimental data.

A generalization of the Nyquist formula for an oscillating electrical circuit with slowly varying parameters is given. Using the momentum method and the time multiscale technique, it is shown that not only the dissipation parameter (resistance), but also the time derivatives of the dispersive parameters (inductance and capacity) determine the spectral properties of the noise in the LC -circuit. This additional contribution is characterized by a new non-local dispersive term which is not related to Joule dissipation and which results from an additional phase shift between the force and the response of the system. The influence of the dispersion contributions on the quality factor of the system is discussed.

We have designed and built a very simple and efficient instrument that allows performing very accurate noise measurements of transistors at any biasing conditions, from room temperature down to cryogenic temperatures. This way a study has been possible of the noise behavior of Silicon JFETs for both the low frequency and the high frequency white noise. We explored a wide range of biasing conditions, starting from a power dissipation of only 2 μW up to 1 μW. Concerning white noise, evidence was found for the hot electron effect: it was negligible at small power dissipation and evident at large power. An experimental study was made of the low frequency noise. Its interpretation was developed based on the Generation Recombination theory. Many JFET samples were investigated, made with different technologies and having different gate area.

Drain current-gate voltage I_d(V_g) characteristics and power spectral density of drain current fluctuations were obtained on SiGe channel pMOSFETs and on their Si homologues, for drain current intensities varied from deep subthreshold to strong inversion regions. Devices with 2.2nm thick SiO₂ gates and channel lengths 50nmd(V_g) characteristics, served for calculating the power spectral density versus drain current functions. The latter required adjusting the interface trap density and a parameter α_c, accounting for the effect of the interface charge fluctuations on the hole mobility fluctuations, significant at high levels of trap filling i.e. high drain current. We found that the power spectral density in the SiGe devices was up to 10 times lower than in the Si controls at sufficiently high drain currents. The simulation, accounting for the data, required a significant lowering of α_c for the SiGe channel. That implies that the low frequency noise reduction in SiGe MOSFETs results from a weaker interaction of the SiGe holes with the interface charges. The sub-0.1μm channel devices show a similar noise lowering, in spite of the significant hole mobility degradation.

This contribution is aimed at describing the available techniques for simulating trap-assisted generation recombination noise in electron devices. We consider physics-based models, where carrier transport equations are complemented by a set of rate equations, one for each trap energy level included in the model, expressing charge conservation. To the aim of noise analysis, such rate equations include stochastic Langevin sources representing level occupancy fluctuations, whose statistical properties are known from basic physical analysis. A generalization of the standard Green's function technique to the physics-based noise analysis can be then exploited to propagate the internal fluctuations to the device terminals, in order to evaluate the correlation matrix of the external noise generators. With reference to a simple device, a superposition of noninteracting trap levels with a proper distribution of timeconstants is shown to yield a 1/f spectrum on a prescribed frequency range. In large-signal operation the fundamental white noise fluctuations are amplitude modulated by the periodic device working point and converted into cyclostationary fluctuations. The cyclostationary internal noise is then propagated to the device terminals by means of proper Green's functions that also involve noise frequency conversion. The same device discussed in small-signal operation is simulated in cyclostationary conditions, therefore demonstrating the upconversion of 1/f noise from baseband to the steady-state harmonics.

We present in this paper a set of coherent tools for noise characterization and physics-based analysis of noise in semiconductor devices. This noise toolbox relies on a low frequency noise measurement setup with special high current capabilities thanks to an accurate and original calibration. It relies also on a simulation tool based on the drift diffusion equations and the linear perturbation theory, associated with the Green's function technique. This physics-based noise simulator has been implemented successfully in the Scilab environment and is specifically dedicated to HBTs. Some results are given and compared to those existing in the literature.

Double Gate Metal-Oxide-Semiconductor Field-Effect-Transistors (DG MOSFETs) are one of the most promising candidates for future CMOS applications in order to comply with the ITRS requirements. Vertical quantum confinement plays a very important role in these devices when the active layer is below 10 nm, and it can modify significantly the performance of the transistors due to the reduction in the inversion layer population and the modification of transport conditions inside the active zone. Starting from an analysis of the results obtained within a semi-classical framework, we present the discussion of the dynamic and noise results when the effective potential approach is considered for the description of quantum effects in a particle-based Monte Carlo simulator. The main static and dynamic figures of merit are investigated, together with the intrinsic noise sources, thus allowing to provide a full comprehension of the inner physics of the devices and elucidating the consequences of quantum mechanical space-quantization effects (like charge repulsion from the gate-oxide boundaries). Results show that neglecting quantum phenomena leads to an important overestimation of gate capacitance and device transconductance and an underestimation of induced gate noise at RF and microwave frequency ranges.

The trace of the gate noise voltage was successfully caught by the measurements of the correlation between the noise outputs of a pair of JFETs connected to a common gate resistor. It is shown for 2SK150 (n-channel junction FET) that the gate noise voltage is 1/f-type and its level is -142dbV²/Hz at 1Hz, and that the correlation coefficient between the gate noise voltage and the gate noise current is -1.

Noise performance of a commercial MOSFET was evaluated for the amplifier application in LF-band. The level of 1/f noise referred to the gate was about -126 dbV/Hz at 1 Hz and was proportional to f^-0.9. At 100 kHz noise was white and was equivalent to the thermal noise from 1 kΩ and 100 kΩ at the drain current of 100 μA and 1 μA, respectively. 2SK1771 is acceptable as the amplifying device connected to a tuning circuit whose resonant impedance is more than the values stated above.

A study of low frequency noise is made in Solid Phase Crystallised (SPC) polysilicon Thin Film Transistors (TFTs) issued from low temperature process (≤600° C). The study is performed in both below and above threshold regions. At first, a static electrical caracterisation of the transistors is carried out. Analysis of the low frequency noise in the TFTs shows that it can be related both to the Meyer-Neldel MN effect, and to the flatband voltage fluctuations due to the trapping/detrapping processes of carriers at the S_iO₂/Poly-S_i interface. Furthermore, a new method of the channel carrier number calculation is proposed. Then, the apparent noise parameter α_app, based on the Hooge formula, is deduced. At low gate voltages α_app increases and reaches a maximum value close to the threshold voltage. This α_app singular behavior is then discussed.

Electrical low frequency excess noise or 1/f noise measurements provide strong means to diagnose the quality and reliability of the devices in semiconductor devices. However the exact nature of the noise sources are not clearly understood yet. In this report, existing models for low frequency excess electrical noise in poly-Si thin-film transistors is scrutinized and a new model is proposed, in particular, for large grain poly-crystalline thin-film transistors. Major noise sources are supposed to be located in the grain boundary region and the grain boundary is modeled as two independent Schottky diode connected face-to-face. As the gate bias increases the grain boundary barrier height decreases and the conduction and therefore the noise generation in the grain bulk region becomes important. Therefore, at low gate bias, grain boundary plays important role in conduction and noise generation, and at high bias, the number fluctuation involving the oxide traps leading to flat band fluctuation (unified model for crystalline-Si MOSFET's) will dominate the noise generation. We calculated the critical gate bias (or barrier height) that severs these two different noise generation regimes. Recently reported experimental results are explained with this model.

Low frequency noise, LFN, was studied in three sets of n-MOSFETs, with silicon nano-crystals, Si-nc's, imbedded in the gate oxide, in planar layers placed at distances t_nc=1.2, 1.5, and 2nm from the Si/SiO₂ interface. The power spectral density of the drain current, I_d, fluctuations, S_Id(f), was measured on the devices with the Si-nc's and without (reference samples). S_Id(f) measured on devices without Si-nc, was of 1/f type. The spectra in the devices with the Si-nc's, were accounted for by a superposition of a 1/f noise and a packet of Lorenzian lines, peaking at some mean frequency, f_nc, found to depend exponentially on t_nc. Such a dependence implied that the charge capture and release on the Si-nc's is governed by a direct tunnelling, with a characteristic tunnelling length, λ. From the data obtained on devices with three different positions of the Si-nc layers we could extract the value of λ, found to be equal to about 0.1nm, with a slight dependence on the applied gate voltage. The same constant is also involved in the 1/f component of LFN which is interpreted in terms of a carrier number fluctuation (McWhorter) model, where surface potential fluctuations result from the charge capture/release on traps distributed in the gate oxide. Finally, the frequency dependence of S_Id on t_nc is explained using the standard model of carrier number fluctuations, generated by trapping/release on oxide interface traps and Si-nc's.

AlGaN/GaN HEMTs are promising devices not only for high frequency power amplification but also for non-linear applications such as VCO. Therefore an assessment of their low frequency noise (LFN) is needed since it can be up-converted around the RF carrier. We have therefore compared different devices either made on sapphire or silicon in order to know which ones feature the lowest LFN. This study involves static and low frequency noise measurements (two different LFN set-up will be used and compared). GaN HEMT devices featuring several gate dimensions have been measured for different biasing conditions both in ohmic and saturation regime. We have compared sapphire based devices with silicon based ones with respect to their LFN levels. In a second part of this work, we report on some reliability results of HEMT on sapphire substrates: identification of defects has been achieved with the help of static measurements, and we make use of low frequency noise as well as physical simulation in order to understand the operating mode of the device. For the first time, we correlate the γ of the 1/f^γ LFN spectrum with transport mechanisms of the carriers: we found that γ strongly depends on the carriers conduction path. This hypothesis has been checked for HEMT on silicon substrate.

The three systems for low frequency noise measurements of an optoelectronic coupled device (an infrared emitting diode and a phototransistor) were described. In the system I a low frequency noise of an infrared diode was measured, in the system II a low frequency noise of a phototransistor was measured, in the system III a low frequency noise of an optoelectronic coupled device was measured. The investigations were carried out for optoelectronic coupled devices of CNY type. The results of noise measurements in three systems are compared and a main source of noise in optoelectronic coupled devices was evaluated.

We present a simulation study of the thermal noise locally generated in the n-channel of strained-Si MOSFETs and compared the obtained results with those of a state-of-the-art 100 μm gate length bulk MOSFET. Local physical magnitudes governing the noise have been obtained using a commercial 2D device simulator that implements the impedance field method to calculate the overall noise behaviour at the terminals. We focus in the analysis of the ability of the devices to operate in the micro-power regime. The design of the s-Si MOSFET is non-optimal and low-doping regions were introduced between the gate and both the source and drain contacts to accommodate for the current shortcomings in the SiGe FET technology. AC results show excellent performance of s-Si MOSFET as compared to the bulk MOSFET. On the contrary, the noise performance of the bulk MOSFET is better than the one of s-Si MOSFETs. This is attributed to the poor design of the lateral structure of the s-Si MOSFET. A re-design of the structure, particularly, a reduction of the source and drain resistances, should allow for a significant reduction of the NF in these transistors.

We apply the technique of the calculus of stochastic differential equations to the problem of noise in an electronic circuit with positive feedback. We argue that this is a very natural approach to the more general problem of noise in electronic circuits of all types. We apply the standard small-signal analysis to the circuit, incorporating the standard high-frequency small-signal model for the field effect transistor. This allows us to derive a state-variable model for the system, which is essentially a coupled system of Ordinary Differential Equations. If we then incorporate a standard noise model for the field effect transistor, we obtain a coupled system of Stochastic Differential Equations, or SDEs. We apply the stochastic differential calculus of Ito to this problem and compare the results with simulations. We examine the dependence of phase-noise on the system parameters. We also simulate the case where the oscillations become large and use this to investigate the limits of the small-signal approximation.