Functional requirements for modern narrow-band and wide-band wireless and lightwave communication systems place stringent demands on speed and noise behavior of circuits and devices used to design them. MOS technology in the nanometer regime continues to be the low-cost high-performance workhorse driving innovations for these applications. In this paper, we trace the developments in the modeling of noise in MOS transistors as the device channel lengths shrink by a factor or a thousand from tens of micrometers to tens of nanometers. The impact of scaling on classical noise mechanisms is explained. Also, generation of new noise sources as a result of scaling are also described. This leads to a better physical understanding of the noise behavior of these devices. Methods of eliminating some of these noise sources by suitable choice of materials and modifications in device structure are explained. Application of this understanding to the practical design and layout of low-noise high-performance circuits is illustrated. As a result, the noise performance of MOS devices has improved by almost an order of magnitude making them an ideal choice for low-noise communication electronics design. Research continues as the channel lengths shrink further.

With the inherent advantages in SOI CMOS technology, minimizing DC and switching floating body effects have enabled high speed digital processors with more than a 25% improvement over bulk silicon CMOS design. Currently, there is a need for a more comprehensive understanding of AC characteristics on SOI CMOS technology for mixed-mode baseband and RF (radio frequency) applications. The objective of this paper is to present a study of unique AC floating body effects and the resultant low-frequency noise overshoot phenomenon in SOI CMOS technology. Further study of their impact on the RF arena will also be discussed.

In order to replace the conventional Si_O2 in MOSFETs and minimize gate tunneling currents, high permittivity dielectric materials have been proposed as alternatives. These materials have successfully resolved the gate leakage problem with thicker oxide dielectric. However, other issues such as lower effective mobility and increased low frequency noise due to higher oxide trap density, limit its further development. Among these candidates, HfSiON offers many advantages compared to other high-k devices such as suppression of Boron penetration, remaining amorphous during high temperature annealing, and offering better thermal stability and interface quality. In addition, the extracted oxide trap density from measured 1/f noise shows lower values compared to other high-k MOSFETs. This paper presents low frequency noise characteristics of MOSFETs with HfSiON and SiON gate dielectrics of varying gate length dimensions and effective oxide thickness. The measured noise spectra as well as DC parameters will be compared between HfSiON and SiON MOSFETs. The noise parameters are extracted from the measured noise data using the interface-generated, correlated number and mobility fluctuation model.

A characterization of low frequency noise in submicron N-MOSFETs is presented. For large devices, it is found that 1/f noise results from carrier number fluctuations. The slow oxide interface trap density deduced from noise data is found around 10¹⁶ eV^-1 cm^-3 in agreement with state-of-the-art gate oxides. Submicron devices present R.T.S noise and exhibit three independent active traps in saturation range, from weak to strong inversion. All of these traps have been found as acceptor type centers. Their activity ranges, their maximum of activities and their positions in the oxide from the Si-SiO₂ interface have been obtained by the study of emission and capture times against gate voltage. It is shown existing overlap in trap activities for particular gate bias ranges. This overlap is confirmed by the observation of multi level R.T.S in time and frequency domains. For each trap, the number of R.T.S events is explained using the trap occupation probability. Finally, the global R.T.S behavior of devices, including the whole trap activities from weak to strong inversion, could be described using the simple R.T.S model classically used for a single oxide trap. This global study shows a simple method to determine R.T.S impact, and describes perfectly multi-trap activity.

The effects of hot carrier stress on CMOS voltage-controlled oscillators (VCO) are investigated. A model of the threshold voltage degradation in MOSFETs due to hot carrier stress has been used to model jitter and phase noise in voltage-controlled oscillators. The relation between the stress time which induces the hot carrier effects and the degradation of the VCO performance is presented. The VCO performance degradation takes into consideration decrease in operation frequency, increase in jitter and phase noise and decrease in tuning range. The experimental circuits have been designed in 0.5 μm n-well CMOS technology for operation at 3 V. It is shown that when the MOSFET threshold voltage, increases from 0.4 V to 0.9 V due to the hot carrier effect, for the single-ended ring oscillator, the oscillation frequency changes from 538 MHz to 360 MHz, and the phase noise changes from -104 dBc to -105 dBc at 1 MHz frequency offset with a power dissipation of 0.37 mW. For the current-starved VCO, the tuning range changes from 72 MHz - 287 MHz to 65.4 MHz - 201 MHz, and the phase noise changes from -109 dBc to -107 dBc at 1 MHz offset from the center frequency, 200 MHz; for the double-ended differential VCO, the tuning range changes from 32 MHz - 983 MHz to 26 MHz - 698 MHz, and phase noise changes from -86 dBc to -87 dBc at 1 MHz offset from the center frequency, 700 MHz.

We have studied the 1/f noise and the radiation response of transistors with silicon-on-insulator (SOI) buried oxides, and with Al₂O₃/SiOxNy/Si(100) gate dielectrics. The former is significant for understanding the response of advanced SOI transistor structures (e.g., double gate devices), and the latter is important for the incorporation of high-K gate dielectrics into advanced MOS processes. The 1/f noise of MOSFETs fabricated on silicon-implanted SOI buried oxides shows little change after 1 Mrad(SiO₂) irradiation. Silicon implantation creates shallow electron traps in the buried oxide of the SOI devices, leading to improved radiation tolerance, but also additional noise and bias instabilities. Whether the traps that lead to these instabilities are filled or empty does not significantly affect the 1/f noise of the back-channel transistor. Low frequency noise in the strongly coupled front-to-back (quasi double-gate) mode of device operation is also investigated, and found to help mitigate the 1/f noise in fully depleted SOI MOSFETs. The decrease in noise is associated primarily with an increase in the number of carriers in the channel for this quasi double-gate mode of operation. In transistors with high-K dielectrics, the low-frequency noise is significantly larger than typically observed for high-quality thermal SiO₂ thin films.

Light emitting diodes (LEDs) are excellent candidates for the applications requiring low noise light sources with wavelengths ranging from 200 nm to 900 nm. These applications include the detection of fluorescence from protein molecules excited with the ultraviolet (UV) light (200-300nm) for identifying miniscule amounts of hazardous biological pathogens. The detection system including the light source must exhibit low noise and high stability over tens of minutes. In comparison with xenon, tungsten halogen lamps, lasers, and other conventional UV sources, UV LEDs are more stable, have lower noise, are smaller, cheaper, and easier to use. We report on the low frequency fluctuations of the current and light intensity of LEDs (fabricated by SET, Inc.) with wavelengths ranging from 265nm to 340nm. The results are compared with the noise properties of the halogen lamps and other commercially available LEDs with the wavelengths of 375nm, 505nm and 740nm. We show that the LEDs fabricated by Sensor Electronic technology, Inc. are suitable for studying steady state and time-varying UV fluorescence of biological materials. The correlation coefficient between the current and light intensity fluctuations varies with the LED current and load resistance. This dependence is explained in terms of the contributions to the 1/f noise from the active region and from the LED series resistance. The noise level could be reduced by operating the LEDs at a certain optimum current level and by using a large external series resistance (in the current source driving mode).

Three different sets of semiconductors light active devices were by low frequency noise diagnostic described. In the first set the low frequency noise of 2.3 μm CW GaSb based Laser Diodes was measured, in set II the noise characteristic of forward biased silicon monocrystalline solar cells were measured and in set III the noise characteristic of forward biased Si:H amorphous solar cells were measured. The results of noise measurement in all systems were compared.

In this paper the experimental results of a study conducted to investigate dependence of low-frequency noise on the geometrical shape of VLSI interconnect are discussed. The metal thin films are most commonly used in fabrication of these metallic interconnects. The interconnection lines of modern ICs have effective cross sections in the range of 1-5 square μm. Therefore, the operating currents of a few milliamps results in current densities in the range of MA/square cm. Under these conditions, the phenomenon of electromigration arises, which may lead to the failure of the interconnection lines in a time ranging from a few several hours to several years, depending on the subjected current density J and thermal stress T. To study the effect of subjected current densities and temperatures, low-frequency noise measurements were performed on a group of ten metal thin film VLSI interconnects. These measurements were carried out under stressing current densities between 1.0x10⁵ A/cm² and 2.2 x10⁶ A/cm² at different heating temperatures up to 280 ^° C. We used a sophisticated noise measurement system based on dual-channel dynamic signal analyzer and ultra low-noise amplifier to monitor and capture the noise spectra exhibited by the samples when subjected to electrical and thermal stress. The low-frequency noise measurement system and measurement technique, metal thin film sample design, and the behavior of these samples under subjected stressing conditions are discussed in the paper.

SiGe technology represents a remarkable success story for the microelectronics industry, and possesses the capability to fundamentally reshape the way broadband communications systems are conceived and built in the 21st century. From the first demonstration of a functional SiGe HBT in 1987, until the achievement of the present performance record of 375 GHz peak cutoff frequency, a mere 18 years has elapsed! The SiGe HBT is the first practical bandgap-engineered Si device, and has evolved from simple transistor and circuit demonstrations in a select few research laboratories to robust production in upwards of two-dozen manufacturing facilities around the world in 2005, and commercial products abound across a wide spectrum of commercial applications. This paper reviews the state-of-the-art in SiGe technology, discusses the design and operational principles of SiGe HBTs, and then focuses on the broadband and low-frequency noise characteristics of SiGe HBTs, emphasizing both the opportunities and the challenges which will necessarily be faced with continued device scaling.

1/f noise was investigated in a complementary polysilicon emitter bipolar process. Noise measurements were carried out for variable base bias resistance (R_S) to analyze how the contribution of each noise source changes as R_S is varied. Two noise measurement setups were used to identify different noise sources in the transistors: noise from the base current (S_IB), collector current (S_IC), and internal resistances (S_Vr). The coherence for transistors measured in both measurement setups were close to unity, implying a single dominant noise source. S_IB had the dominant contribution at lower bias currents. In this case, R_S was relatively larger than the input resistance of the transistor. Higher current measurements with a smaller R_S showed a dominant contribution from S_Vr. S_IB was modeled as a combination of the minority carrier diffusion fluctuations in the monosilicon and polysilicon emitter, and tunneling fluctuations through the interfacial oxide. A combination of the number and diffusion fluctuations of the minority carriers in the base was used to model S_IC. It was concluded that mainly originates from the fluctuations in the internal emitter resistance, which was ascribed to the tunneling fluctuations of the majority carriers through the interfacial oxide.

We present a comprehensive investigation of the fundamental differences in low frequency noise behavior between npn and pnp SiGe HBTs. Geometry effects on the low frequency noise are assessed, as well as the impact of interfacial oxide(IFO) thickness on pnp noise characteristics. Temperature measurements and ionizing radiation are used to probe the fundamental physics of 1/f noise in npn and pnp SiGe HBTs. The npn transistors show a stronger size dependence than the pnp transistors. The 1/f noise for pnp SiGe HBTs exhibits an exponential dependence on IFO thickness, indicating that IFO produces the main contribution. In most cases, the magnitude of the 1/f noise has quadratic dependence on the base current(I_B), the only exception being for the post-radiation npn transistor biased at low base currents, which exhibits a near-linear dependence on I_B. In the proton radiation experiments, the pnp devices show better radiation tolerance than the npn devices. The observed temperature dependence for both types is quiet weak, consistent a tunneling mechanism.

We present a comprehensive study of low-frequency noise mechanisms in 210 GHz SiGe HBTs using a variety of measurement techniques, and explain a unique scaling effect. The implication of these noise mechanisms on SiGe HBT compact modeling methodologies are also discussed.

The noise performance of PNP and NPN SiGe structures is examined by an experimentally verified hydrodynamic (HD) noise model. This model is a hierarchical numerical noise model because all noise parameters required by this model are generated by full band Monte Carlo bulk simulations leading to the methodology of the hierarchical numerical noise simulation. The hierarchical HD noise model is applied to compare the performance of NPN and PNP SiGe HBTs. The simulations include AC, DC and noise characteristics like the minimum noise figure. A similar noise performance for both types of devices is found.

This paper presents a nanowell device that detects the nano-scale electric field fluctuations due to ion cascade in bacteria. Solid-state nano devices allow for the measurement and analysis of fluctuation on the single cell or molecule scale, which can offer orders of magnitude higher sensitivity than microscopic measurements through conventional sensors. We fabricated a nanowell that is a 150nm wide gap in the middle of a titanium line on LiNbO3 substrate. The noise in the electrical current through this gap is measured. When bacteria are infected by bacteriophage, a large amount of ions are released, which yields spatiotemporal fluctuations of electric potential captured by this nanowell. It was demonstrated that this technology can be used to identify bacteria within minutes using the high specificity of phage/bacteria interaction. The perspective of building a biochip with hundreds of nano devices, immobilized phages and microfluidic channels so as to identify a large variety of bacteria is also discussed in this paper.

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

This is a review paper summarizing the recent reports on low-frequency noise in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with high dielectric constant (high-k) gate oxides. Although several such publications have appeared in the literature recently, the only unified theme among them is that the noise in these high-k gate stacks is considerably higher than that observed on conventional SiO₂ gate oxide transistors. In addition, interface- and bulk-dielectric trap-induced correlated carrier number and mobility fluctuations (Unified Model) seem to be the commonly accepted cause of these fluctuations. This report attempts to compile the published data, make comparisons between different high-k dielectrics with respect to 1/f noise characteristics and reach preliminary conclusions. Since there is still room for improvement in processing of high-k materials for MOSFET applications, the review represents merely a slice in time of the progress made, and not meant to be a fundamental, theoretical review.

In this paper, the performances and limitations related to the high frequency noise properties of SOI MOSFET Technology are investigated. The study is conducted through powerful analytical noise parameters calculation, experimental data, and physical based drift-diffusion noise modeling. In addition to the noise generated by the inner part of the active device, the influence of access resistances, overlap/fringing capacitances, tunneling gate current are discussed qualitatively and quantitatively. The paper ends up with a critical discussion related to the "New Era SOI Technology" to come and its influence on the noise performance.

An improved analysis of low frequency noise in ploy-Si TFT's is proposed in this paper. We present a simple parameter extraction method for 1/f noise sources in poly-Si TFT's based on a comprehensive model for noise generation. The sources for the low frequency noise are identified as the oxide traps in high current regime and the bulk traps in the grain boundary deletion region in low current regime. For high current regime, a simple and useful formula is developed from the Unified Model, which can be used for crystalline Si MOSFET's and SiGe MOSFET's also. For low current regime the bulk trap density in the grain boundary can be extracted utilizing the expression for the noise density considering the thermal activation of carriers from the traps which induces the fluctuations in the barrier height and hence the current noise. The extraction method is successfully applied to the experimental data from the literature with reasonable values for the noise parameters. The concept of mobility in poly-Si TFT's is elucidated. The work can also explain the experimental observation on the barrier height dependence of the low frequency drain current noise in poly-Si TFT's.

The flicker noise characteristics of MOSFETs with HfO₂, HfAlO_x, Al₂O₃ / HfO₂ gate stacks have been studied, where both n and p type devices having 10 Å or 40 Å SiO₂ interfacial layer (IFO) were considered. The corresponding equivalent oxide thickness (EOT) values were 23Å, 53Å for HfO₂; 28.5Å, 58.5Å for HfAlO_x; and 33Å, 63 Å for Al₂O₃ / HfO₂. Gate leakage currents were (~ 2-5x10^-5 A/cm²) which are 2 orders of magnitude lower compared to SiO₂ devices with similar oxide thickness. The positive and negative threshold shifts as derived from the threshold voltages of n, p devices, respectively, suggested the presence of interface states between poly-gate and dielectric. Normalized power spectral density plot vs. gate overdrive shows that the devices with thin interfacial oxide (IFO) layer exhibit about an order of magnitude higher noise than those with thicker IFO owing to higher number of traps in the high-k and to the fact that carrier tunneling distance is ~20 Å. The Unified Model representing the carrier number and correlated mobility fluctuations was used to extract the oxide trap density and Coulomb scattering coefficient values. In general, n-type HfO₂ devices yielded low noise, trap density and best mobility values compared to the other two gate stacks.

Klumperink et al., have recently had a number of publications on the low frequency noise of MOSFET’s under switched gate bias conditions. Since this is an important consideration in the low frequency noise in analog circuits with switching we have investigated the experimental technique used in some detail. No consideration was given to phase noise, a mixing with and modulation of the switched bias drain current by l/f noise in the analysis of the data. This can result in a response on the spectrum analyzer which corresponds very closely to the experimental data where the switched bias off gate voltage is near the threshold voltage. If the switched bias off gate voltage is near zero however we have also found a reduction in the l/f noise at low frequencies with switched bias. Here we have also investigated the time dependence of switched bias l/f noise and have found long term transients in the time domain.

The evolution of microprocessor miniaturization and performance, often described by Moore's law ^1,2, is close to the saturation limit. This is the part of a more general slowing down which is indicated by, among other things, the facts that Intel has failed with the 65 nm efforts and IBM has recently given up its personal computer market. In the present paper we would like to discuss some noise-related characteristic features of the present situation from the angle of noise and dissipation.

A technique integrating the noise analysis based testing and the conventional power supply current testing of CMOS analog integrated circuits is presented for bridging type faults due to manufacturing defects. The circuit under test (CUT) is a CMOS amplifier designed for operation at ± 2.5 V and implemented in 1.5 μm CMOS process. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. The amplifier circuit is analyzed and simulated in SPICE for its performance with and without fault injections. The faults in the CUT are identified by observing the variation in the equivalent noise voltage at the output of CUT. In power supply current testing, the current (I_PS) through the power supply voltage, V_DD is measured under the application of an AC input stimulus. The effect of parametric variation is taken into consideration by determining the tolerance limit using the Monte-Carlo analysis. The fault is identified if the power supply current, I_PS lies outside the deviation given by Monte-Carlo analysis. Simulation results are in close agreement with the corresponding experimental values.

Noise is an important factor in determining the sensitivity of CMOS imagers at low light levels. Both device or transistor thermal noise and l/f noise are contributing factors, correlated double sampling reduces the effect of both thermal noise and l/f noise but is less effective in reducing l/f noise as sampling time increases. Techniques to simulate noise in sampling circuits have only recently become available and are compared here to the older analytical techniques.

We review the physics of GaN-based devices including pyroelectric and piezoelectric sensors, GaN-based Heterostructure Field Effect Transistors (HFETs); SAW and acousto-optics devices; UV Light Emitting Diodes, and THz plasma wave electronics devices using GaN HFETs, paying special attention to polarization effects. We also discuss oscillating electron and hole islands in semiconductor GaN or AlGaN grains embedded into a pyroelectric matrix with a larger spontaneous polarization.

We report systematic investigations on hot-electron degradation in GaN-based HEMTs with different gate recess depths, d _r , fabricated by reactive ion etching. The experimental data stipulate two different mechanisms underlying the hot-electron degradations of the devices. During the initial phase of hot-electron injection significant changes were observed in the dc characteristics of the devices and the flicker noise power spectral density, S_V(f).The degradations were partially recovered by annealing the devices at 100^°C for 20 minutes. It is shown that for stress time t_s≤25 hours the reverse bias gate current, I_G, decreases systematically with t_s, whereas S_V(f) fluctuates randomly. Detailed analyses of S_V(f) measured over a wide range temperatures show that the initial degradations originate from the percolation of carriers in the 2DEG. The significant increase in the flicker noise during the initial phase of high-voltage stress is due to the generation of H⁺ at the AlGaN/GaN interface. The fluctuations in the magnitudes of S_V(f) for t_s≤25 hours originate from the motion of the H⁺ in the direction of the electric field. This results in the modulation of the percolation path leading to significant variations in S_V(f) as a function of t_s. For t_s>25 hours both I_G and S_V(f) are stabilized resulting from the drifting of the H⁺ away from the gate region. Further stressing beyond 25 hours indicate strong dependencies of the device lifetimes on d_r suggesting significant material degradation due to the reactive ion etching process for the fabrication of the gate recesses. Detailed characterization of the noise show that the final irreversible degradation is due to the generation of traps at the AlGaN/GaN interface.

It has been suggested the surface defects and dislocations could act as the leakage paths affecting the low-frequency noise performance of the AlGaN/GaN heterostructure field-effect transistors. In this paper we report results of the capacitance-voltage (CV) characterization of SiO₂-passivated Al_0.2Ga_0.8 N/GaN heterostructure field-effect transistors. From the measured frequency dependent CV profiling data, we identified the characteristics of the traps at the AlGaN/GaN interface adjoining the channel and on the surface along the ungated region between the gate and drain. Based on the measured data, the influence of the channel traps on the low-frequency noise spectra and the effect of the surface traps on possible leakage noise are analyzed and compared with previous studies.

A technique for testing CMOS analog integrated circuits is presented which is based on an analysis of the noise behavior of the circuit under test (CUT). The technique is simple and new. The CUT in the present work is an integrated CMOS amplifier circuit designed in a standard 1.5 μm n-well CMOS process for operation at ±;2.5 V. The bridging faults simulating possible manufacturing defects have been introduced using fault injection transistors. The faults in the CUT are detected by observing the variation in the noise at the output of CUT, which is the sum of noise contributed from each component in the circuit. An analytical noise model of the CUT has been developed with and without faults and results are compared with the corresponding data obtained from the simulation studies using SPICE.

Low-frequency noise measurements are usually performed by measuring the voltage across a dipole, or the current through a wire. Here we demonstrate the feasibility of the measurement of the noise power flowing through a line connecting two dipoles. A sampling wattmeter, with spectral display capabilities, having a bandwidth in the range 1 Hz - 10 kHz and sensitivity better than 10^-22 W/Hz is here described, and employed to measure the noise power flowing between two resistors at different temperatures. Possible applications of the device include noise thermometry, noise measurement of active devices under load condition, investigations of excess noise below thermal threshold.

While pseudo random number generators based on computational complexity are widely used for most of cryptographic applications and probabilistic simulations, the generation of true random numbers based on physical randomness is required to guarantee the advanced security of cryptographic systems. In this paper we present a method to exploit manufacturing variations, metastablity, and thermal noise in integrated circuits to generate random numbers. This metastability based physical random number generator provides a compact and low-power solution which can be fabricated using standard IC manufacturing processes. Test-chips were fabricated in TSMC 0.18um process and experimental results show that the generated random bits pass standard randomness tests successfully. The operation of the proposed scheme is robust against environmental changes since it can be re-calibrated to new environmental conditions such as temperature and power supply voltage.

The presence of thermal noise dictates that an energy barrier is needed to preserve a binary state. Therefore, all electronic devices contain at least one energy barrier to control electron flow. The barrier properties, such as height, length, and shape determine the operating characteristics of electronic devices. Furthermore, changes in the barrier shape require changes in charge density/distribution. Operation of all charge transport devices includes charging/discharging capacitances to change barrier height. In this paper we analyze energy dissipation for several schemes of charging capacitors. A basic assumption of Reversible Computing is that the computing system is completely isolated from the thermal bath, i. e., phonons are not coupled to the motion of the information-bearing particle. An isolated system is a mathematical abstraction never perfectly realized in practice. Coupling of the system to the rest of the world results in thermal noise and errors due to thermal excitations are equivalent to information erasure, and thus computation dissipates energy. Another source of energy dissipation is due to the need of measurement and control. To analyze this side of the problem, the Maxwell’s Demon is a useful abstraction. Proposals for “adiabatic circuits” do not make attempts to isolate the system from the thermal bath, hence the circuits cannot be reversible. We hold that apparent “energy savings” in models of adiabatic circuits result from neglecting the total energy needed by other parts of the system to implement the circuit. We are not aware of convincing experimental evidences that adiabatic circuits save wall-plug energy.