More on accelerating physical verification using STPRL: a novel language for test pattern generation

Ahmed Nouh

doi:10.1117/12.712389

21 March 2007 More on accelerating physical verification using STPRL: a novel language for test pattern generation

Ahmed Nouh

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65211T (2007) https://doi.org/10.1117/12.712389
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

In this work, test-patterns, test-cases and layout-patterns generations are widely investigated in the sense of turnaround time for creation and/or modification. STPRL, a novel behavioral modeling language for test-pattern creation, is being proposed. The turn-around time for both creation and modification is hugely reduced at no degradation in either accuracy or performance. Furthermore, STPRL provides considerable performance improvements in custom testpatterns creation over available automatic layout creation tools. Our method has been verified with real data at different node-technologies and for migration from and between different technology nodes.

Citation Download Citation

Ahmed Nouh "More on accelerating physical verification using STPRL: a novel language for test pattern generation", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211T (21 March 2007); https://doi.org/10.1117/12.712389

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