This PDF file contains the front matter associated with SPIE Proceedings Volume 7028, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and the Conference Committee listing.

Logic CMOS device scaling trend is described along the International Technology Roadmap for Semiconductors (ITRS) 2007 edition. For transistor performance improvement, geometrical scaling of gate length still plays an important role. At the same time, equivalent scaling such as metal gate and mobility enhancement is also indispensable. In order to break through the improvement limitation of planar bulk structure, new transistor structure such as FinFET will be introduced from 2010 or 2011 time frame. In long term, alternative materials and structures will be required to realize extremely high ballistic transport.

The development of semiconductor process for 32nm node is in progress. Immersion lithography has been introduced as an extension of 193nm lithograpy. In addition, DPL (Double patterning lithography) is becoming a strong candidate of next generation lithography. The extension of optical lithography increases more mask complexity and tighter specification of photomasks. CD performance is the most important issue in the advanced photomask technology. However, it is expected that conventional mask cannot satisfy the required mask specifications for 32nm node and beyond. Most of CD errors are contributed to the dry etching process. Mask CD variation is greatly influenced by the loading effect from dry etching of the absorber. As the required accuracy of the mask arises, Cr absorber thickness has been gradually thinner. CD linearity with the thinner Cr absorber thickness has better performance. However, it is difficult to apply thinner Cr absorber thickness simply under the condition of OD > 3, which is needed for wafer printing. So, we adopted MoSi absorber instead of conventional Cr absorber, because MoSi absorber has less micro and global loading effect than that of Cr absorber. By using MoSi absorber, we can reduce Cr thickness as a hardmask. The thinner Cr hardmask allows for reduce resist thickness and become same condition for conventional EB resist lithography. The lithography performances were confirmed by the simulation and wafer printing. The new MoSi absorber mask behaves similar to the conventional Cr absorber mask. The adoption of super thin Cr as a hardmask made it possible to reduce resist thickness. By the application of the thin resist and the latest tools, we'll improve the mask performance to meet the 32 nm generation specification.

193nm-immersion lithography is the most promising technology for 32nm-node device fabrication. A new Cr absorber (TFC) for 193-nm attenuated phase-shift blanks was developed to meet the photomask requirements without any additional process step, such as hardmask etching. TFC was introduced with a design concept of the vertical profile for shorter etching time, the over etching time reduction. As a result, the dry-etching time was dramatically improved by more than 20% shorter than the conventional Cr absorber (TF11) without any process changes. We confirmed that 150nm-resist thickness was possible by TFC. The 32nm technology-node requirement is fully supported by TFC with thinner CAR, such as resolution and CD performance.

193nm-immersion lithography is the most promising technology for 32nm-node device fabrication. At the 32nm technology-node, the performance of photomasks, not only phase-shift masks but also binary masks, needs to be improved, especially in "resolution" and "CD accuracy". To meet sub-100nm resolution with high precision, further thinning of resist thickness will be needed. To improve CD performance, we have designed a new Cr-on-glass (COG) blank for binary applications, having OD-3 at 193nm. This simple Cr structure can obtain superior performance with the conventional mask-making process. Since the hardmask concept is one of the alternative solutions, we have also designed a multilayered binary blank. The new COG blank (NTARC) was fully dry-etched with over 25% shorter etching time than NTAR7, which is a conventional COG blank. Thinner resist (up to 200nm) was possible for NTARC. NTARC with 200nm-thick resist showed superior resolution and CD linearity in all pattern categories. On the other hand, the multilayered binary stack gives us a wide etching margin for several etching steps. Super thin resist (up to 100nm) was suitable by using a Cr-hardmask on a MoSi-absorber structure (COMS). The COMS blanks showed superior performance, especially in tiny clear patterns, such as the isolated hole pattern. We confirmed that these new photomask blanks, NTARC and COMS, will meet the requirements for 32nm-node and beyond, for all aspects of mask-making.

Phase, along with defect levels and CD, must be closely monitored on 45nm technology node masks. The final phase shift of a mask is highly dependent on the ability of the etch tool to stop at precisely the correct depth. Developing etch processes and endpoint recipes for successful phase shift processing depends on rapid and accurate measurement of etch depth. In many mask shops, these measurements are made by either direct phase measurement tools or atomic force microscopes (AFM). These tools have relatively low throughput. In the case of the direct phase measurement tool, the large measurement spot size precludes the measurement of the small features most interesting to mask makers. A need exists for a relatively fast measurement tool that can be applied to features <1μm in size. As part of Oerlikon USA's continuous etch process improvement efforts, the etch depth measurement capabilities of a scatterometry based metrology tool were explored. Phase shift masks (one EAPSM, one AAPSM) were created to act as standards for our experiments. Regions of each mask were etched to various depths using an Oerlikon Mask Etcher system, and then measured with both a commercial AFM and an n&k Technology 1700-RT scatterometry tool. Using this data, recipes capable of measuring quartz trench features, partially-etched MoSi trench features, and bulk MoSi films were developed on the n&k 1700-RT. Phase uniformity data taken from actual etch experiments will be provided, as well as data showing the repeatability of each system, and a comparison of the relative measurement times.

High particle removal efficiency (PRE) up to 99%+ without damage to sub-50 nm linewidth features has been demonstrated using a mixed fluid jet technology and sulfur-free chemistry. This high PRE was achieved with several types of deposited particles, including polystyrene latex spheres. Damage-free cleaning was demonstrated on binary and phase shift masks with Cr and MoSi structures. All masks were processed using the Tetra^TM mask cleaning tool configured with the NanoDroplet^TM mixed fluid jet technology.

Damage to minute features of 45nm-node device masks occurred during megasonic cleaning. Since we were obliged to weaken the mechanical effect of megasonics in order to prevent the collapse of minute features, we could not obtain acceptable cleaning results. In order to manage the minute features, there is a need to develop a new mechanical cleaning method that causes less damage, but does not compromise the ability to remove particles. Cleaning using a two-fluid nozzle is a promising candidate. We investigated the two-fluid nozzle and compared it with megasonic cleaning, and we confirmed that the two-fluid nozzle achieved acceptable cleaning results without damaging 45nm-node device masks. Furthermore, for 32nm-node device masks, we have improved the two-fluid nozzle in terms of the cleaning energy distribution.

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.

Association of Super-Advanced Electronics Technologies (ASET) Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) started a 4-year development program for the total optimization of mask design, drawing, and inspection technologies to reduce photomask manufacturing costs in 2006. At the Mask Writing Equipment Technology Research Laboratory, we are developing an e-beam exposure system introducing concepts of MCC (multi column cell), CP (character projection), and VSB (variable shaped beam), which has several times higher throughput than currently commercially available e-beam writing systems.

The impending need of double patterning/double exposure techniques is accelerating the demand for higher pattern placement accuracy to be achieved in the upcoming lithography generations. One of the biggest error sources of pattern placement accuracy on an EB mask writer is the resist charging effect. In this paper, we provide a model to describe the resist charging behavior on a photomask written on our EBM-6000 system. We found this model was very effective in correcting and reducing the beam position error induced by the charging effect.

Application of double patterning technique has been discussed for lithography of HP 3X nm device generation. In this case, overlay budget for lithography becomes so hard that it is difficult to achieve it with only improvement of photomask's position accuracy. One of the factors of overlay error will be induced by distortion of photomask after chucking on the mask stage of exposure tool, because photomasks are bended by the force of vacuum chucking. Recently, mask flatness prediction technique was developed. This technique is simulating the surface shape of mask when it is on the mask stage by using the flatness data of free-standing state blank and the information of mask chucking stage. To use this predicted flatness data, it is possible to predict a pattern position error after exposed and it is possible to correct it on the photomask. A blank supplier developed the flatness data transfer system to mask vender. Every blanks are distinguished individually by 2D barcode mark on blank which including serial number. The flatness data of each blank is linked with this serial number, and mask vender can use this serial number as a key code to mask flatness data. We developed mask image position correction system by using 2D barcode mark linked to predicted flatness data, and position accuracy assurance system for these masks. And with these systems, we made some masks actually.

As the design rule with wafer process is getting smaller down below 50nm node, the specification of CDs on a mask is getting more tightened. Therefore, more tight and accurate E-Beam Lithography simulation is highly required in these days. However, in reality most of E-Beam simulation cases, there is a trade-off relationship between the accuracy and the simulation speed. Moreover, the necessity of full chip based simulation has been increasing in order to estimate more accurate mask CDs based on real process condition. Therefore, without consideration of long range correction algorithm such as fogging effect and loading effect correction in E-beam machine, it would be impossible and meaningless to pursue the full chip based simulation. In this paper, we introduce a breakthrough method to overcome the obstacles of E-Beam simulation. In-house E-beam simulator, ELIS (E-beam LIthography Simulator), has been upgraded to solve these problems. First, DP (Distributed Processing) strategy was applied to improve calculation speed. Secondly, the long range correction algorithm of E-beam machine was also applied to compute intensity of exposure on a full chip based (Mask). Finally, ELIS-DP has been evaluated possibility of expecting or analyzing CDs on full chip base.

Yield of a Variable Shaped Beam (VSB) created photomask is directly related to the quality of the fracture. The quality of a fracture is determined by three criteria: split CDs, slivers, and fracture consistency. Split CDs of figures whose widths are under the beam's shot size affect the quality due to adding an unnecessary shot registration error. Slivers, or extremely skinny shots, are harmful because they increase write time, adversely affect lithography patterning, and subsequently can cause inspection errors. Inconsistent fracturing of identical geometry compounds these issues that affect uniformity. Testmask structures devoted to grading the impact of slivers and consistency will be created, manufactured, and measured to enable statistical analysis of fracture data. These structures will be systematically designed to cover a wide range of sliver widths and feature geometries. The mean to target will be evaluated for these test structures, and from this, impact on CD linearity and CD uniformity can be judged. The effect of slivers on write time will be discussed in a more general scope. When evaluating the impact of slivers, five criteria should be investigated: sliver length, sliver width, proximity, avoidability, and location. Each of these criteria either affect lithography or write time. Determining how to define the maximum width of a sliver is fracture algorithm dependent, but this paper gives guidelines that should ease that process. The goal is to fracture identical geometry in an identical fashion, regardless of orientation or mirroring, while making the shots as large as possible and avoiding slivers; and when avoiding a sliver is impossible, trying to embed the sliver between large shots.

The minimum feature size of integrated circuit continues to shrink. At 32 nm and smaller nodes, mask linearity errors caused by short range proximity effects less than around 3um during the manufacturing of photomasks become more significant in the overall lithography error budget. To address this, we have carried out a study that: (1). models the short range mask error; (2). implements mask process correction (MPC) based on these mask error models; and (3). verifies the mask process corrections. In this paper we will demonstrate that application of MPC can significantly reduce mask errors with minimal increase in writing overhead.

To protect the reticle during shipping and storage, several reticle pod concepts have been proposed and evaluated in the last 10 years. MIRAI-Selete has been developing EUV reticle handling technology and evaluating EUV reticle pods for two years. In this paper, we report results of shipping tests and storage tests using CNE pods; the CNE pod is designed by Entegris using "Dual Pod Concept" which Canon and Nikon jointly proposed in 2004. The pod consists of an inner pod and an outer pod. The inner pod has two components, a baseplate and a cover; the base plate protects the reticle front surface and the cover protects the back surface from particle contamination in shipping, storage and loading to a reticle chuck in an exposure tool. The outer pod is a RSP-200 slightly modified to contain the inner pod in it. We carried out thirty shipping tests and several storage tests and found the CNE pods had very promising protecting performance during shipping and storage.

EUV mask damage caused by Ga focused ion beam irradiation during the mask defect repair was studied. The concentration of Ga atom implanted in the multilayer through the buffer layer was calculated by SRIM. The reflectivity of the multilayer was calculated from the Ga distribution below the capping layer surface. To validate the calculation, a multilayer sample was irradiated with Ga FIB, and then EUV reflectivity was measured. The measured reflectivity change was in good agreement with the calculated value. An aerial image of patterns with Ga implanted region was simulated. The impact of the estimated Ga absorption on the linewidth of 32 nm hp line pattern was found to be less than 1 nm.

As the semiconductor industry enters the 45nm node and beyond, the tolerable lithography process window significantly shrinks due to the decreasing k₁ factor and increasing lens NA required to meet product shrink goals. The usable depth of focus at the 45nm node for critical layer is less than 200nm and for the 32nm node it will approach 100nm. Consequently, process window aware Optical Proximity Correction (OPC) and Lithography Rule Check (LRC) become crucial to ensure the robustness of OPC to focus and dose variation. An accurately calibrated continuous process window model is the corner stone for successful process variation aware OPC and LRC. For ease of use, this calibrated model should be a continuous function of defocus and dose and able to interpolate and extrapolate in the usable process window. Lithographic proximity effects have an optical component and a resist component. As state of the art OPC simulation tool is capable of precise and fast optical simulation, however its treatment of chemical amplified resist effects is relatively crude and does not capture the complex behavior during acid & quencher reaction, diffusion and development. This in turn causes difficulties for a continuous process window model where the resist component plays an important role. We proposed a hybrid resist model, which is a superposition of a traditional OPC chemical amplified resist model and a first order resist bias model. Using Synopsys' OPC modeling software package-ProGen, we incorporated this hybrid resist model into the continuous process window (PW) modeling module, and very good model calibration performance was achieved.

Despite advanced resolution enhancement techniques (RET) and illumination techniques, several sources of variation in the pattern transfer process manifest as variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities. However, lithography simulation is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this work, we develop a predictive model of device linewidths after optical proximity correction (OPC) across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation. To model litho effects on 2D poly geometries in standard cell layouts, we rigorously identify layout parameters that affect the litho contour. We classify gate poly (devices) into different categories based on their geometric parameters as well as those of neighboring field poly shapes. To create a model, we create a design of experiments (DOE) for all device categories and perform OPC followed by through-process window litho simulation. To limit the runtime of OPC and litho simulation for the DOE, we reduce the layout parameter space with a rigorously qualified methodology for filtering out unimportant parameters. To allow prediction of the device contour, we model the device edge placement error (EPE) using a response surface methodology followed by polynomial regression. We have implemented our predictive linewidth modeling with foundry 90nm and 65nm technology, along with industry-strength OPC models and recipes. Using the regression models, we have performed prediction on standard-cell blocks and achieved a 3σ prediction accuracy of 2nm across the process window.

An approach to parameter sensitivity methodology for OPC modeling is enhanced, automated, and applied to generate production-quality models for a 32-nm logic node poly layer. Two parameter sensitivity models are generated and compared to a baseline model from the same experimental dataset. The three models are thoroughly investigated to demonstrate that parameter sensitivity can enhance advanced OPC models with essentially no impact on the time required for model optimization. Results also indicate that parameter sensitivity, if used improperly, can decrease model quality.

Continuous shrinkage of the design rule in LSI devices brings about greater difficulty in the manufacturing process. Since not only process engineers' efforts but also yield-centric layout optimization is becoming increasingly important, such optimization has recently become a focus of interest. One of the approached is lithographic hotspot modification in design data. Using lithography compliance check and a hotspot fixing system in the early stage of design, design with wider process margin can be obtained. In order to achieve higher process yield after hotspot fixing, layout should be carefully optimized to decrease pattern-dependent yield loss. Since yield value for the design will fluctuate sensitively as designed pattern are modified, pattern should be optimized based on a comprehensive consideration of yield loss covering parametric, systematic and random effects. In this work, using lithography simulation, a lithographic yield loss model is defined and applied for precise quantification of process yield loss in 45 nm logic design. Yield loss values of each cell for lithographic, parametric and random effects are estimated, and then layouts through multiple layers are optimized to decrease total yield loss. As a result, litho-yield loss is greatly improved without deteriorating total yield value. Thus, layout is obtained that reflects an awareness of overall process yield.

Extreme ultraviolet (EUV) lithography is seen as a main candidate for production of future generation computer technology. Due to the short wavelength of EUV light (≈ 13 nm) novel reflective masks have to be used in the production process. A prerequisite to meet the high quality requirements for these EUV masks is a simple and accurate method for absorber pattern profile characterization. In our previous work we demonstrated that the Finite Element Method (FEM) is very well suited for the simulation of EUV scatterometry and can be used to reconstruct EUV mask profiles from experimental scatterometric data. In this contribution we apply an indirect metrology method to periodic EUV line masks with different critical dimensions (140 nm and 540 nm) over a large range of duty cycles (1:2, ... , 1:20). We quantitatively compare the reconstructed absorber pattern parameters to values obtained from direct AFM and CD-SEM measurements. We analyze the reliability of the reconstruction for the given experimental data. For the CD of the absorber lines, the comparison shows agreement of the order of 1nm. Furthermore we discuss special numerical techniques like domain decomposition algorithms and high order finite elements and their importance for fast and accurate solution of the inverse problem.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using Samsung's current flash memory production device design. The fabrication of the template is discussed and the resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting results are described in terms of CD uniformity, etch results, and overlay.

A novel high-resolution model (HRM) filtering technique was proposed to describe litho-constrained layouts. Litho-constrained layouts are layouts that have difficulties to pattern or are highly sensitive to process-fluctuations under current lithography technologies. HRM applies a short-wavelength (or high NA) model simulation directly on the pre-OPC, original design layout to filter out low spatial-frequency regions, and retain high spatial-frequency components which are litho-constrained. Since no OPC neither mask-synthesis steps are involved, this new technique is highly efficient in run time and can be used in design stage to detect and fix litho-constrained patterns. This method has successfully captured all the hot-spots with less than 15% overshoots on a realistic 80 mm² full-chip M1 layout in 65nm technology node. A step by step derivation of this HRM technique is presented in this paper.

Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM flow required to continue shrinking designs in the low-k₁ lithography regime. The ability to understand and minimize MEEF during design optimization and RET application is essential to obtain a usable process window. The traditional limited-cutline approach to analyzing and characterizing MEEF is no longer sufficient to accommodate increasing design complexity. In this paper, we present a new method of edge-based MEEF for analyzing and characterizing MEEF-based hot spots that overcomes the limitations of the traditional cutline approach. Application of the technique to analyze full-field pixel-based two dimensional (2D) MEEF color maps of several different design clips is explained. Process window (PW) is the most important metric in lithography simulations for evaluating the performance of a given RET solution. Traditionally, process window calculation assumes a perfect mask, with no mask errors or corner rounding. In a low k₁ regime, MEEF increases enough that mask errors can no longer be ignored in PW evaluation. A method of calculating "MEEF-aware" common process windows and creating a MEEF-aware process variation (PV) band, including mask bias, is presented, and wafer image variability is examined under several process variations, including dose, defocus and mask error. Results of MEEF-aware source-mask optimization (SMO) and design rule exploration using inverse lithography technology (ILT) are also presented.

In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by creating a short-range mask process model (MPM) for each unique mask process and a long-range CD uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1) and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with the current results of this new dynamic application to improve hot spot verification through Brion Technologies' model-based mask verification loop.

As the feature size of LSI becomes smaller, the increase of mask manufacturing cost is becoming critical. Association of Super-Advanced Electronics Technologies (ASET) Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) started 4-year program for mask manufacturing cost reduction by total optimization of MDP, mask writing, and mask inspection. The total optimization is accomplished by close relationship and synergism of three fields, MDP, mask writing, and mask inspection. And also, the total optimization will be accomplished by sharing four key items, common data format, good use of repeating patterns, pattern prioritization based on design intent, and parallel processing. In this paper, we describe functions of these four key items in the three fields and present status of development.

This paper proposes new scanner fleet management utilizing programmed hotspot patterns. We have developed a methodology to control and adjust critical parameters of scanner, such as effective illumination shape and numerical aperture (NA), to obtain the same lithography performance. The purpose is to improve hotspot patterns and depth of focus (DOF) of each scanner. The method is carried out with a test mask having programmed hotspot patterns that are likely to become fatal errors for circuit reliability in wafer processing. Actual circuit patterns whose patterning fidelity is sensitive to the critical parameters are selected as the programmed hotspots. The mask also has various lithography process monitor marks, such as flare monitor pattern, MEF evaluation pattern and aberration monitor pattern, for OPE control and simulation. Using the same test mask for every scanner, we can reveal the variation of lithography performance within a "scanner fleet". The hotspot patterns on the mask and the patterns printed onto wafers are inspected by Die-to-Database (D2DB) EB inspection and a wafer D2DB EB inspection, respectively. Using those D2DB inspection systems, we can evaluate quantitatively the change of pattern shape from drawing data to wafer. The OPE adjustment and OPC feedback are corrected by using the simulation data acquired for the D2DB inspection. The quality of the evaluation provides accurate scanner fleet control, resulting in high productivity and cost effectiveness at wafer fabrication.

The challenge for the upcoming full-chip CD uniformity (CDU) control at 32nm and 22nm nodes is unprecedented with expected specifications never before attempted in semiconductor manufacturing. To achieve these requirements, OPC models not only must be accurate for full-chip process window characterization for fine-tuning and matching of the existing processes and exposure tools, but also be trust-worthy and predictive to enable processes to be developed in advance of next-generation photomasks, exposure tools, and resists. This new OPC requirement extends beyond the intended application scope for behavior-lumped models. Instead, separable OPC models are better suited, such that each model stage represents the physics and chemistry more completely in order to maintain reliable prediction accuracy. The resist, imaging tool, and mask models must each stand independently, allowing existing resist and mask models to be combined with new optics models based on exposure settings other than the one calibrated previously. In this paper, we assess multiple sets of experimental data that demonstrate the ability of the Tachyon^TM FEM (focus and exposure modeling) to separate the modeling of mask, optics, and resists. We examine the predictability improvements of using 3D mask models to replace thin mask model and the use of measured illumination source versus top-hat types. Our experimental wafer printing results show that OPC models calibrated in FEM to one optical setting can be extrapolated to different optical settings, with prediction accuracy commensurate with the calibration accuracy. We see up to 45% improvement with the measured illumination source, and up to 30% improvement with 3D mask. Additionally, we observe evidence of thin mask resist models that are compensating for 3D mask effect in our wafer data by as much as 60%.

Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present, mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost. We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF printing problems economically and accurately.

The extendibility of 2D-TCC technique to an isolated line of 45 nm width is investigated in this paper. The 2D-TCC technique optimizes mask patterns placing assist pattern automatically. For 45 nm line patterns, the assist pattern width generally becomes much smaller than the exposure wavelength of 193 nm. Thus, the impact of the topography of a mask is examined using an electro-magnetic field (EMF) simulation. This simulation indicates that unwanted assist pattern printings are brought about by assist patterns with a smaller size than expected by the Kirchhoff's approximation. The difference, however, can be easily solved by giving a bias to the main pattern in the optimized mask. The main pattern bias decreases DOF very little. Furthermore, DOF simulated with a thick mask model is roughly the same as that simulated with a thin mask model. Therefore the topography of the optimized mask does not have an influence on the assist pattern position of the optimized mask. From these results, we have confirmed that the 2D-TCC technique can be extended to the optimization of 45 nm line patterns. As one of the notable features, the optimized aperiodic assist pattern greatly reduces MEEF compared with the conventional periodic assist pattern. To verify the feasibility of the 2D-TCC technique for 45 nm line, we performed experiment with an optimized mask. Experimental results showed that DOF increased with the number of assist pattern as simulation indicated. In addition, a defect whose length was twice that of the assist pattern did not have an influence on CD. From these results we have confirmed that the 2D-TCC technique can enhance the resolution of 45 nm line and has practical feasibility.

When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. In this paper, we will explore the capability of using the double pattern technique (DPT) to extend the resolution capability of the water-based immersion lithography and examine the readiness of EUV to carry the lithography resolution capability beyond the 32 nm HP. The DPT, whether done in two litho and etch steps (LELE) or using the side wall spacer and sacrificial layer technique (SPT), will require significant improvement in CDU and overlay process control performance. We will report the experimental results in exploring the CDU and overlay performance of the LELE and the SPT options. We will also demonstrate the need to perform full field and full wafer process corrections to compensate for dual CDU populations and overlay entangled CDU variations. Furthermore, we will make an assessment of EUV readiness to further extend the lithography resolution capability beyond the 32 nm half-pitch.

SRAF insertion through inverse microlithography methodologies has been explored at length in recent years as one of the most promising approaches to determining the right placements of Model-based SRAF (MBSRAF) for complex two dimensional geometrical configurations for advanced nodes. This work will discuss the latest development of MBSRAF insertion software at Mentor Graphics. The software system operates on the principles of inverse methods of microlithography or pixel inversion. The ability to examine the image of every pixel in the work region as well as the mathematical solution to synthesize the mask shapes as a cost minimization problem make it possible to reliably deal with SRAF insertion for advanced illumination schemes such as quasar, dipole and cross-quad. Pixel inversion involving high transmission attenuated PSM as well as hard PSM will be also discussed. We will also report on the MRC capability to make the pixel inversion mask shapes manufacturable.

A spacer patterning technology (SP) has the possibility of extending optical lithography to below 40nm half-pitch devices. Since the spacer patterning process necessitates somewhat more complicated wafer process flow, the CD variation on wafers involves more process error sources compared with conventional exposure patterning process. This implies that, for the spacer patterning process innovation in determining specifications for each unit process is requried. In particular, it is important to determine mask-related specifications in order to select high-end mask fabrication strategies for mask writing tools, mask process development, materials, inspection tools, and so on. The purpose of this paper is to discuss how to consider mask specification in spacer patterning process for 40nm half-pitch and beyond.

High NA and Ultra-High NA (NA>1.0) applications for low k₁ imaging strongly demand the adoption of polarized illumination as a resolution enhancement technology since proper illumination polarization configuration can greatly improve the image contrast hence pattern printing fidelity and the effectiveness of optical proximity correction (OPC). However, current OPC/RET modeling software can only model the light source polarization of simple types, such as TE, TM, X, Y, or sector polarization with relatively simple configuration. Realistic polarized light used in scanners is more complex than the aforementioned simple ones. As a result, simulation accuracy and quality of the OPC result will be compromised by the simplification of the light source polarization modeling in the traditional approach. With ever shrinking CD error budget in the manufacturing of IC's at advanced technology nodes, more accurate and comprehensive illumination source modeling for lithography simulations and OPC/RET is needed. On the other hand, for polarized illumination to be fully effective, ideally all the components in the optical lithography system should not alter the polarization state of light during its propagation from illuminator to wafer surface. In current OPC modeling tools, it is typically assumed that the amplitude and polarization state of the light do not change as it passes through the projection lens pupil, i.e. the polarization aberration of projection lens pupil is ignored. However, in reality, the projection lens pupil of the scanner does change the amplitude and the polarization state to some extent, and ignorance of projection pupil induced polarization state and amplitude changes will cause CD errors un-tolerable at the 45nm device generation and beyond. We developed an OPC-deployable modeling approach to model arbitrarily polarized light source and arbitrarily polarized projection lens pupil. Based on polarization state vector descriptions of a general illumination source, this modeling approach unifies optical simulations of unpolarized, partially polarized, and completely polarized illuminations. The polarization aberration imposed by the projection lens pupil is modeled via Jones matrix format, and it is applicable to arbitrary polarization aberrations imposed by any components in the lithography system that can be characterized in Jones matrix format. Numerical experiments were performed to study CD impact from illumination polarization and projection lens pupil polarization aberrations, and up to several nanometers impact on optical proximity effect (OPE) was observed, which is not negligible given the extremely stringent CD error budget at 45nm node and beyond. Based on an experimentally measured Jones matrix pupil which intrinsically provides a much better approximation to the physical scanner projection pupil, we propose a more physics-centric methodology to evaluate the optical model accuracy of OPC simulator.

Mask specifications of the pitch splitting type double patterning for 22nm node and beyond in logic devices have been discussed. The influences of the mask CD error and the mask induced overlay error on wafer CD have been investigated in both cases of bright field and dark filed. The specification for intra-layer overlay alignment is much smaller than inter-layer one. The specification of mask CD uniformity for dark is more challenging. In order to overcome the technology gap between single patterning and double patterning, many things will have to be improved.

We report on the experimental observation of mask transmission resonances in line/space gratings on bi-layer mask stacks and on the validation by mask 3D lithographic simulations. The mask transmission resonances manifest themselves as a local enhancement in the dose-to-size curve through mask line width for a given pitch targeted to a fixed wafer CD. We observed this resonance in gratings on a bi-layer Ta/SiON 1% attenuated phase shift mask (att.PSM). We relate the finding to a local transmission loss of the propagating diffraction orders in this range of mask line widths. This resonant-type anomaly has a large impact on the imaging performance of the mask stack. The through-mask-line-width behavior of the mask error enhancement factor (MEEF) shows strong variations and even negative MEEF values around the position of this resonance, which stem from the local dose-to-size enhancement. More precisely, the behavior of the MEEF can be well predicted by the differential of the dose-to-size curve. In this study we investigate both by experiments and simulations the dependency of this mask transmission resonance on various lithographic conditions such as incidence angle and polarization state of the incoming light, grating pitch, and mask material. Based on our findings we provide an explanation of the underlying optical mechanism.

Stability of across field line variation (ACLV) is crucial in advanced semiconductor manufacturing. Degraded signatures cause deterioration of transistor parameters and yield loss. After having contained haze issues, the IC industry is now confronting a new reticle degradation mechanism. It has been reported, that targeting energy is changing with the number of exposures and later on a rapid increase of ACLV is observed. Although effective monitoring and correction methods have been introduced, the root cause of this type of reticle degradation has not been fully elucidated. Our AIMS^TM, SEM and optical CD measurements on reticle demonstrated consistency with wafer CD measurements and clearly show that pattern distortions on wafers originate from the front side of the reticle. The results indicate the transmission loss to be gradually distributed over the reticle surface causing CD variations. In the most acute case, changes in the center area could be detected by the reticle inspection tool. Dependency of degradation rate on percentage of the clear field on the reticle and reticle type was observed. Finally, using a variety of analytical techniques including AFM, ion and gas chromatography, TOF-SIMS, Auger and TEM we have been able to identify the root cause of this problem. Our experimental results do show that the structural degradation of the absorber film is the primary cause for CD change. Possible mechanisms behind this effect are discussed.

In the relentless pursuit of device miniaturization and sustainable yield performance, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and sub-resolution assist feature (SRAF) are identified as enabling technologies that fuel the industry. The introduction of advanced reticles, however, considerably augments the mask error enhancement factor (MEEF) where the growth of progressive defects or haze is accelerated by repeated laser exposure, and continues to be a source of reticle degradation threatening device yield. Previous investigations have identified ammonium sulfate, cyanuric acid and ammonium oxalate as the primary and most concerning species found in both mask shop and wafer fabs. In this work, magnesium sulfate is used to emulate crystal growth due to its identical optical properties to ammonium sulfate. A technique has been developed to deposit magnesium sulfate of varying concentrations onto chemically cleaned reticle surfaces. These defects are then inspected with a high resolution reticle inspection system enabled with MEEF detector Litho3. Upon inspection, defects are classified and analyzed with respect to their location relative to device geometry, optical transmission loss as well as the residing surface. Ammonium oxalate crystals are also deposited separately onto reticle surface to comprehend the impact of crystal type and population on defect printability. Compositional analysis are carried out using Raman spectroscopy and time-of-flight secondary ion mass spectroscopy (TOF-SIMS) to correlate the amount of magnesium sulfate and ammonium oxalate crystals with transmission loss. Such emulation study of various crystal formulation mimics progressing stages of crystallization and allows a mechanistic understanding of crystal congregation, transmission loss and defect printability.

It is known that PSM pattern edge (MoSiON/Qz boundary) of EA-PSM mask is the weakest point against Haze occurrence in real mass production. Based on the understanding of these phenomena, we have developed very efficient ways to protect PSM pattern edge from Haze defect formation even after normal SPM cleaning processes. Oxide layer formulated on the PSM pattern (including pattern top and side) is actively trapping chemical ions existing on the surface and inside bulk of mask substrate, preventing their motion or diffusion toward Haze defect creation during laser exposure. As a result, we are able to reduce cleaning frequency of each EA-PSM mask set without Haze issues and thereby dramatically expand their life time in real mass production.

The transition to sub 45 nm technology nodes presents a significant technical challenge for mask repair due to a number of previously lesser known physical phenomena. Nanomachining technology, which has a history of equally successful repair of all photomask types-including Cr binary masks, has not been immune to these challenges. This has led to the development of a number of distinctly new processes to meet these technical requirements. In one of the two new processes reviewed in this work, the bulk of the defect is removed by applying compressive instead of tangential stresses to the NanoBit^TM during repair. This allows for 45 nm and smaller repairs, with sidewall angles and aspect ratios greater than 70° and 2:1 respectively, in open mask structures. For repair in closed-or missing defect-structures, a process was developed to minimize tip deflection away from the designated repair box boundaries for accurate two dimensional shape reconstructions of deep and complex patterns. The successful application of this technique is shown for actinic phase-correct missing and partial CPL, EAPSM, and Cr-absorber square contacts at these nodes. Additionally, the potential of these new processes to enable higher aspect advanced NanoBit^TM designs for robust mask repair, and the new processes developed to effectively clean nanomachining debris from these advanced mask structures are discussed to provide a complete review of these solutions and their supporting technologies.

It has been previously demonstrated that wafer CD uniformity can be improved via an ultrafast laser system. The system provides local CD Control (CDC) by writing inside the bulk of photomasks. Intra-field CD variation correction has been implemented effectively in mask-shops and fabs based on CD-SEM and Scatterometry (Optical CD or OCD) as the CD data source. Using wafer CD data allows correction of all wafer field CD contributors at once, but does not allow correcting for mask CD signature alone. For mask shops attempting to improve CDU of the mask regardless of the exposure tool, it is a better practice to use only mask CD data as the CD data source. In this study, we investigate the use of an aerial imaging system AIMS^TM45-193i (AIMS45) as the mask CD data source for the CDC process. In order to determine the predictive value of the AIMS45 as input to the CDC process, we have created a programmed CD mask with both 45nm and 65nm node L/S and hole patterns. The programmed CD mask has CD errors of up to 20nm in 2.5nm steps (4X). The programmed CD mask was measured by AIMS45, defining the CDU map of the programmed CD mask. The CDU data was then used by Pixer CDC200^TM to correct the CDU and bring it back to a flat, almost ideal CDU. In order to confirm that real CDU improvement on wafer had been achieved, the mask was printed before and after CDC on an immersion scanner at IMEC and results of pre and post CD data were compared.

Advanced photomasks for low-k₁ lithography, are prone to various defects sources: contamination, geometry, transmission, phase, etc. These defects exhibit a complex relation between the signal from an imaging detector and its print related impact, with important consequences for the performance of the detection scheme under nuisance-ubiquity conditions. We studied numerically several imaging schemes, with respect to their defect detection signal and its relation to the associated CD effect. We show that for actinic aerial imaging detection the signal is tightly correlated and linearly scaled with the induced CD variation regardless of defect source and location. Conversely, the correlation of non-actinic and/or non-aerial (high-resolution based) detection signal with printing effect is poor. Whereas the linear behavior characterizing aerial imaging is independent of the distribution of defect attributes, the statistics of non-aerial defect signal is shown to be highly sensitive to defect distribution. Such non-aerial detection schemes would generally have to compromise detection sensitivity in order to maintain a constant nuisance false alarm rate. Aerial imaging is therefore the optimal discriminator between printing and non-printing defects. The tight linear correlation between defect signal and CD effect in aerial inspection systems, allows for an optimized and effective mask inspection, suitable for all mask types and technologies. Specifically, we show here that such a tool allows a straightforward migration from 65nm node to 45nm and 32nm with double patterning, by tuning the detection threshold without being flooded by nuisance induced false alarms.

High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yield-limiting mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newly-developed Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects on wafers. WPI is a new inspection mode that has been developed by KLA-Tencor and is currently under test with multiple customers. It employs the same transmitted and reflected-light high-resolution images as the industry-standard high-resolution inspections, but with much more sophisticated processing involved. A rigorous mask pattern recovery algorithm is used to convert the transmitted and reflected light images into a modeled representation of the reticle. Lithographic modeling of the scanner is then used to generate an aerial image of the mask. This is followed by resist modeling to determine the exposure of the photoresist. The defect detectors are then applied on this photoresist plane so that only printing defects are detected. Note that no hardware modifications to the inspection system are required to enable this detector. The same tool will be able to perform both our standard High Resolution inspections and the Wafer Plane Inspection detector. This approach has several important features. The ability to ignore non-printing defects and to apply additional effective sensitivity in high MEEF areas enables advanced node development. In addition, the modeling allows the inclusion of important polarization effects that occur in the resist for high NA operation. This allows for the results to better match wafer print results compared to alternate approaches. Finally, the simulation easily allows for the application of arbitrary illumination profiles. With this approach, users of WPI can make use of unique or custom scanner illumination profiles. This allows the more precise modeling of profiles without inspection system hardware modification or loss of company intellectual property. This paper examines WPI in Die:Die mode. Future work includes a review of Die:Database WPI capability.

A major challenge of low-k1 microlithography that has to be addressed by any photomask defect detection strategy is the complex relation between the signal of the defect in the detector and its impact, in terms of printing errors, on the processed wafer. This non-trivial relation is immanent to the large MEEF values characterizing lithography at sub-wavelength features. One common method to work around this problem is to use aerial imaging optics which emulates the stepper exposure process. Currently available aerial inspection and review tools based on the well established fact that CD variation in the aerial image closely represents the CD variation on the wafer. Published literature explains why a defect's printing effect can be captured, with high correlation, by aerial imaging optics. Here we describe a novel connection between a defect's detection signal and the printed CD variation on an adjacent pattern. This connection can be exploited by aerial imaging mask inspection systems to ensure that their detection thresholds are set to detect CD variation of a given threshold. We show that under aerial imaging conditions, the defect signal and CD variation are linearly related, regardless of defect's attributes, provided that the defect resides close to a pattern's transition edge, or is surrounded by a dense pattern. We present experimental results, demonstrating this linear scaling between the defect signal and CD variation, and show practical application results of aerial imaging mask inspection, with implications to production mask fab.

Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMS^TM.

Conventionally, pattern inspection is performed on completed reticles. In other words, the completed circuit pattern on a reticle is inspected after etching and removing the resist. This pattern consists of the transmission region (Qz), half transmission region (MoSi) and shading region (Cr). If the process stage where a detected defect occurred can be specified, detection can be made at an earlier process stage, enabling an improvement in the process and/or yield. When inspecting the resist pattern on a reticle before the etching process, points such as the endurance of the resist against the inspection light beam and the effect of the gas that is generated by irradiation must be considered. In addition to there being no damage to the resist pattern, there must also be no contamination of the optical elements caused by outgases. To prevent contamination, therefore, we developed a cassette-type enclosure with gasproof windows in which the reticle is set, thus shutting out outgases. Also, because the image of the resist pattern is very different from a normal pattern, we needed to develop various functions, such as algorithms, to detect defects on the resist pattern. This time, we have successfully developed a resist pattern inspection function for the LM7500 reticle inspection system. This function enables both die-to-database and die-to-die inspection and features an inspection light wavelength of 266 nm, allowing the detection of smaller defects that could not be detected with an i-line (365 nm) inspection system.

Single mode inspections, using die-to-die Transmitted (ddT) or die-to-die Reflected (ddR) modes, provides a high level of sensitivity to opaque and clear defects on reticles. Die-to-die (DD) inspections however, cannot inspect the scribes or frames which are potential locations for haze growth. Historically, STARLight-2^TM (SL2) has been the only mode effectively utilized for contamination inspection in reticle scribes and frames. However, SL2 is designed for identifying contamination and not pattern defects on a mask. The solution presented here is Fast Integrated Inspection which includes ddT, ddR, and SL2, and allows the user to inspect a reticle for pattern and contamination defects over patterned areas and scribes simultaneously, and in unit time.

Lithographic process steps used in today's integrated circuit production require tight control of critical dimensions (CD). With new design rules dropping to 32 nm and emerging double patterning processes, parameters that were of secondary importance in previous technology generations have now become determining for the overall CD budget in the wafer fab. One of these key parameters is the intra-field mask CD uniformity (CDU) error, which is considered to consume an increasing portion of the overall CD budget for IC fabrication process. Consequently, it has become necessary to monitor and characterize CDU in both the maskshop and the wafer fab. Here, we describe the introduction of a new application for CDU monitoring into the mask making process at Samsung. The IntenCD^TM application, developed by Applied Materials, is implemented on an aerial mask inspection tool. It uses transmission inspection data, which contains information about CD variation over the mask, to create a dense yet accurate CDU map of the whole mask. This CDU map is generated in parallel to the normal defect inspection run, thus adding minimal overhead to the regular inspection time. We present experimental data showing examples of mask induced CD variations from various sources such as geometry, transmission and phase variations. We show how these small variations were captured by IntenCD^TM and demonstrate a high level of correlation between CD SEM analysis and IntenCD^TM mapping of mask CDU. Finally, we suggest a scheme for integrating the IntenCD^TM application as part of mask qualification procedure at maskshops.

Aggressive line width and other features of interest in advanced-technology node designs are achieved by using pattern-related resolution enhancement techniques (RET) coupled with mask transmission effects. Mask transmission effects, such as phase shift, are controlled by physical parameters, including mask blank material characteristics and mask architecture. In the case of advanced phase shift masks, the uniformity of transmitted phase, affected by both material properties and thickness, can become a dominant factor in achieving the final wafer CD targets. While traditional mask inspection tools are capable of detecting geometrical variation, detecting phase non-uniformity effects requires complementary, slow analytical tools. AMAT's IntenCD^TM is a novel application for advanced PSM masks which can be used for CD variation control in mask qualification. IntenCD captures mask CD variations in the aerial image regardless of the geometrical or physical aspect of its origin, producing a high-definition CDU map of the reticle. In this paper, we focus on a case study encountered at MP Mask where a PSM mask was sent to the fab to confirm large CD variations on a printed wafer due to mask etching process issues. Conventional defect inspection was not capable of detecting this excursion. The effect was clearly related to phase layer thickness as verified using an Atomic Force Microscope (AFM) tool. We show how the novel IntenCD application integrated into the aerial image mask inspection tool enables accurate prediction of CD variation in the aerial image due to mask phase errors.

In 45nm node and beyond, since mask topography effect is not ignorable, 3D simulation is required for precise printing performance evaluation and mask CD bias optimization. Therefore, the difference between real mask and 3D mask model on simulation needs to be clarified. Verification of 3D mask model by diffraction intensity measurement with AIMSTM45-193i was discussed in our previous works. In various conditions (mask materials, pattern dimensions and CD-SEMs), the diffraction intensity measured on actual masks were agreed to 3D simulations by introducing constant CD offset. The cause of the CD difference was explained to be mainly due to electron beam size by using simple SEM image simulation. In this work, we introduce the new procedure to measure diffraction intensity by AIMSTM in order to confirm the CD difference between 3D mask model and CD-SEM more accurately because the agreement of diffraction intensity between AIMSTM and simulation was not perfect especially for 1st order's diffraction. As a result, the value of CD difference was slightly changed on the same mask by using the same CD-SEM. Measured diffraction intensity showed better matching to 3D simulation results with the constant CD offset on all evaluated conditions. Secondary, to confirm how accurately printing performance could be predicted by CD-SEM measurement results, MEEF difference calculated from diffraction intensity between 3D simulation and CD-SEM with the offset was confirmed. Additionally, this method was extended to hole patterns. Measured diffraction intensity was matched to simulation result with the same CD offset with line/space patterns and appropriate corner rounding.

The application of aggressive Optical Proximity Correction (OPC) has permitted the extension of advanced lithographic technologies. OPC is also the source of challenges for the mask-maker. Small shapes between features and highly-fragmented edges in the design data are difficult to reproduce on masks and even more difficult to measure exactly with CD-SEM, which requires not only tool stability but also better measurement methods. To cope with this problem, we have been focusing on finding better methods for measuring actual mask Critical Dimension (CD) that would show a good correlation to wafer CD. In BACUS 2006, we presented an effective measurement for closed patterns, which is "area measurement". In time paper we are introducing new potential solution, which include a reliable method, distance measurement, for certain types of unclosed patterns. For instance, we evaluated an unclosed pattern which couldn't be measured with Region of Interest (ROI) that is large enough, and found a reliable method, Distance ROI. Though the method has a major drawback of image tilt, we also found an approach to avoid this. Finally we verified that Distance ROI could be new solution for unclosed patterns by jointly applying tilt monitoring, beam rotation correction, and area scan.

As design rule of memory device is shrinking, the various errors obtained by process, such as line edge roughness, local CD variation and electron beam shot placement error, are significant to CD measurement results on mask and wafer. Reliable CD measurement is needed to represent real feature size of mask and wafer results in high accurate CD target and uniformity by various CD correction techniques before mask fabrication and after. Recently light transmittance control technique on mask has been introduced, which reduce the field CD variation of wafer [1]. To correct the wafer field CD uniformity by selective control of the light transmittance of mask, good correlation of mask CD and wafer field CD is important [2][3]. AIMS (aerial image measurement and simulation) or light intensity uniformity of inspection tools or other light intensity measurement tools are generally used to measure mask CD uniformity on mask. In this study, mask CD uniformity measured by CD-SEM was used to compensate the field CD variation on wafer, by enhancing the correlation between wafer field CD uniformity and mask using spatial filtering of SEM image and area CD measurement concept. Expected residual error of wafer field CD error using correction of mask CD uniformity were compared to wafer CD variation by selective light correction using wafer CD uniformity map.

Anticipating the cost of ownership (COO) of different lithography approaches into the future is an act of faith. It requires that one believe that all of the lithographic problems with next generation lithography (NGL) approaches will be sufficiently resolved to support the production of manufacturing wafers. This paper assumes that all of the necessary technologies will be available in the future and that the cost of the components can be extrapolated from historic cost trends. Mask and wafer costs of a single critical lithography layer for the 65, 45, 32 and 22 nm half-pitch (HP) nodes will be compared for immersion, double process (DP), double expose (DE), extreme ultraviolet (EUV), and imprint technologies. The mask COO analysis assumes that the basic yield of an optical mask is constant from node to node and that the infrastructure that allows this performance will be in place when the technologies are needed. The primary differences in mask costs among lithography approaches are driven by the patterning write time and materials. The wafer COO is driven by the mask cost (for the low wafer-per-mask use case), the lithography tool cost, and the effective wafers per hour (wph) for the lithography approach being considered.

Extreme Ultra Violet Lithography (EUVL) is one of promising candidates for next generation lithography, 32nm node and beyond. Authors are developing EUV mask process targeting full field EUV exposure tool. Unlike the conventional optical mask, EUV mask is reflective type mask. To reflect 13.5nm wavelength light, 40 pairs of Mo/Si multilayer (ML) is used for reflective layer. Reflective layer is covered by capping layer. The capping layer protect reflective layer from absorber etching, defect repair and environmental condition. Top of absorber layer is covered by low reflective (LR) layer to achieve high contrast between the etched and not etched portion. Back side of EUV mask is covered by conductive film for electrostatic chuck use. In this paper, we will report current process development status of EUV mask for full field EUV exposure tool. Absorber patterning process including resist patterning and absorber etching were developed. Thin resist use and small resist damage dry etching process achieved pattern resolution of 32nm node. Defect inspection was also evaluated using DUV reticle inspection tool. Ta-based absorber on ruthenium (Ru) capped ML blanks was used for this evaluation. Because, Ru material has high resistivity to absorber etching plasma, it enable buffer layer less EUV mask structure. Ru also has better property on oxidation resistance compared to standard silicon (Si) capping layer.

The effects of mask absorber thickness on printability in EUV lithography was studied from the viewpoint of lithographic requirements which can give high imaging contrast and reduce shadowing effect. From lithography simulation, optimum thickness range of mask absorber (LR-TaBN) for exposure latitude was predicted, and the effect of absorber thickness on MEF and H-V (Horizontal - Vertical) printed CD difference was determined using resist blur model. From printability experiments with a Small Field Exposure Tool (SFET) and with high resolution resist, optimum thickness of LR-TaBN absorber was demonstrated. When thinner absorber mask is employed in EUVL for ULSI chip production, it becomes necessary to introduce EUV light shield area in order to suppress the leakage of EUV light from neighboring exposure shots. Resist pattern CD change from the neighboring exposure shots was estimated by lithography simulation.

The impact of mask blank surface roughness and mirror surface roughness on the defect inspection signal is presented. The power spectrum density (PSD) of the roughness is assumed to be inversely proportional to the square of the spatial frequency. The PSD was estimated based on the mask blank surface roughness (rms), and then the background intensity was calculated using the PSD of the spatial frequencies between the inner and outer NA. The results indicate that the larger outer NA leads to an increase in the background intensity, and that a mask blank roughness of 0.15 nm generates a background intensity of 0.15 - 0.23 %. We also analyzed the effect of the mirror surface roughness on the background intensity and on the defect signal contrast. A point spread function (PSF) of scattered light from the mirror surface was calculated using the estimated PSD, and the defect images were simulated for the inspection optics by employing Fourier technique. The degradation of defect images caused by the mirror roughness was calculated by using the convolution of the PSF with the simulated images. Based on the results, it is concluded that the roughness has a large impact on the maximum intensity of the defect signal but has little effect on the background intensity. It was also learned that the degradation rate of the defect signal contrast is approximately proportional to the square of the mirror roughness.

We utilized a newly developed low acceleration voltage FIB (Focused Ion Beam) system and evaluated the process for repairing the absorber layer on EUVL mask. During the etching of the absorber layer, which is a step in conventional repair technique, a phenomenon of side-etching of Ta-nitride layer with XeF₂ gas was observed. This phenomenon was considered to be caused by the isotropic etching of the Ta-nitride layer with XeF2 gas. We then added another gas for etching and evaluated the new process to prevent the side-etching of Ta-nitride layer. In this paper, we will report four evaluation results of EUVL mask pattern defect repair using FIB-GAE (Gas Assisted Etching). The first one is the problem of pattern topography after conventional repairing process and the reaction mechanism of gas assisted etching of Ta based absorber. The second evaluation result is addressed in two parts. One is the evaluation of a new gas assisted etching process that employs an additional gas that has an ability to control the etching rate of absorber layer. The second part addresses the repairing accuracy of EUVL mask pattern. The third is the basic etching performance e.g. etching rate of Ta based absorber, Cr based buffer, and Si based capping layer. The fourth and the last evaluation is the application of the newly developed gas assisted etching process on programmed bridge defect in narrow pitched L/S patterns.

As the semiconductor industry requires lithography suitable for 32-nm node, extreme ultraviolet lithography (EUVL) has the potential to provide this capability for the mass fabrication of semiconductor devices. But because an extreme ultraviolet (EUV) lithography exposure system is operated in vacuum, during irradiation by EUV light, hydrocarbons are decomposed in vacuum1-3, for example, by the out-gassing from EUV mask, and contaminate the surface of imaging optics which is coated with Mo/Si multi-layers with carbon. Thus, this contamination not only reduces the reflectivity of the Mo/Si multi-layers of imaging optics and degrades the exposure uniformity, but also degrades the resolution of the imaging optics. In this study, as we examined the volume of the out-gassing and the species from EUV mask after every process for EUV mask production, we will control the carbon contamination of EUV mask. Keywords: EUV, carbon contamination, reflectance, out-gassing

Templates for UV-Nano-imprint lithography (NIL) have been rapidly improved these days. Feature sizes of the templates have come to be less than 30 nm. Consequently, metrology has been also one of the challenges to fabricate templates for UV-NIL. There are many issues in metrology for the templates; for instance, necessity of the higher resolution, critical dimension (CD) accuracy and repeatability for measurement tools. In this paper, we will focus on an optimization of measuring conditions for the templates of UV-NIL. And we will discuss some measuring techniques for CD precision and repeatability using a CD-SEM and a scanning probe microscope.

UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns. We have been focused on the resolution improvement in mask making, and with a 100kV acceleration voltage EB writer process, we have achieved down to 18nm resolution, and have established a mask making process to meet the requirements of the pioneers. Usually such masks needed just a small field (several hundred microns square or so). Now, UV NIL exploration seems to have reached the step of feasibility study for mass production. Here, instead of a small field, a full chip field mask is required, though the resolution demand is not as tough as for the extremely advanced usage. The 100kV EB writers are adopting spot beams to generate the pattern and have a fatally low throughput if we need full chip writing. In this work, we focused on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50kV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we could achieve resolution down to 32nm. Our initial results of 32nm class NIL masks with full chip field size will be shown and resolution improvement plan to further technology nodes will be discussed.

As semiconductor features shrink in size and pitch, the image placement error at photomask has been interested as an important factor to be reduced. Especially, by the development of double exposure technique (DET) or double patterning technique (DPT) for sub-45 nm node the image placement error is required to be controlled tightly. Following ITRS roadmap, when DET or DPT is used the registration for sub-45 nm node is required to be less than 4 nm but this specification still corresponds to the challengeable goal. Among various sources of image placement errors, here, we focus on the error occurring at patterning process of photomask and discuss its effect on the photomask overlay. We name the image placement error occurred at patterning process due to e-beam charging effect, absorber etching effect, and so on as the pattern loading effect. We quantify the amount of pattern loading effect on registration error, analyze it with the help of simulation and experiment, and discuss the character of each error and correction method.

This paper presents an experimental study of resist charging of mask blanks written with a variable shaped electron beam mask writer. Experiments were performed at a current density of 40 A/cm² on mask blanks with a chemically amplified resist. Test patterns were written to examine the magnitude of the pattern shift due to resist charging and the distance within which the pattern shift is significant. To reduce the pattern shift due to resist charging, furthermore, similar test patterns were written with a two-pass scanning in which both horizontal and vertical scanning directions are different between the two passes. With this writing method, the pattern shift was successfully reduced to about half.

Tightening requirements on resolution, CD uniformity and positional accuracy push the development of improved photomask blanks. One such blank for 45nm node attenuated phase shift masks (att-PSM) provides a thinner chrome film, TF11, with a higher etch rate compared to previous generation NTAR5 att-PSM blanks from the same supplier. FEP-171, a positive chemically amplified resist, is commonly used in mask manufacturing for both e-beam and DUV laser pattern generators. TF11 chrome allows the FEP-171 resist thickness to be decreased at least down to 2000 Å while maintaining sufficient etch resistance, thereby improving photomask CD performance. The lower stress level in TF11 chrome films also reduces the image placement error induced by the material. In this study, TF11 chrome and FEP-171 resist are evaluated with exposures on a 248 nm DUV laser pattern generator, the Sigma7500. Patterning is first characterized for resist thicknesses of 2000 Å to 2600 Å in steps of 100 Å, assessing the minimum feature resolution, CD linearity, isolated-dense CD bias and dose sensitivity. Swing curve analysis shows a minimum near 2200 Å and a maximum near 2500 Å, corresponding closely to the reflectivity measurements provided by the blank supplier. The best overall patterning performance is obtained when operating near the swing maximum. The patterning performance is then studied in more detail with a resist thickness of 2550 Å that corresponds to the reflectivity maximum. This is compared to the results with 2000 Å resist, a standard thickness for e-beam exposures on TF11. The lithographic performance on NTAR5 att-PSM blanks with 3200 Å resist is also included for reference. This evaluation indicates that TF11 blanks with 2550 Å resist provide the best overall mask patterning performance obtained with the Sigma7500, showing a global CD uniformity below 4 nm (3s) and minimum feature resolution below 100 nm.

As technology advances with feature size shrinking for the state-of-the-art integrated circuit (IC) fabrication, the degree of reduction in critical dimension (CD) features on a photomask shrinks at a faster pace, thanks to the ever aggressive optical proximity correction (OPC) design. In addition to stringent CD requirement, defect control has also become one of the most difficult challenges for advanced photomask manufacturing as a result of reduction in printable defect size. Therefore, keeping a photomask etching chamber at an optimal condition becomes very critical for controlling in both defectivity and CD fidelity. In the present study, analyses on optical emission spectrum (OES) collected in an Applied Materials' Tetra^TM chrome etch module have been performed to understand (1) the impact of Cr etching on the chamber condition, and (2) the effectiveness of in-situ chamber dry clean for chamber condition control and potential particle reduction. Results showed that, with the right selection of chamber materials (to be compatible with process chemistry and etching condition), the main impact of Cr etching on chamber condition and particle performance is from resist etch-by-products. Various plasma dry clean chemistries have been explored to address the effectiveness for the removal of such etch-by-products. As a result, an in-situ chamber clean (ICC) procedure is developed and has been validated to be production-worthy for desired particle control and chamber stability control.

As the industry approaches to 45nm and below lithography, resolution and pattern collapse of SRAF (Sub Resolution Assistant Feature) on photoresist is becoming critical issues on photomask industry. The collapse of photoresist pattern has been become a serious problem in manufacturing of fine patterns in wafer and mask industries. The presumed causes of the resist pattern collapse are capillary forces acting on the patterns and adhesion property of the patterns. The use of thinner resist thickness has been known as one of the most effective method among reported literatures. However, etching resistance of present resist is still bad. Therefore it is difficult to reduce the photoresist thickness, though the pattern size is very small. In this paper, the available limits of resist thickness for FEP171 were calculated for several kinds of common absorber layers as considering current dry etch capability. We focused on pattern design and collapse window for SRAF. FEP171 resist performance especially for resolution and collapse window were evaluated for both 2000Å and 3000Å thickness with line, space, and length focused on sub 100nm features. Radial position effect and drying conditions were studied herein.

We have proposed and modified a model of drying process of polymer solution coated on a flat substrate for flat polymer film fabrication. And for example numerical simulation of the model reproduces a typical thickness profile of the polymer film formed after drying. Then we have clarified dependence of distribution of polymer molecules on a flat substrate on a various parameters based on analysis of numerical simulations. Then we drove nonlinear equations of drying process from the dynamical model and the fruits were reported. The subject of above studies was limited to solution having one kind of solute though the model could essentially deal with solution having some kinds of solutes. But nowadays discussion of drying process of a solution having some kinds of solutes is needed because drying process of solution having some kinds of solutes appears in many industrial scenes. Polymer blend solution is one instance. And typical resist consists of a few kinds of polymers. Then we introduced a dynamical model of drying process of polymer blend solution coated on a flat substrate and results of numerical simulations of the dynamical model. But above model was the simplest one. In this study, we modify above dynamical model of drying process of polymer blend solution adding effects that some parameters change with time as functions of some variables to it. Then we consider essence of drying process of polymer blend solution through comparison between results of numerical simulations of the modified model and those of the former model.

Haze is a kind of contamination on the surface of mask which observed in the wafer production clean room only on reticles exposed with 193nm or 248nm wavelength process. Analyses have been provided an approach with enhance reticle purging efficiency method for investigating the required purging flow of clean, dry gas to prevent the ingestion of external contaminants into the reticle. In this study, we investigate the purging parameters theoretically by using natural convection with the purpose of avoiding rupturing the pellicle and expediting the overall purging process as shown in fig.1. Accordingly, a parametric analysis of important geometric variables including the size and number of purging holes is performed. Our study then process to identify the optimized parameters (number of holes, position of holes, purging flow rate) by using computational fluid dynamic (CFD) simulation. As indicated by our results, a parametric analysis investigating the effect of the pellicle variables shows that the purging time were sensitive to the number of purging or vent holes. As shown in fig.2 and fig.3, the total purging time can be reduced by increasing the number of purging or vent holes from 2 to 4. An increase in the number of purging holes from 2 to 4 help shorten the purging time by 20 to 40seconds. So the production throughput can be expected to rise while the consumption of gas can be reduced.

A key feature of a photomask is the transmission (Tr) property of its many surfaces. Typical advanced 6" masks have 4 surfaces: back side Quartz (Qz), Front side pattern, inside pellicle and outside pellicle. In addition to the surfaces themselves the bulk of the transparent materials- fused silica which is the material out of which the blank Qz is made and fluoropolymer out of which the pellicle is made, have specific optical Tr properties which contribute to the total Tr properties of the mask. Also surface coating materials like Cr, MoSi and Anti Reflective (AR) coatings have their specific Tr contributions. Figure 1 (see paper) shows a schematic drawing with all the different contributors to Tr loss in a photomask exposure system. Overall the wafer printed pattern fidelity to the design depends both on the physical size of the etched lines and spaces and on the Tr properties of the spaces and of the coating material in the lines. Factors which may contribute to transmission deviations may be: 1. Virgin Qz raw material non homogeneity. 2. Contamination by haze growth on any of the surfaces (Qz, absorber, pellicle). 3. Contamination by metal and oxide ions absorbed in the Qz and adsorbed on the Qz surface during mask manufacturing. 4. Photochemical degradation of the pellicle and fused silica substrates. 5. Degradation of absorber thickness, particularly of MoSi, due to clean processes. 6. Other factors. Accumulated contributions of all those factors can give rise to several percents of transmission variation. Every percent of exposure dose change may result in 1-2 nm CD change on wafer depending on exposure and process conditions. All the above raise the need for an advanced transmission measurement system that will be able to measure transmission at the exposure wavelength with sensitivities better than 0.1%, preferably better than 0.01% (100 ppm). Such systems are not currently available.

ArF lithography sometimes generates the haze defects on the photomask substrate, resulting in serious yield deterioration in ULSI production. In order to solve this problem, experimental and theoretical studies have been carried out on the generated haze defects. In characterizing the haze defects, the composition and chemical structure of the haze defects were analyzed by focusing on 1.0 x 0.3μm sizes defects using Raman, ToF-SIMS and AES spectroscopy with their highest spatial and mass resolution level. To confirm the experimental analyses, theoretical ab initio molecular orbital calculations were carried out on the model compounds of the generated haze defects. These experimental and theoretical studies indicate that the haze defects on quartz surface consist of (NH₄)₂SO₄ and that those on half-tone (HT) film surface, on the other hand, consist of (MoO₃)_x(SO₄)_y(NH₄)_z complex including Mo from HT film material. In the latter case, NH₄ ion was observed only in surface region of the haze defects. Based on these results, we have proposed a novel model of haze generation mechanism on quartz and HT film surfaces of photomask substrate.

Haze formation on reticle continues to be a significant source of concern for the photolithography. Possible sources and causes continue to be investigated. This paper provides a haze source evaluation result under the sub-pellicle defect on the mask. It is well known that there are several sources to produce the haze. One is inorganic molecules such as SOx, NH3, H2O and CO2. The haze formation of inorganic sources is promoted for growing defect size by the exposure energy in time. The other is organics that are prevalent Fab and storage environment. In this paper, we deal with the haze that is immediately generating with a low energy exposure. Especially, this study treats the haze source during the mask packaging method.

A lot of research has been carried on sulfate free cleaning process to minimize haze generating residual ions on mask surface. However sulfate free cleaned mask has been suffered from short life time of haze generation than we expected, because pellicle outgassing combines with ammonium residuals and formed haze near pellicle frame area and decrease yield. Therefore physical and PKL developed chemical surface modification treatment was studied and evaluated in term of near pellicle haze threshold energy, surface energy of mask substrate components (Qz/MoSi/Cr), AFM and AES depth profile. Dehydration bake treatment (physical surface modification treatment) and PKL developed chemical treatment increased near pellicle haze threshold energy by 2.5 and 4 times, respectively. Surface modification treatments didn't show negative effect on phase angle and transmittance losses of ArF EAPSM mask. The effect of illumination sources on surface modification treatment was also studied.

Progressive and haze defects continue to be the primary cause of mask degradation and mask re-clean due mainly to intensified density of photon energy involved with ArF exposure. To monitor and prevent haze in production, the methodology of direct reticle inspection has been widely implemented in wafer fabs to provide early warning of haze defects before they reach a critical level. With the continuous shrinkage of IC design rules for scaling devices, reticle inspection systems are increasingly challenged by aggressive OPC and high sensitivity requirements to detect printable defects. In this paper, two new reticle inspection technologies: STARlight2+^TM (SL2+) and Thin-line De-sense (TLD) on Die-to-Die (D2D) mode have been studied and evaluated on ArF production test reticles. The haze defect capture rate, defect residue modulation, and rendering on SL2+ mode have been compared with STARlight2 (SL2); the false defect count and usable sensitivity for D2D with TLD have been compared with D2D mode without TLD. The results of the two new technologies revealed significant improvement on sensitivity, inspectability.

In this study, A phenomenon of high peroxynitrite generated in purge gas in purge head outlet of RSP SMIF-POD Charger was found. A superior purification CDA("CDA" is abbreviated from Clean Dry Air) continuous purge system has been used in 193nm ArF reticle chemical free preservation process for mask Haze control. Ion Chromatography(IC) and Gas Chromatography Mass Spectrometry(thermal desorber GC-MS) methods are used to analyze and verify inorganic ion and volatility organic compound cleanliness of purge gas, respectively. After IC analysis, high nitrate ion concentration was detected in UPW("UPW" is abbreviated from Ultra-Purification Water). As a result of this study, It is confident of presuming that high peroxynitrite contamination in purge gas in purge head outlet was caused by the blow type in-line gas ionizer, high potential(approximate 2KV) needle discharge influence on the inside of purge piping of Charger. After bypass in-line gas ionizer apparatus, the IC analysis result has a tendency towards a diminution in peroxynitrite that nitrate ion was not detected in UPW at all. At the same operation condition, if purge gas replace by superior purification AN₂(A Class Nitrogen) and the inference conjectured that high ammonium ion response in UPW would take place. According to our study, superior purification CDA passed through the emitter tip of blow type in-line gas ionizers and under high potential needle discharge influence, high peroxynitrite concentration was generated in purge gas in purge head outlet of Charger. Due to the generation of peroxynitrite ion contamination in purge gas, it was not suitable to apply in the prevention of ESD damage of mask pattern in superior purification CDA(Clean Dry Air) continuous purge system. In this study, we also unexpectedly find that the blow type in-line gas ionizer with thermoplastic conductive tube resulted in purge gas a large number of volatility organic compounds(VOCs) contamination. VOC outgassing was generated from the inner walls of conductive tube which the most neighbor on the emitter tip, and heated by the power dissipation of needle discharge influence of corona ionizers.

The defects and contaminants on a photo mask can seriously impact the yield of manufacturing devices in semiconductor and flat panel display fabrication. Actually, as the device size and line width shrink in ultra large scale integrated (ULSI) circuit technology, even tiny amount of haze defects on the photo mask may cause device failure. Especially, in ArF lithography era, haze problem which is caused by deep ultra violet (DUV) laser beam exposure of have more serious effects to the quality and productivity of photo mask than in former lithography generation using a KrF excimer laser. Because the photon energy of ArF excimer laser is much higher than that of KrF excimer laser, ArF excimer laser can more easily accelerate the photo-chemical reactions generating a haze defect on the photo mask between laser exposure beam and thin metallic film on the photo mask. In general, photochemical effects can occur whenever the energy of a single photon exceeds the dissociation energy for a component of the material. For example, the photon energy of the ArF excimer laser which has 193 nm wavelengths is approximately 6.4 eV and this photon energy can break the chemical single bonds of pellicle film of photo mask. It is widely known that the formation of haze defect depends on laser wavelength, accumulated energy density onto the photo mask, a kind and concentration of surrounding gases, humidity and cleaning method. Although many researchers have reported on efforts to find out the alternative improving the photo mask quality, reducing residual contamination level and revealing the exact cause of the haze generation on the photo mask, however performance improvement of such efforts has been difficult to measure. Typically test for haze generation and inspection by using production lithography system takes much time as well as this process is too expensive and risky. Accordingly Kornic Systems has developed and implemented laser induced haze acceleration system. This system can provide the solution to reduce of haze generation time and to reveal which factor make the haze onto the photo mask during lithography process. In this paper, we also introduce a practical ArF excimer laser system for accelerating the haze formation and simultaneously revealing the detrimental effects of haze generation on the photo mask in lithography process. The haze acceleration system which can control the accumulated energy density on the photo mask level, humidity, temperature and concentration of gases such as NH₃ and SO₂ in process chamber, could be an effective tool for providing technical and economical benefits to the photo mask and device manufacturers.

This paper summarizes the dramatic results achieved through the use of novel reticle haze prevention techniques and new equipment which have enabled these results. Near continuous XCDA® purge of reticle pods coupled with integrated pod purifiers resulted in the elimination of reticle haze defects for the usable production life of reticles.

Since the haze generation causes unexpected wafer yield losses, it has been a serious issue on wafer lithography as illumination wavelengths become shorter with 248nm and 193nm. Several papers regarding to cleaning and its effect on haze generation have been published. A mask is cleaned periodically to prevent from the haze generation. These periodic or repetitive cleanings causes unacceptable phase and transmittance variation. Therefore, the number of cleaning cycles has been limited to meet limitation of phase and transmittance. In this paper, relaxation for pass or fail criteria was studied based on phase and transmittance margin, as one of the solutions of cleaning limitation. Optimum cleaning cycles were determined by using AIMS (Aerial Image Measurement system) simulation methods. Various parameters such as phase and transmittance variation, depth profile, intensity, CD (Critical Dimension) with line and space and contact pattern of pre and post cleaned ArF PSM were measured whenever a mask was cleaned repeatedly. Moreover, a mask quality was validated based on the measured parameters, considering limitation of phase and transmittance and lithography margin. The cleaning and validation were repeated several times until intensity and CD were out of limitation. Based on these studies, a correlation model between the numbers of cleaning cycles and measured parameters from AIMS simulation were developed. The newly developed correlation model was used for an estimating parameter for the optimum number of cleaning cycles to be performed.

The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask Data Preparation (MDP), mask writing, and mask inspection in 2006, with the support from the New Energy and Industrial Technology Development Organization (NEDO). We report on the development of a new low cost mask inspection technology with short Turn Around Time (TAT), as a result of adopting a method of selecting defect detection sensitivity level for every local area, defined by such factors as defect judgment algorithm and defect judgment threshold, as one of the pseudo-defect-reduction technique necessary to shorten mask inspection TAT. Those factors are extracted from the database of Mask Data Rank (MDR) and converted on the basis of pattern prioritization determined at device design stage, using parallel computation.

Sub-resolution assist features (SRAF) are a common optical proximity correction method to preserve main feature patterns upon imaging into a photoresist during the lithographic process. The presence of SRAF can often reduce the inspectability and usable sensitivity in high resolution inspections of these reticles. KLA-Tencor has developed an improved Thin-Line De-sense capability for Die-to-Database inspections (dbTLD) on the TeraScanHR that addresses this challenge. The dbTLD capability provides sensitivity control focused on SRAF, thus improving inspectability without compromising high sensitivity to main features. The key feature of the improved dbTLD capability is that it provides greater flexibility to effectively de-sense non-critical defects on SRAF in variable sizes oriented at any angle and in variety of shapes including challenging L- and U-shaped structures. This paper will demonstrate the value of dbTLD on improving inspectability where aggressive SRAF structures exist. The selective application of sensitivity on main features and assist features is the key to improvement in database inspections without impacting throughput.

By refining the entire optical system in our LM7500 reticle inspection system, we have successfully improved the image quality and inspection speed. The LM7500 system uses a beam scanning method in which the inspection pixel size is switched by changing the magnification ratio of the telescope in the section subsequent to the scanner's optical system. The telescope magnification ratio is designed to meet the requirements of the light spot diameter and beam scanning width on a reticle, and specifies the scanning speed. We have realized a smaller light spot diameter by improving the design of the section prior to the optical system, including the AOD (acousto-optic deflector), which is the starting point of the scanner's optics. This has led to faster scanning. We have also succeeded in minimizing the adjustment error by optimizing the magnification ratio of the telescope, thus increasing the adjustment margin of the incident light beam entering the section subsequent to the scanner's optical system. This means that the difference in the X and Y directions of an image can be suppressed to a remarkable extent for a beam scanning system. Moreover, because the LM7500 scans both transmitted and reflected light simultaneously, pattern inspections, particle inspections and even scribe-tri-tone inspections can be carried out at the same time. We have also succeeded in increasing the inspection speed by 30% through optical system optimization.

Semiconductor device manufacturers have made technological advances in fabricating devices at 65nm and 45nm nodes. Technology is advancing towards 32nm node devices. Reticles at these device nodes are designed with tight critical dimension (CD) specifications and sub-resolution features. Inspection tools capable of detecting CD defects on the order of 20 nm are required to accommodate these device nodes. To meet this challenge, KLA-Tencor has developed a new "CD Detector" capability on the TeraScanHR reticle inspection tool that efficiently detects two-sided CD defects on reticles at the 45nm node and beyond. The CD Detector is available in both Die-to-Die (DD) and Die-to-Database (DB) inspection modes. This paper presents results of a CD Detector Beta evaluation on variety of advanced reticles in a production setting at Advanced Mask Technology Center (AMTC) in Germany. Inspection results will demonstrate improved sensitivity to two-sided CD defects and good inspectability, at inspection times similar to a standard HiRes inspection. Discussion will focus on enabling the highest sensitivity to CD defects at 72nm pixel inspections, which is suitable for advanced research and development studies, as well as improved sensitivity at 90nm pixel inspections for higher productivity.

This paper discusses the most efficient mask re-qualification inspection mode for 7Xnm half pitch design node production memory reticles in advanced memory wafer fab. By comparing overall performance including inspectability, sensitivity, and throughput for 8 different inspection modes, P150 Pixel Die-to-Die Reflected Light (P150 DDR) was identified to be the most desirable inspection mode for the specific use case where only one inspection mode is available. The evaluation was executed on the most critical layers - active, gate and contact layer. P150 DDR demonstrates the capability of providing early warning for the crystal growth type defects on both quartz and MoSi surfaces. It also showed good sensitivity for capturing small contamination defects in the dense Line/Space or Contact/Hole pattern areas. With a fast inspection scan speed and easy to use set up, TeraScanHR P150 DDR offers the best cost of ownership among all inspection modes. To gain higher sensitivity for smaller design nodes, TeraScanHR P150 DDR can be easily extended to smaller inspection pixels with minimum impact on productivity.

As the industry embarks on sub 50nm half pitch design nodes, higher resolution and advanced inspection algorithm are needed to resolve shrinking features and find critical yield limited defects. In this paper, we evaluate the detection capability of STARlight2+ 72nm pixel on DRAM masks. The mask sets targeted for this evaluation were focused on critical layers. Although memory mask sets are dominated by multi-die layout, single die layout masks were also inspected because of their significance during research and development. Inspection results demonstrated the performance of STARlight2+ based on its sensitivity to contamination defects, inspectability, first time success rate and throughput. STARlight2+ has single die inspection capability, which is also needed in order to inspect scribe-lines and frame areas. The primary defects of interest are photo induced defects or contamination, causing mask degradation. Contamination continues to be the primary reason for mask returns at 193nm exposure across the industry. The objective of this paper is to demonstrate STARlight2+ 72nm capability to support memory wafer fab mask qualification requirements.

KLA-Tencor has introduced the new TeraFab reticle inspection systems for wafer fabs to address market demand for systems with high productivity and high sensitivity. The core inspection technology of the TeraFab systems is STARlight2+ (SL2+). STARlight is the industry accepted method for mask inspection in wafer fabs for reticle requalification. STARlight uses transmitted and reflected light images of a reticle to generate reference images of the reticle that are used to detect defects that have been added to the reticle while the reticle has was exposed or in storage. The improvements in reference generation in SL2+ relative to previous generations of STARlight is made possible, in part, by increases in computation resources for TeraFab systems. Improved modeling capability of SL2+ leads to increased usable sensitivity in dense geometries. Improved modeling capability also allows the user to optimize inspection cost of ownership (COO) if the maximum sensitivity of the TeraFab system is not required for a specific application. This paper describes an investigation of sensitivity versus throughput using SL2+ on multi-die production reticles with haze at the 65nm technology node. SL2+ data is also provided showing the feasibility of using larger inspection pixels (pixel migration) while retaining good sensitivity at the 45nm technology node.

Two aspects are critical when a new reticle type is introduced in a wafer fab: printability and reticle inspection. In this study, we inspected 4 PSM reticles at the 45nm technology node, at P90, on the 5xx TeraScanHR platform. We successfully inspected SL2+ reticles of the PSM type at P90. We forecast that in a high volume 32nm node production environment, P72 SL2+ will address the inspectability challenges associated with PSM masks. This is based on strict requirements for sensitivity on contamination defects, inspectability, and cost of ownership, as when UMC addressed their wafer printability issues.

Aerial image mask inspection tools are effective in qualifying masks based upon printability assessments using scanner-based actinic (193nm) illumination conditions. Aerial imaging inspection application is relevant for masks that are at final process steps or resemble a completed mask. However, maskshops perform inspections at additional, intermediary, mask manufacturing stages, as well as on masks designed for 248nm scanners. In both of these cases, aerial image inspection using scanner-based actinic (193nm) illumination conditions was not considered relevant. This paper demonstrates that aerial imaging inspection tools can be easily configured to perform inspections using various non-aerial illumination modes, owing to their inherently flexible optical design. Aerial image mask inspection tools, running in these optical modes, are effective for detecting defects at various stages of the mask manufacturing process and even for inspecting 248nm masks. Accordingly, MP Mask has adopted the first and second generation aerial imaging mask inspection tools of Applied Materials for all of the following applications: Advanced front end reticle qualification, low and high transmission PSM masks, and immersion and non-immersion plates from 65nm to 45nm technology nodes for DRAM and flash products. A simple cost of ownership comparison of aerial image mask inspection tools with traditional inspection methodology indicates that these inspection tools are well-qualified for use on a wide spectrum of masks and process points. This paper presents qualification procedures and results obtained with this new tool based on a set of masks representing several exposure wavelengths, mask types, technology nodes, product families, and inspection points.

Technical demand for the photomask is becoming severer along with super-miniaturization of the semiconductor patterns as shown in the ITRS roadmap. Defect inspection is especially becoming more challenging and difficult as the photomask design rules continue to shrink toward hp65-45nm and below. One of the factors for such difficulties is aggressive OPC (Optical Proximity Correction), which makes defect inspection extremely difficult. In lithography, ArF immersion lithography will be predominantly used as one of the powerful candidates for the technology for hp65-45nm. Therefore, we have to assure zero printable defects assuming the use of ArF immersion lithography. Recently, there is another issue of increase in mask production cost, causing QCD balance to start to collapse. To cope with this new problem, tool operation is being considered for inspections ranging from accelerating inspection in R&D phase to reasonable inspection in production phase. In this paper, inspection concept for operation of inspection tools in R&D and production phases is discussed, with special focus on the aerial image based inspection.

This paper studies the application of resist models to AIMS^TM images. Measured AIMS^TM data were coupled with resist simulations of the Fraunhofer IISB research and development lithography simulator Dr.LiTHO and with a compact resist model developed by Carl Zeiss SMS. Through-focus image data of the AIMS^TM are transformed into a bulk image--the intensity distribution within the resist. This bulk image is used to compute the concentration of photo-acid after exposure and the following resist processing. In the result a resist profile is obtained, which can be used to extract the printed wafer linewidth and other data. Additionally, a compact resist model developed by Carl Zeiss SMS was directly applied to the AIMS^TM data. The described procedures are used to determine dose latitudes for lines and spaces with different pitches. The obtained data are compared to actual wafer prints for a 1.2 NA system.

Most of photomask issues such as pattern collapse, HAZE, and cleaning damage relate to behavior of mask surfaces. Therefore it is coming to be important to control surface energy in photomask processes. Especially adhesion analysis in micro region is strongly desired to optimize material and process designs in photomask fabrication. Quantitative measurements of adhesive forces of resists on photomask blanks were realized with scanning probe microscopy (SPM) techniques. Then surface energy on photomask blanks was able to be controlled by modification with some silanization reagents. In addition, adhesive forces of resists on surfaces modified with some silanes were able to be also controlled. The SPM method is proved to be effective for measuring adhesive energy of micro patterns on photomask blanks.

Hotspot management in low k1 lithography is essential for the achievement of high yield in the manufacture of devices. We have developed a mask quality assurance system with hotspot management based on lithography simulation with SEM image edge extraction of actual mask patterns. However, there are issues concerning this hotspot management from the viewpoint of hotspot sampling and turnaround time. To solve these problems, we modify the mask quality assurance system by introducing dynamic adaptive sampling in which hotspots are sampled depending on actual mask fabrication quality. As a result, producer's and consumer's risks are efficiently reduced, and TAT for mask inspection is also reduced.

Since mask design rule is smaller and smaller, Defects become one of the issues dropping the mask yield. Furthermore controlled defect size become smaller while masks are manufactured. According to ITRS roadmap on 2007, controlled defect size is 46nm in 57nm node and 36nm in 45nm node on a mask. However the machine development is delayed in contrast with the speed of the photolithography development. Generally mask manufacturing process is divided into 3 parts. First part is patterning on a mask and second part is inspecting the pattern and repairing the defect on the mask. At that time, inspection tools of transmitted light type are normally used and are the most trustful as progressive type in the developed inspection tools until now. Final part is shipping the mask after the qualifying the issue points and weak points. Issue points on a mask are qualified by using the AIMS (Aerial image measurement system). But this system is including the inherent error possibility, which is AIMS measures the issue points based on the inspection results. It means defects printed on a wafer are over the specific size detected by inspection tools and the inspection tool detects the almost defects. Even though there are no tools to detect the 46nm and 36nm defects suggested by ITRS roadmap, this assumption is applied to manufacturing the 57nm and 45nm device. So we make the programmed defect mask consisted with various defect type such as spot, clear extension, dark extension and CD variation on L/S(line and space), C/H(contact hole) and Active pattern in 55nm and 45nm node. And the programmed defect mask was inspected by using the inspection tool of transmitted light type and was measured by using AIMS 45-193i. Then the marginal defects were compared between the inspection tool and AIMS. Accordingly we could verify whether defect size is proper or not, which was suggested to be controlled on a mask by ITRS roadmap. Also this result could suggest appropriate inspection tools for next generation device among the inspection tools of transmitted light type, reflected light type and aerial image type.

Recently more and more mask designs for critical layers involve strong OPC which increases the complexity for standard CD SEM mask measurements and conclusive interpretation of results. For wafer printing the wafer level CD is the crucial measure if the mask can be successfully used in production. Recent developments in the AIMS^TM software have enabled the user to use the tool for wafer level CD metrology under scanner conditions. The advantage of this methodology is that AIMS^TM does see the CD with scanner eyes. All lithographic relevant effects like OPC imaging which can not be measured by other tools like mask CD SEM will be captured optically by the AIMS^TM principle. Therefore, measuring the CD uniformity of the mask by using AIMS^TM will lead to added value in mask metrology. With decreasing feature sizes the requirements for CD metrology do increase. In this feasibility study a new prototype algorithm for measuring the lithographically relevant AIMS^TM CD with sub pixel accuracy has been tested. It will be demonstrated that by using this algorithm line edge and line width roughness can be measured accurately by an AIMS^TM image. Furthermore, CD repeatability and tool matching results will be shown.

The aerial images of modern photomasks are highly susceptible to CD errors, owing to the high MEEF values characteristic of the low-k₁ regime. The requirement for tight wafer CD control thus places stringent constraints on mask errors. Nevertheless, multiple physical variations of the mask parameters can lead to the same aerial CD error. We introduce IntenCD^TM, a novel, fast and precise CD variation mapping application running on Applied Materials' aerial image inspection tools. The IntenCD application generates a high-precision map of the CD variation, and allows tighter control of mask manufacturing process and qualification, without loss of precision compared to slow, discrete measurement tools such as CD SEM, but with a higher throughput, while offering complete mask coverage and higher measurement definition. We study and provide the theoretical basis to the IntenCD application. We analyze image formation of dense, repetitive mask patterns under aerial imaging conditions and show, analytically and numerically (through a series of simulations), that for a small perturbation of the nominal physical mask parameters, the relative variation of the average aerial intensity scales linearly with the relative aerial CD error. This linear relation, unique to aerial imaging mask inspection, is independent of the physical source of the variation and of the mask design pitch. Our results imply that a robust aerial intensity measurement can detect sub-nm aerial CD variations. We discuss some practical problems that have to be addressed to obtain this challenging resolution, and describe in some detail the technological solutions.

The development of the 45-nm node manufacturing process at leading edge mask shops is nearly finished. In order to reach the required registration measurement performance with a precision to tolerance value of P/T=0.25, the measurement error may not exceed 1.2 nm according to ITRS roadmap. This requires the latest generation of registration measurement tools. In addition, the demand for measuring very small features increases - for standard pattern placement measurements, as well as special engineering tasks, e.g., the position measurement of single contact holes. In this work, the error of pattern placement measurement on an LMS IPRO4 is determined using an analysis of variance methodology (ANOVA). In addition we analyze the capability as a function of the critical dimension (CD) of the registration feature. The results are compared to the previous tool generation.

The extension of optical lithography to the 45nm node and beyond goes along with increased mask complexity and tightening of specifications. The proper use of PSM becomes more and more important and the phase shift needs to be quantified exactly in order to achieve accurate CD printing results during wafer processing. The methods currently available run into limitations because they are not able to consider diffraction limitations caused by scanner NA and mask pitch, as well as 3D mask effects. In the transition to the 45nm node and beyond, these effects play an important role and need to be considered. Zeiss' new phase metrology system Phame^® captures diffraction limitations, rigorous effects (i.e., a failure of the Kirchhoff approximation), and polarization effects. The new phase metrology system measures the phase shift in any in-die feature of the active mask area for on- and off-axis applications with high spatial resolution. This paper is focused on through pitch and through duty cycle measurements on an alternating PSM. Phame^® measurements will be compared to AFM measurements. Additionally rigorous 3D simulations have been performed for different CD, varying pitch and varying duty cycle using coherent illumination with polarization. The simulation results will be compared to Phame^® measurement results.

Photomask processing during mask manufacturing can influence key-parameters of CD-SEM measurement such as measurement accuracy and repeatability. In particular, resist strip and mask clean processes seriously affect the surface properties of CoG-reticles and therefore increase the chrome-CD-measurement uncertainty. In extreme cases, the change of chemo-physical properties of the top Chromium oxide layer can have dramatically impact on the electrons emitted by the surface, utilized by the imaging process of CD SEMs. This change leads to a decreased secondary electron yield, and even more dramatic, induces charging near isolated chromium structures. Although the surface changes appear to be reversible with typical charge decay times in the order of days, the associated charging effect is in severe conflict to the common demand for low cycle times and high measurement accuracy experiments for the CD-measurement processes. In this work, we present fundamental experiments on Chromium oxide layers taking into account the effect of hydrophilicity on the optical as well as on the electrical behavior. We observe that the dependence of secondary electron yield on primary electron energy turns out to be the main issue effecting charging of electrically floating chromium structures. This charging effect thus can be understood in terms of shifting the so-called "iso-electrical point", ultimately resulting in contrast reversion. Furthermore, our data are compared to a simple model respecting electron induced charging during mask surface activation. Our model is supported by numerical calculations of the effective surface potentials near isolated chromium structures. Moreover, the model provides ways to find novel routes for improved surface preparation prior to CD-measurement that allow a good SEM imaging behavior.

Rigorous electromagnetic field simulations are an essential part for scatterometry and mask pattern design. Today mainly periodic structures are considered in simulations. Non-periodic structures are typically modeled by large, artificially periodified computational domains. For systems with a large radius of influence this leads to very large computational domains to keep the error sufficiently small. In this paper we review recent advances in the rigorous simulation of isolated structures embedded into a surrounding media. We especially address the situation of a layered surrounding media (mask or wafer) with additional infinite inhomogeneities such as resist lines. Further we detail how to extract the far field information needed for the aerial image computation in the non-periodic setting.

The continuous progress in semiconductor technology has caused mask feature sizes shrinking to 120 nm for the 45nm node and down to 85 nm for the 32nm node. Along with the smaller features, mask image placement accuracy has to improve to 3.4 nm by 2013. Applying double patterning in particular requires rigorous manufacturing control over level to level registration in order to achieve the specified yield and device speed. There is currently no registration tool that ensures image placement performance at the minimum feature size of current and future technology nodes. This work describes fundamental concepts and working principals of a new metrology tool currently under development at Carl Zeiss for measuring image placement and critical dimension in photomask manufacturing. The design of the instrument will be discussed with special emphasis on its optical components. Benefits and advantages using 193nm illumination as well as contrast simulations on different types of masks are presented.

Smaller feature sizes and aggressive Reticle Enhancement Techniques have led to greatly increased mask data file sizes, longer processing times, and shrinking error budgets. Improvements to Mask Data Preparation software can mitigate these trends. Processing time can be reduced by using algorithms which are compatible with scalable multi-core Distributed Processing. Increased pattern uniformity in the fractured output can reduce Critical Dimension variation on the finished mask plate. Procedures for estimating pattern uniformity and CD variation are described.

In order to go through the transition term from GDSII to OASIS successfully, the aid of the verification tools between OASIS and GDSII is necessary. In general, we have two methods of OASIS file verification. One is a hierarchical method that checks between GDSII and OASIS by each cell level. The other is a flat method that merges each pattern through its hierarchy into a flat level and compares the flattened geometry one by one. We did the experiments of comparison between two methods for OASIS to GDSII verification. The software tool called 'ogdiff' has been used for a hierarchical verification experiment. We used SmartMRC for the flat method experiment. In this paper, we show the experimental results of comparison and we also address the pros and cons of each method. Then we suggest which method is preferable for specific cases.

One of the ASET/MaskD2I target is the mask data prioritization and it effective uses for mask manufacturing issues. The MaskD2I and STARC have been working together to build efficient data flow based on the information transition from the design to the manufacturing level. By converting design level information called as "Design Intent" to the priority information of mask manufacturing data called as "Mask Data Rank (MDR)", MDP or manufacturing process based on the importance of reticle patterns is possible. Our main purpose is to build a novel data flow with the priority information of mask patterns extracted from the design intent. In this paper, we introduce the basic activities of the MaskD2I, and address the effectiveness of MDR information. Then we explain how to apply it to mask writing, inspection, MDP and MRC. We will show the new experimental results by extracted MDR from actual mask data provided by STARC.

As the feature size of LSI becomes smaller, the increase of mask manufacturing cost is becoming critical. Association of Super-Advanced Electronics Technologies (ASET) started a 4-year project aiming at the reduction of mask manufacturing cost and TAT by the optimization of MDP, mask writing, and mask inspection in 2006 under the sponsorship of New Energy and Industrial Technology Development Organization (NEDO). In the project, the optimization is being pursued from the viewpoints of "common data format", "pattern prioritization", "repeating patterns", and "parallel processing" in MDP, mask writing, and mask inspection. In the total optimization, "repeating patterns" are applied to the mask writing using character projection (CP) and efficient review in mask inspection. In this paper, we describe a new method to find repeating patterns from OPCed layout data after fracturing. We found that using the new method efficient extraction of repeating patterns even from OPCed layout data is possible and shot count of mask writing decreases greatly.

The design shrinking of semiconductor devices and the pattern complexity generated after OPC (optical proximity correction) have an impact on the two major cost consuming processes in mask manufacturing, EB (electron beam) writing and defect assurance. Mask-DFM (design for manufacturing) is a technique with various steps ranging from the design to the mask manufacturing to produce the mask friendly designs and to reduce the workload in the advanced mask production. We have previously reported on our system, called MiLE (Mask manufacturing Load Estimation), which quantifies the mask manufacturing workload by using the results of mask layout analyses. MiLE illustrates the benefits of mask-DFM efforts as numerical indexes and accelerates the DFM approaches. In this paper, we will show the accuracy of the workload estimation of the advanced devices by the comparison between the indexes and the process times in the actual mask manufacturing. The throughput of MiLE calculation of the production masks of a 65nm device was measured.

As the pattern feature sizes become smaller, photomask assurance by one-dimensional criteria using a CD-SEM is reaching its limits. For instance, minute steps generated by OPC (Optical Proximity Correction), especially under the influence of corner rounding, are hard to measure. Thus, photomask assurance by means of two-dimensional features has been studied. Conventionally, in simulations to predict the printed shape on the wafer, OPCed data pattern have been used. While the OPCed data pattern represents the ideal pattern fidelity, actual pattern on a real photomask is different from the ideal shape. In addition, the increase of MEEF (Mask Error Enhancement Factor), along with the fine-than-ever pattern feature size, emphasizes the difference between the simulation result and the actually printed result on the wafer. To realize the two-dimensional assurance, we have to think of a method to predict the wafer image accurately. This is also important when we have to verify and manage the lithographic hotspots. For this purpose, we have been studying a mask model, a technique to take into consideration the actual pattern fidelity on the photomask, by modeling mask patterns' linearity, proximity, corner-rounding, etc., for each mask making process. By applying the mask model to OPCed design pattern, mask pattern shapes were found to be accurately predicted before mask making. Furthermore, we studied hotspot verification flow using the mask model. By the application of the mask model on the data pattern for the optical simulation, we accurately predicted the shape printed on the wafer, and accurately verify hotspots. This is expected to lead to assurance of photomask using two-dimensional shape.

Double patterning has gained prominence as the most likely methodology to help keep Moore's law going towards 22nm 1/2 pitch lithography. However, most designs cannot be blindly shrunk to run using only two patterning layers and a variety of constraints must be imposed on designs to allow for correct decomposition. These constraints are more onerous for the contact layer than for line/space patterns because they more easily form odd cycles on the 2D plane, which cannot be broken using polygon cutting. As this can adversely limit packing density, especially in bit cells, a triple patterning decomposition capability could be attractive for the contact layer. Pattern decomposition for contacts can be likened to coloring a map where minimum spaces between contacts are replaced with borders. It is well known that 4 colors can color any map, but it is an NP-complete problem to compute the minimum number of colors needed to color any given map. This should place an upper limit on the scalability of any algorithm able to color large networks. A variety of test patterns that are known 3-colorable are needed to compare suitable algorithms. It has been proved that a set of aperiodic tiling known as "Penrose Tiles" is 3-colorable. This paper compares the scalability of different coloring algorithms using a variety of contact patterns based on Penrose Tiles.

A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this regard. In this work, we calculate the I_on and I_off impact of line-end taper shapes as well as line-end length. The proposed models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ΔI_on and ΔI_off. Finally, the electrical metric for line-end printing is defined as expected change in I_on or I_off under a given overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large variety of taper shapes to characterize electrical impact.

A thin membrane called a pellicle is commonly used to protect the mask from contamination. The thickness of the pellicle material is usually optimized at normal incident angle to minimize the thin film optics interference effect by cancellation of the reflected light from the top ambient/pellicle interface with the reflected light from the bottom pellicle/ambient interface. In previous lithography generations the maximum angle collected by the projection lens (NA) was low, hence the normal incidence approach was valid, and the transmission loss for the non-normal incident angles was minor and ignored. With modern hyper-NA imaging for 45nm and smaller nodes, this transmission attenuation becomes larger. The more stringent CD error budget of these technology nodes demands that this effect should not be ignored anymore. In this paper, we present a modeling framework that takes into consideration the high angle pellicle effects. Taking the pellicle's polarization state dependent transmission data, which can be measured or computed with a rigorous simulator, we first present the pellicle transmission property as Jones matrices on the pupil plane, and then incorporate pellicle modeling into the existing vector model for lithography imaging computation. Existing modeling software for modelbased OPC/RET tools is easily enhanced to include pellicle modeling. Using Synopsys' OPC/RET modeling software ProGen, we investigate the necessity of pellicle effect modeling for mask synthesis for 45 nm and smaller nodes. Numerical experiments are performed to study the impact of illumination polarization on the accuracy of lithography simulation and the quality of OPC results.

Metal layers have some drawbacks in building up model based OPC (MBOPC) because metal layers are mainly composed of 2 dimensional (2D) patterns which show modeling inaccuracy and the difficulty of fragment optimization compared with 1-dimensional patterns. As a result, metal layers have considerable hot spots such as pinch, bridge and insufficient contact overlap. The modeling inaccuracy of 2D patterns results from a few reasons like measurement noise, inaccurate optical simulation and empirical resist modeling etc. The fragment optimization operated by rule does not control automatically corner rounding problems induced by small jogs of 2D patterns. The design for manufacturability (DFM) is known to provide a solution to overcome these problems. One of engines operating the DFM is MBOPC, which is made by an empirical process model and offers the process variation counter map simulated by the MBOPC engine. However, the accuracy of the simulation is quite low because we cannot avoid over-corrected patterns generated inevitably with the empirical model. In order to detect and correct the hot spots caused by the design itself, that is, the inherent function of the DFM, it is necessary to provide the OPC engine of the physical model with the optimized illumination condition to rule out empirical effect. Physical model is more emphasized in case of process window simulation because of its accuracy in the edge boundary of process window. One of important function of DFM for the metal layers is to enhance the contact overlap margin which can be influenced by the lithography process such as line end shortening, corner rounding effect and miss-alignment. Etch process is also a significant parameter of contact overlap. Calibrated process model is very effective to detect the insufficient contact overlap with process window. In this paper, MBOPC of sub-45nm node metal layers is studied to provide the effective DFM engine. The DFM flow with renewed MBOPC engine will show the improved process window and large contact overlap margin and will also make it possible to search and correct just patterns capable of decreasing the process window by only layout defect itself.

Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict the entire lithography process correctly even using advanced optical and resist models. In order to compensate for the mask proximity effect within OPC a special model is required along with changes to the OPC flow. This article presents a method for producing such a model and OPC flow and shows the difference in results when they are used.

Increasing pattern density and the higher complexity of advanced OPC and RET technologies have lead to an explosion in mask data volume. This increased data volume leads to increased mask write times, inspection times, and costs. In the past, several techniques for reducing the mask shot count have been proposed, including OPC fragment alignment, jog alignment, jog smoothing, and design intent-aware layout fragmentation among others. This paper will explore the tradeoffs between mask shot count and simulated print quality for various shot count reduction strategies.

~30nm width isolated line is formed with over 300nm DOF by Single Exposure process of ArF immersion lithography. Super-Diffraction-Lithography ("SDL") technique, which utilizes fine dark line image formed between a pair of bright lines in attenuating non-phase-shifting field and which enables formation of very fine isolated line pattern with single exposure, is applied with ArF immersion lithography. By simulation study, superior performance of "SDL" is exhibited for ArF immersion lithography. From view point of mask fabrication, it is shown that requirement for mask technology is not so severe, such that photo mask for "SDL" in hyper NA ArF immersion era can be fabricated with current mask technology. By experiments with an optimum quadrupole illumination, ~30 nm width isolated line is successfully printed by single exposure process with over 300nm DOF by a mature 6% transmission EA-PSM. Moreover, device like pattern with ~35nm line width is well formed with enough large DOF to industrially fabricate devices. We believe this technique is one of the promising candidates for advanced logic at 32 nm node and beyond.

The tight process window of advanced lithography in the semiconductor industry is further challenged by the growing contribution of photo-mask related CD variations. In previous technology generations, global measurement and global correction were sufficient to compensate for critical dimension uniformity (CDU) variations deriving from various sources. However, in the low K₁ regime for 45nm nodes and below, cross-coupled effects such as Mask Error Enhancement Factor (MEEF) and mask CDU can easily consume the overall CD budget related to lithographic process steps (see table 3). ASML's DoseMapper was designed to correct system (e.g. scanner, track) and non-system (e.g. mask) related errors controlled by an Automated Process Control (APC) system. It was introduced as a method for correcting intra-field and inter-field variations, relying on feedback from printed wafer based metrology. Here we propose using AMAT's IntenCD^TM map for supplying dense CDU measurement results from the reticle as a feed-forward input to DoseMapper. The IntenCD^TM application characterizes CD uniformity of 'features of interest' across the mask in the form of a dense map with high accuracy and throughput. The case studies presented in this paper are the result of collaboration between AMAT and ASML to demonstrate the benefit of feeding IntenCD output into DoseMapper CD analyzer which translates the mask CD map into a scanner dose recipe. The integrated solution can be implemented in manufacturing factories to shorten turnaround time and improve the exposure process window. It can be used to compensate for CDU effects due to mask production as well as contributions due to life time deterioration.

Flow of fixing of hot spot induced by optical variation among exposure tools is discussed for quick ramp-up of high volume products. To achieve robust pattern formation for optical variation, following hot spot detection and fixing approaches are introduced: i) at the design stage, hot spot detection within the optical variation space and hot spot fixing by layout modification or OPC optimization, ii) in order to efficiently detect hot spots within the optical variation space, lithography simulation by combinations of optical parameters determined by the design of experiment (DoE), iii) at the manufacturing stage, hot spot fixing by adjustment of optical parameters using the multi-variable optimization to match OPE between the primary and secondary exposure tool.

The purpose of this work was to identify the specific effects of mask topography by analyzing in the Fourier domain. Our focus patterns extend from a simple contact hole (CH) with a fixed pitch and bias to ones that have a variety of different pitches and hole sizes. We also attempt to predict phases and amplitudes of diffraction on the pupil plane without a rigorous mask topography approximated model. Intensities of CH patterns are simulated using three mask models. We had determined that there are serious differences among the three mask models concerning the contrast of the intensity and the qualitative interpretation of the trend of contrast varies according to pitch and hole sizes. The mask topography effects can be classified into waveguide and shadowing effects simply by using the diffraction decomposition diagram. We clarify how much and when the mask topography influences imaging under hyper-NA lithography by the diagram. From 1D near-field phase distribution, it is clarified that phase distribution has also been decided by the MoSi width between holes so that waveguide effects are not only from hole but also from MoSi area. It has been determined that the influence of the real 3D structures of the mask under the hyper-NA condition cannot be disregarded. However, use of the rigorous EMF calculation costs much more and requires more time than using a non-EMF calculation. We have also clarified the mechanism of 3D mask effects based on the amplitude and the phase of the diffraction light in the Fourier-domain diagram and examined whether the 3D mask effects can be predicted by thin mask approximation (TMA) and found that once we have values of amplitude and phase of the 0th and the 1st diffraction in TMA, it will be possible to predict the values of the other pitch and the other hole size.

This paper reports on the mutual optimization of the mask geometry, mask absorber stack, and illumination settings for arrays of non-quadratic contact holes with different pitches. In contrast to previous work in this field, mask topography effects are fully taken into account. The proposed procedure is enabled by significant performance improvements implemented in the rigorous Waveguide EMF solver and by the application of global optimization techniques. In order to allow for a flexible and efficient interaction, all models and algorithms have been integrated into the Fraunhofer IISB development and research lithography simulation environment Dr.LiTHO. To demonstrate the flexibility of our optimization approaches, we have optimized the imaging of dense and semi-dense arrays of 65nm×90nm contact holes with a 1.35NA water immersion ArF scanner. The process performance is evaluated in terms of overlapping process windows of all relevant feature sizes.

It is well known that optical proximity effects are highly dependent upon the details of the illumination source. Tremendous effort is taken to match illumination source profiles between tools, as well as to appropriately represent the source intensity distribution in the models used for OPC and post-OPC verification. OPC software typically models the intensity profile in such a manner that empirical fitting of the CD data during model calibration can result in a representation of the "effective" source. In some cases, an actual measured source profile is available and can be referenced directly in the OPC recipe. However, it is common to average the 4 quadrants of a measured source profile such that the source representation is symmetrical about the x and y axes. This is done so that optical proximity correction can be applied hierarchically, with a single correction applied to a cell which may be instantiated in multiple orientations within the chip. It has generally been accepted that the positive runtime benefit accompanying this symmetrization is beneficial relative to any potential accuracy loss for cells oriented in different directions. In this paper, we investigate the impact of real source profile asymmetries on identical features with different orientations.

Extending lithography to 32 nm and 22 nm half pitch requires the introduction of new lithography technologies, such as EUVL or high-index immersion, or new techniques, such as double patterning. All of these techniques introduce large changes into the single exposure immersion lithography process as used for the 45 nm half pitch node. Therefore, cost per wafer is a concern. In this paper, total patterning costs are estimated for the 32 nm and 22 nm half pitch nodes through the application of cost-of-ownership models based on the tool, mask, and process costs. For all cases, the cost of patterning at 32 nm half pitch for critical layers will be more expensive than in prior generations. Mask costs are observed to be a significant component of lithography costs even up to a mask usage of 10,000 wafers/mask in most cases. The more simple structure of EUVL masks reduces the mask cost component and results in EUVL being the most cost-effective patterning solution under the assumptions of high throughput and good mask blank defect density.