Statistical approach to design DRAM bitcell considering overlay errors

Yu-Jin Pyo; Dae-Wook Kim; Jai-Kyun Park; Ji-Seong Doh; Hyun-Jae Kang; Ji-Suk Hong; Chul-Hong Park; Sang-Hoon Lee; Moon-Hyun Yoo

doi:10.1117/12.815341

12 March 2009 Statistical approach to design DRAM bitcell considering overlay errors

Yu-Jin Pyo, Dae-Wook Kim, Jai-Kyun Park, Ji-Seong Doh, Hyun-Jae Kang, Ji-Suk Hong, Chul-Hong Park, Sang-Hoon Lee, Moon-Hyun Yoo

Author Affiliations +

Proceedings Volume 7275, Design for Manufacturability through Design-Process Integration III; 72751L (2009) https://doi.org/10.1117/12.815341
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

Overlay performance and control requirements have become crucial for achieving high yield and reducing rework process. Increasing discrepancy between hardware solutions and overlay requirements, especially in sub-40nm dynamic random access memory (DRAM) devices, motivates us to study process budgeting techniques and reasonable validation methods. In this paper, we introduce a SMEM (Statistical process Margin Estimation Method) to design the DRAM cell architecture which considers critical dimension (CD) and overlay variations in the perspectives of both cell architecture and manufacturability. We also proposed the method to determine overlay specifications. Using the methodologies, we obtained successfully optimized sub-40 DRAM cells which accurately estimated process tolerances and determined overlay specifications for all layers.

Citation Download Citation

Yu-Jin Pyo, Dae-Wook Kim, Jai-Kyun Park, Ji-Seong Doh, Hyun-Jae Kang, Ji-Suk Hong, Chul-Hong Park, Sang-Hoon Lee, and Moon-Hyun Yoo "Statistical approach to design DRAM bitcell considering overlay errors", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751L (12 March 2009); https://doi.org/10.1117/12.815341

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