This PDF file contains the front matter associated with SPIE Proceedings Volume 7637, including the Title Page, Copyright information, Table of Contents, Introduction, and the Conference Committee listing.

Multi-beam writing becomes mandatory in order to stay within reasonable realization times for the fabrication of leading-edge complex masks and templates. IMS Nanofabrication has developed multi-beam projection techniques implementing a programmable aperture plate system (APS) and charged-particle projection optics with 200x reduction. Proof-of-concept of multi-beam writing was demonstrated in 2009 with 10 keV ion multi-beams and 50 keV electron multi-beams using 43-thousand and 2.5-thousand, respectively, programmable 12.5nm sized beams. In Q4 2009 the development of a 50 keV electron multi-beam Mask Exposure Tool (eMET) was started with the aim to realize 256-thousand programmable 20 nm and 10 nm sized beams. The eMET column realization will provide important synergies for the development of projection mask-less lithography (PML2) for direct write on wafers. In order to enhance throughput a Multi-Axis-PML2 scheme is put forward with potential throughput of 5 WPH for the 16 nm hp technology node and below. Clustering such maskless tools a throughput of 50-100 WPH within a scanner floor space is envisioned. Ion multi-beam techniques may be applied for 2.5D / 3D template fabrication and resistless nanopatterning.

Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. However, many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for semiconductor high volume manufacturing (HVM). This paper discusses the current status of SFIL, including the process and templates, and shows where more industry collaboration is needed to solve the most critical issues.

Reverse-tone Step and Flash Imprint Lithography (S-FIL/R) requires materials that can be spin coated onto patterned substrates with significant topography and that are highly-planarizing. Ideally, these planarizing materials must contain silicon for etch selectivity, be UV or thermally curable, have low viscosity, and low volatility. One such novel material in particular, a branched and functionalized siloxane (Si-12), is able to adequately satisfy the above requirements. This paper describes a study of the properties of epoxy functionalized Si-12 (epoxy-Si-12) as a planarizing layer. An efficient synthetic route to epoxy-Si-12 was successfully developed, which is suitable and scalable for an industrial process. Epoxy-Si-12 has a high silicon content (30.0 %), low viscosity (29 cP @ 25 °C), and low vapor pressure (0.65 Torr @ 25 °C). A planarizing study was carried out using epoxy-Si-12 on trench patterned test substrates. The material showed excellent planarizing properties and met the calculated critical degree of planarization (critical DOP), which is a requirement for a successful etch process. An S-FIL/R process using epoxy-Si-12 was demonstrated using, an Imprio^R 100 (Molecular Imprints Inc., USA) imprint tool. The results indicate that epoxy-Si-12 works very well as a planarizing layer for S-FIL/R.

In this paper, the status of mask-less lithography for advanced semiconductor applications is reviewed. Mask-less lithography received a lot of interest as the lithography for manufacturing the critical layers of advanced integrated processes, because of the severe increase in mask costs that the industry is experiencing for critical layers as of the 45nm technology onwards. The availability of mask-less lithography would allow to get rid of these mask costs, which is in particular interesting for low volume products. First the various mask-less initiatives are reviewed, with emphasis on the European ones. The typical results that are obtained by these groups are reviewed and compared to the requirements that need to be met to become the lithography process of choice for the manufacturing of certain critical layers in advanced chips. The requirements are typically expressed in terms of resolution, overlay and throughput. A number of key conclusions are drawn : focus of mask-less tool development should be on insertion at the 16nm node, with extendibility to 11nm. Promising resolution results have been demonstrated by various groups. Today the proof-of-concept tools have not shown any overlay nor throughput performance, which needs to become the main focus for the next few years. Finally, it is recommended to focus on a parallel beam mask writer initially, where the level of complexity is much lower but most of the same challenges will need to be addressed.

Projection Mask-Less Lithography (PML2) is a potentially cost-effective electron multi-beam solution for the 16 nm hp ITRS technology node and beyond. First results obtained with a PML2 Testbench are presented where a programmable Aperture Plate System (APS) was used to generate ca. 2500 micrometer-sized beams which are projected onto wafer level with 200x demagnification. The APS contains CMOS electronics which allows for addressable deflection of selected beams; only non-deflected beams make it to the wafer surface to achieve 12.5 nm spot size. Beam energy (50keV) and current density (~2 A/cm²) are the same as in future PML2 production tools. Thus, the results obtained with the PML2 Testbench unambiguously prove the patterning capabilities of the PML2 technology.

In the Mask D2I project at ASET, the authors evaluated an e-beam multi column cell exposure system with character projection to expose photomask patterns of hp65nm and hp45nm devices. They prepared more than 2,000 characters in a deflection area of a character projection mask extracted from the hp65nm pattern. The character projection in the multi column cell system could expose patterns equivalent to those by the conventional variable shaped beams. In a typical pattern layout of photomasks for hp45nm devices, the four column cell system required an exposure time of about 1/3 of the time required by a single column system. The character projection can reduce the exposure time corresponding to the reduction of shot counts.

In this paper, we propose and evaluate maskless electron beam direct writing (EBDW) with double character projection (CP) apertures. In the conventional CP-capable EBDW, the first aperture generates a square beam and the second aperture finalizes the complex character shape. In our proposed method, each aperture has complex character patterns. The double CP apertures system projects circuit patterns onto a wafer by the combined use of two apertures. We present a novel pattern writing algorithm for double CP apertures, especially a generation/merging method of character patterns. The experimental results on ITC'99 benchmark circuit b19 synthesized with Nangate 45nm Open Cell Library showed that throughput of the proposed method was enhanced up to 147.3% of the variable-shaped beam method and up to 117.5% of the conventional CP method.

Electron Beam Direct Write lithography is used in the IC manufacturing industry to sustain optical lithography for prototyping applications and low volume manufacturing. It is also used in R&D to develop the technological nodes ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the need to accurately control the dimensions and the roughness of the features becomes tighter. As a consequence the requirements in terms of process window and resolution for the electron beam tools are more stringent. However the standard proximity effects corrections show difficulties to provide the required energy latitude for the sub-22nm nodes. A new approach is thus required to improve the patterning capabilities of electron beam lithography. In previous papers a new writing strategy based on multiple pass exposure has been introduced and optimized to pattern critical dense lines. This technique consists in adding small electron Resolution Improvement Features (eRIF) on top of the nominal structures. Previous studies have demonstrated that the energy latitude and the writing time can be optimized by tuning the design of the eRIF. A methodology to implement the eRIF on dense lines has also been established. The goal of this paper is to extend the use of the multiple pass exposure strategy to more complex designs taken from products layouts. The most critical layers of SRAM and Logic layouts down to the 16nm node are corrected with this advanced correction technique. The results from wafer exposures show that the edge roughness of the features is decreased and the energy latitude of our process is multiplied by two for each SRAM layer. Thanks to these improvements of the patterning capabilities of our electron beam tool, a gain in resolution of one technological node is achieved. Finally a method is proposed to implement the multiple pass exposure within an automated data preparation flow.

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made with a throughput of 10-20 wafers per hour. By clustering several of these systems together high throughputs can be realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV alternatives^[1]. In 2009 MAPPER shipped two systems one to TSMC and one to CEA-Leti. Both systems will be used to verify the applicability of MAPPER's technology for CMOS manufacturing. This paper presents a status update on the development of the MAPPER system over the past year. First an overview will be presented how to scale the current system to a 10 wph machine which can consequently be used in a cluster configuration to enable 100 wph throughputs. Then the results of today's (pre-) alpha systems with 300 mm wafer capability are presented from the machines at MAPPER, TSMC and CEA-Leti.

We survey several different approaches wherein self-assembly has been applied in lithographic patterning. As part of this survey, we trace the evolution of block copolymer directed self-assembly used as lithographic technique, and summarize its current status. We compare a process based on block copolymer lithography with an equivalent process based on spacer pitch division. We conclude with a brief discussion of design issues and future research in the field.

Block copolymers have been proposed for self-assembled nanolithography because they can spontaneously form well-ordered nanoscale periodic patterns of lines or dots in a rapid, low-cost process. By templating the selfassembly, patterns of increasing complexity can be generated, for example arrays of lines with bends or junctions. This offers the possibility of using a sparse template, written by electron-beam lithography or other means, to organize a dense array of nanoscale features. Pattern transfer is simplified if one block is etch resistant and one easily removable, and in this work we use a diblock copolymer or a triblock terpolymer with one Sicontaining block such as polydimethylsiloxane or polyferrocenylsilane, and one or two organic blocks such as polystyrene or polyisoprene. Removal of the organic block(s) with an oxygen plasma leaves a pattern of Sicontaining material which can be used as an etch mask for subsequent pattern transfer to make metallization lines or magnetic nanostructures with feature sizes below 10 nm and periodicity below 20 nm.

Single FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer are demonstrated in this work. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved with a unique guiding layer and the self-assembly process is integrated with an existing CMOS process flow using conventional tools on a full 4" wafer level. Potential application for block copolymer patterning on SRAM circuit level is also discussed.

An outline of research on the directed assembly of block copolymer films to meet the needs of advanced lithographic systems, as defined by the International Technology Roadmap for Semiconductors, is presented. These requirements include pattern perfection, control of placement of features, the ability to generate patterns corresponding to regular fabric architectures, control of feature shapes and dimensions, scaling to below 10 nm, and pattern transfer. Accomplishments toward these requirements have been achieved by self-assembly with solvent annealing and by directed assembly on topographical or chemical patterns. Looking forward, these requirements must be met simultaneously, and examples are provided that show simultaneous achievement of many of these requirements. In addition, research focusing on specific implementation opportunities, such as directed assembly in 193 nm immersion lithography, is briefly discussed.

Cationic self-assembled monolayers (SAMs) can easily be formed on silicon dioxide via siloxane chemistry, and these SAMs provide robustly attached surface charges that anchor DNA nanostructures and origami. The surface charge of the SAM can be controlled by formation of mixed monolayers of aminopropyltriethoxysilane (APTES) and trimethyl aminopropyltrimethoxysilyl chloride (TMAC). X-ray photoelectron spectra of mixed monolayers show surface charges ranging from about 1 to 3 charges per nm². At high mole fractions of APTES, binding defects such as folded and rolled origami are common; at moderate mole fractions of APTES, binding metrics for DNA origami are comparable to mica, and on pure TMAC, binding is weaker than on mica. In order to locate individual DNA nanostructures at desired sites, 35-40 nm APTES dots or 125 nm APTES stripes were fabricated by a combination of EBL and molecular liftoff. Deposition of small DNA nanostructures (8 nm × 37 nm × 2 nm) or DNA origami (60 nm × 90 nm) was conducted in 0.1-1.0 micromolar solution. The binding selectivity between the anchor pads and the background silicon dioxide was at least 50:1. The DNA origami are persistently attached and can be imaged in air after rinsing the substrate in flowing water.

We have developed a processing method that employs direct surface imaging of a surface-modified silicon wafer to define a chemical nanopattern that directs material assembly, eliminating most of the traditional processing steps. Defining areas of high and low surface energy by selective alkylsiloxane removal that match the polymer period length leads to defect-free grating structures of poly(styrene-block-methyl methacrylate) (PS-b-PMMA). We have performed initial studies to extend this concept to other wavelengths beyond 157 nm. In this present paper, we will show that electron beam lithography can also be used to define chemical nanopatterns to direct the assembly of PS-b-PMMA films. Half-pitch patterns resulted in the directed assembly of PS-b-PMMA films. Electron beam lithography can also be used to prepare surfaces for pitch division. Instead of the deposition of an HSQ pinning structure as is currently done, we will show that by writing an asymmetric pattern, we can fill in the space with smaller lamellar period block copolymers to shrink the overall pitch and allow for 15-nm features.

Carbon nanotubes (CNTs) have many unique properties ideal for field emission such as narrow diameters, high aspect ratios, high temperature stability, good conductivity, and structural strength. A gated array is preferable to a diode type array due to the lower extraction voltages and reduced screening effects. An inexpensive fabrication process has been developed using self-assembling nanosphere lithography for sub-micron gate dimensions of a CNT field emission array. The array fabrication process consists of a silicon wafer with a 20 nm titanium diffusion barrier followed by 10 nm nickel catalyst layer covered with 1-2 μm of silicon dioxide. Self-assembling polystyrene spheres are deposited in a monolayer across the substrate to create the gate mask. The diameter of the spheres is reduced to the desired gate dimensions using an oxygen plasma ash. The gate metal is then deposited via evaporation. The gate openings are created through lift-off facilitated by dissolving the polystyrene spheres in an ultrasonic acetone bath. Reactive ion etching is used to remove the silicon dioxide and expose the nickel catalyst layer for CNT synthesis within the gate openings. The process is demonstrated for both 1 μm and 500 nm diameter polystyrene spheres for gate dimensions and gate pitch of 500 nm and 250 nm respectively. The resulting array is analyzed using a scanning electron microscope. Further development of the polystyrene monolayer deposition method is necessary to decrease defects in the monolayer structure. Future work will investigate the reduction of gate dimensions to 20 - 50 nm to facilitate a single CNT per gate array.

Self-assembling block copolymer thin films have attracted considerable attention as a promising high resolution lithographic tool due to the 10 nm scale of microdomain ordering and their facility for modulation of size and pattern. However, for block copolymer lithography to be a viable solution for advanced nano-lithographic technologies, several critical requirements need to be satisfied. Our research has focused on developing complementary mixed polymer brush lithography tools satisfying the required criteria, by means of Self-Consistent Field Theory (SCFT) simulations. Specifically, we have concentrated on graphoepitaxial techniques that are widely tested and considered a particularly promising method for controlling the microdomain ordering.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology

Nanoimprint Lithography (NIL) is a high throughput replication technology for structures ranging from micrometer down to few nanometers. NIL can be divided into UV-Nanoimprint (UV-NIL) and Hot embossing (HE). The main difference between these two techniques are the material types of both template and resist, i.e transparent templates and photosensitive resists for UV-NIL and non transparent templates and thermoplastic resists for HE. Hot embossing is a low-cost, high throughput fabrication technique of disposable, polymer based devices needed for emerging point-of care diagnostic or bio-sensing applications. This paper describes the technology for imprinting of polymer substrates as well as spin-on polymers by using soft working stamp materials on a fully automated hot embossing system, the EVG^R750, built to use this rapid replication processes. Soft working stamps demonstrate the possibility to replicate both, high-aspect ratio features in thermoplastic materials as needed for microfluidic lab-on-chip applications as well as high resolution features down to 50 nm in polymers that can be used as templates for pattern transfer in the fabrication of plasmonic substrates for biosensing applications.

Targeting applications that require resolution of around 25nm on substrates to 200mm, automated equipment is described that performs the molecular transfer lithography process in which water-soluble templates of polyvinyl alcohol, replicated from master topography on silicon, are coated with resist and bonded onto substrates. Moreover, to eliminate the need for handling wet resist, dry bondable epoxy-based resist is demonstrated, which is pre-coated on the templates and shipped to the fabrication facility where the automation equipment is housed thereby improving ease-of-use, efficiency and throughput, while lowering costs.

Scanning probe-based methods for surface modification and lithography are an emerging method of producing sub 20-nm features for nanoelectronic applications. In this study, we have demonstrated the nanoscale lithography based on patterning of 10 to 50-nm-thick calix[4]arene by electric-field-induced electrostatic scanning probe lithography. The features size control is obtained using electrostatic interactions and depends on the applied bias and speed of the AFM tip. The width of the obtained lines and dots varies from 10 to 60 nm depending on tip-sharpness, tip-substrate separation and tip-bias voltage.

For shortening the writing time, especially in shaped Electron Beam Direct Writing (EBDW), it is crucial to reduce the number of shapes and the coverage of layout for exposure. The determination of conventional or reversed image printing according to the process integration is one of the concerns for time and cost-effective process in the EBDW. We have studied two different cases for the purpose above. First, the proximity effect correction (PEC) with dose modification applied on each tone of resists, positive and negative, for the printing of conventional and reversed images. The CDs that are obtained from the both printed images compared and are either with that from the simulations. Secondly, the two different types of PEC, dose and shape modification, applied to a conventional image using an identical point spread function (PSF). The line edge roughness (LER), line width roughness (LWR) and CDs in dose and shape corrected conventional image pattern have been measured and compared. The MGS/PROXECCO was used for all the preparation of exposure data mentioned above. In summary, we suggest the strategies of efficient PEC for the EBDW of contrasting images, propose the available method of PEC for the time-efficient EBDW, and for the further multiple EBDW developments.

Electron beam lithography (EBL) causes pattern distortions and printability issues during its entire pattern making process, starting from the mask design and finishing with the lithography processes. Hence EBL aerial image formation and proximity correction (PC) modeling becomes more critical and urgent especially for full chip layouts and designs before EBL may be deployed in high-volume manufacturing. This study shows a complete solution for EBL modeling and Electron Beam Proximity Correction (EBPC) correction of full-chip layouts based on aerial image formation through modeling of the e-beam point spread function to assimilate electron beam image formation. The main idea behind the method is to construct a model-based analyses and interpretation of generic pattern distortions of non-corrected representative patterns to achieve the best possible matching of EBL proximity effects with extracted empirical data using an analytical EBL absorbed energy distribution form based on three or more Gaussians, and the form's convolution with representative patterns. Two approaches have been used for EBL model simulation and the comparison of the models is shown. The method has been successfully implemented and integrated into existing tools for modeling.

Despite the great potential of nanomaterials in electronic and photonic applications, their incorporation into functional devices will require the combination of top-down lithographic large-area patterning with the high resolution and chemical precision afforded by bottom-up self-assembly. Despite the wealth of existing lithography techniques, there remain significant hurdles to addressing below the 20nm regime. In light of these challenges, there have been significant efforts to use "bottom-up" or self-assembly approaches for patterning. One key, "manufacturable" approach has been to merge self-assembling systems with substrates patterned using conventional lithographic techniques. This paper will show our recent efforts in directing the placement of single stranded DNA and DNA templates on several different substrates that have been patterned by lithography. A variety of substrates have been generated by optical and e-beam lithography and these have been used to produce highly parallel arrays of mesoscale DNA scaffolds and DNA oligonucleotides in a single step. Furthermore, these DNA templates encode multiple nanometer recognition sites that can be further used to generate hierarchical assemblies of both organic and inorganic nanoscale materials. Because a significant challenge of future nanotechnology is the ability to address sub-20nm features, these self-assembled DNA arrays are being explored as potential templates for the assembly and wiring of nanoscale materials for both logic and memory.

This paper presents the fabrication and measurements of MOSFETs with various dopant distributions in the channels for investigating the impact of discrete dopant distribution on device performances. Phosphorus-ions are implanted "orderly" into the channels as well as "asymmetrically" into one side of channels both with ordered and random distribution by single-ion implanter with capability of one-by-one doping. Electrical measurements reveal that the threshold voltage (V_th) fluctuation for the ordered dopant arrays is less than for conventional random doping and the device with ordered dopant array exhibits two times the lower average value (-0.4V) of V_th shift than the random dopant distribution (-0.2V). We conclude that the observed lower value originates from the uniformity of electrostatic potential in the channel region due to the ordered distribution of dopants. We also observe deviation in subthreshold current when interchanging the source and drain terminals. The subthreshold current is always larger when the dopants are located at the drain side than at the source side for both ordered and random distribution cases. We believe that this increase in current is caused by the suppression of injection velocity degradation in the source side. Accurately controlling both the amount and the positioning of dopant atoms is critical for the advancement of extending CMOS technologies with reduced variation caused by random dopant fluctuation.

In this paper we report on the development of a Surface Electron Emission Lithography system (SEL) for high resolution and high throughput Electron Beam (EB) lithography. The Parallel EB lithography is performed on a 1:1 prototype electron stepper. A planar type silicon nanowire array ballistic electron emitter (PBE) is employed as a patterned electron emitting mask in this system. The PBE has a metal / silicon nanowire array / semiconductor structure. The nanowire is composed of interconnected silicon nanocrystallites. When a bias voltage is applied to the nanowire, the electrons injected from semiconductor substrate are accelerated via cascade tunneling between silicon nanocrystallites, and emitted from metal surface electrode. The PBE exhibits properties originated from the ballistic transport in nanosilicon layer. The electrons are emitted with uniform intensity in the surface. The emission current is fluctuation-free and low sensitivity against an environmental atomosphere. The PBE projects the pattern on the target wafer in the electron optics of parallel electric and magnetic fields. If all emitted electrons have same initial velocity, they are focused at the same distance. The pattern of the mask on the PBE is reproduced on the target wafer at the distance of the n (n=1, 2, ...) cycle of the spiral trajectory of the electron. Practical resolution is limited by the chromatic aberration in this system. We can improve the resolution by reducing the initial energy spread and emission angle dispersion of the emitted electrons because of the characteristics of the ballistic electron emission from PBE. In this study, we confirmed that the submicron patterns is reproduced all over the area of 2.8 mm square. This homogeneity of exposure in the extended area results from the uniformity of nanowire array produced by self-organized chemical reaction process. This technique will be available to produce next generation MEMS with lower cost than that of optical stepper.

Optical lithography has been the key for continuous size reduction of semiconductor devices and circuits manufacturing. Although the industry is continually improving the resolution, optical lithography becomes more difficult and less cost effective in satisfying the ever increasing demands in nano-manufacturing. Besides manufacturing, the dramatic advancements in nanoscale science and engineering also call an urgent need for high-throughput nano-fabrication technologies that are versatile to frequent design changes. Here we experimentally demonstrated the capability of patterning with 50 nm linewidth with a high flying speed at 10 meter/second. This low-cost nano-fabrication scheme has the potential of a few orders of magnitude higher throughput than current maskless techniques, and promises a new route towards the next generation nano-manufacturing. Besides its application in nanolithography, this technique can also be used for nanoscale metrology, imaging and data storage.

In this paper a full package high throughput multi electron-beam approach, called Multi Shaped Beam (MSB), for applications in mask making as well as direct write will be presented including complex proof-of-lithography results. The basic concept enables a significant exposure shot count reduction for advanced patterns compared to standard Variable Shaped Beam (VSB) systems and allows full pattern flexibility by concurrently using MSB, VSB and Cell Projection (CP). Proof of lithography results will be presented, which have been performed using a fully operational electron-beam lithography system including data path and substrate scanning by x/y-stage movement.

Future lithography systems must produce chips with smaller feature sizes, while maintaining throughput comparable to today's optical lithography systems. This places stringent data handling requirements on the design of any direct-write maskless system. To achieve the throughput of one wafer layer per minute with a direct-write maskless lithography system, using 22 nm pixels for 45 nm technology, a data rate of 12 Tb/s is required. In our past research, we have developed a datapath architecture for direct-write lithography systems, and have shown that lossless compression plays a key role in reducing throughput requirements of such systems. Our approach integrates a low complexity hardware-based decoder with the writers, in order to decode a compressed data layer in real time on the fly. In doing so, we have developed a spectrum of lossless compression algorithms for integrated circuit rasterized layout data to provide a tradeoff between compression efficiency and hardware complexity, the most promising of which is Block Golomb Context Copy Coding (Block GC3). In this paper, we present the synthesis results of the Block GC3 decoder for both FPGA and ASIC implementations. For one Block GC3 decoder, 3233 slice flip-flops and 3086 4-input LUTs are utilized in a Xilinx Virtex II Pro 70 FPGA, which corresponds to 4% of its resources, along with 1.7 KB of internal memory. The system runs at 100 MHz clock rate, with the overall output rate of 495 Mb/s for a single decoder. The corresponding ASIC implementation results in a 0.07 mm² design with the maximum output rate of 2.47 Gb/s. In addition to the decoder implementation results, we discuss other hardware implementation issues for the writer system data path, including on-chip input/output buffering, error propagation control, and input data stream packaging. This hardware data path implementation is independent of the writer systems or data link types, and can be integrated with arbitrary directwrite lithography systems.

E-beam direct write (EBDW) is one of the potential solutions for technology nodes of 28-nm half-pitch (HP) and beyond. Throughput limitation confined its development mostly to small-volume prototyping. Recently, proposals have been made to achieve throughput greater than 10 wafers per hour (WPH) on a single column with >10,000 beams writing in parallel (MEBDW), or even greater than 100 WPH by further clustering multiple columns within a typical production-tool footprint. The MAPPER concept contains a CMOS-MEMS blanker array driven by high-speed optical data path architecture to simultaneously control >10,000 beams, switching them on and off independently. The MAPPER Pre-Alpha Tool with a 110-beam, 5-keV column and a 300-mm wafer stage has been installed in a semiconductor manufacturing cleanroom environment and is ready for imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 30-nm half-pitch (HP) dense hole on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including resolution, local variation, focusing, energy latitude, proximity effect correction and electron scattering model fitting of hole patterning are discussed. Similar to mask-error-enhanced-factor (MEEF), the new writing-error-enhanced-factor (WEEF) to describe the impact of writing error, is introduced.

Texas Instrument's spatial light modulator chip, the DMD (digital micromirror device, the central chip in all DLP based systems) has been used in multiple maskless lithography applications for the past 5-7 years. Typically these applications have been focused on PCB lithography. Applications using illumination below 320nm have not been feasible due to shortened lifetime of the device at shorter wavelengths. Recent advances in DMD processing have made significant improvements in the operational lifetime of the DMD. This paper will cover the background of UV-A DMD maskless lithography and demonstrate the increased lifetime at 311nm and 266nm with the new processes.

A solution to the problems of roll-to-roll lithography on flexible substrates is presented. We have developed a roll-toroll imprint lithography technique to fabricate active matrix transistor backplanes on flexible webs of polyimide that have a blanket material stack of metals, dielectrics, and semiconductors. Imprint lithography produces a multi-level 3- dimensional mask that is then successively etched to pattern the underlying layers into the desired structures. This process, Self-Aligned Imprint Lithography (SAIL), solves the layer-to-layer alignment problem because all masking levels are created with one imprint step. The processes and equipment required for complete roll-to-roll SAIL fabrication will be described. Emphasis will be placed on the advances in the roll-to-roll imprint process which have enabled us to produce working transistor arrays.

The Jet and Flash Imprint Lithography (J-FIL) process uses drop dispensing of UV curable resists for high resolution patterning. Several applications, including patterned media, are better, and more economically served by a full substrate patterning process since the alignment requirements are minimal. Patterned media is particularly challenging because of the aggressive feature sizes necessary to achieve storage densities required for manufacturing beyond the current technology of perpendicular recording. In this paper, the key process steps for the application of J-FIL to pattern media fabrication are reviewed with special attention to the vapor adhesion layer and imprint performance at >300 disk per hour.

In order to unlock the true potential of nanotechnology, the development of controlled nanomanufacturing techniques for individual structures is critical. While the capability to grow, deposit, and manipulate nanostructures currently exists, the ability to reliably fabricate these devices with controlled differences in size, shape, and orientation at various substrate positions does not exist. To bridge this gap, the Defense Advanced Research Projects Agency (DARPA) launched the Tip-Based Nanofabrication (TBN) research program with the intent of achieving controlled nanomanufacturing of nanowires, nanotubes and quantum dots using functionalized AFM cantilevers and tips. This work describes the background, goals, and current approaches being explored during the multi-year TBN program.

A high-resolution probe based patterning method is presented using organic resists that respond to the presence of a hot tip by local material desorption. Thereby arbitrarily shaped patterns can be written in the organic films in the form of a topographic relief. The patterning process is highly reproducible and repeatable enabling the creation complex relief structures with arbitrary texture also in the vertical dimension. The patterns can be readily transferred into silicon using standard RIE technology. The new technique offers a cost-effective and competitive alternative to high-resolution electron-beam lithography in terms of both resolution and speed.

We suggest near-field optical lithography that uses contact probe for high speed patterning. The contact probe contains high transmission metal nano aperture and cover-layer for gap distance formation without external feed-back control unit. For contact mode operation, lubricant layer is applied between probe and photoresist surface. Using this contact probe, we recorded 50nm width line pattern with 10mm/s which is 500 times faster than conventional near-field scanning optical microscope lithography. The various line patterns having are recorded as increasing exposure dose and pattern qualities such as line width roughness (LWR) and depth roughness (DR) are evaluated. We expect the contact probe could be extended array probe lithography system for high throughput plasmonic lithography for mass production.

In this paper, a maskless single step multiple (two and four) beams surface plasmon interference lithographic configuration is proposed and illustrated experimentally so as to obtain interference pattern with resolution several orders less than the illumination source wavelength. This technique utilizes a custom made prism layer configuration to pattern both one dimensional (grating line) and two dimensional (dot array) periodic nanostructures on the recording medium. Both aluminum and silver metal films are used for the experimental study. Large area patterns of grating lines and dot arrays with feature size ≈ 90 nm were experimentally obtained using an exposure radiation of 364 nm wavelength.

While directed self-assembly of diblock copolymers is increasingly developed in terms of process flow, metrology and evaluation are the next crucial step in maximizing its effectiveness for integration into device design based on directed self-assembly trends. We present a novel image processing and data analysis program, SLICE (Sub-Lithography Imaging Computation and Evaluator), whose capabilities enable a systematic, automated analysis and characterization of directed self-assembly (SA) of block copolymers for high-density circuit integration. Key features such as defect-free region detection and trench-to-trench comparison of SA quality illustrate the potentially significant impact of SLICE to the process optimization and commercialization of sub-lithographic techniques.

The accuracy of image placement and linewidth on masks has become very crucial to the point that even minor variations in exposure parameters require re-works and result in increasing mask cost. In 2006, at the Association of Super-Advanced Electronics Technologies (ASET), Mask Design, Drawing and Inspection technology Research Department (Mask D2I) had launched a 4-year development program for the optimization of mask design, drawing, and inspection to reduce photomask manufacturing cost. An outline of a system to monitor and self-diagnose the process of data transfer, magnetic field change, and vibration during exposure is described here.

Future lithography systems must produce microchips with smaller feature sizes, while maintaining throughputs comparable to those of today's optical lithography systems. This places stringent constraints on the effective data throughput of any maskless lithography system. In recent years, we have developed a datapath architecture for direct-write lithography systems, and have shown that compression plays a key role in reducing throughput requirements of such systems. Our approach integrates a low complexity hardware-based decoder with the writers, in order to decompress a compressed data layer in real time on the fly. In doing so, we have developed a spectrum of lossless compression algorithms for integrated circuit layout data to provide a tradeoff between compression efficiency and hardware complexity, the latest of which is Block Golomb Context Copy Coding (Block GC3). In this paper, we present a modified version of Block GC3 called Block RGC3, specifically tailored to the REBL direct-write E-beam lithography system. Two characteristic features of the REBL system are a rotary stage resulting in arbitrarily-rotated layout imagery, and E-beam corrections prior to writing the data, both of which present significant challenges to lossless compression algorithms. Together, these effects reduce the effectiveness of both the copy and predict compression methods within Block GC3. Similar to Block GC3, our newly proposed technique Block RGC3, divides the image into a grid of two-dimensional "blocks" of pixels, each of which copies from a specified location in a history buffer of recently-decoded pixels. However, in Block RGC3 the number of possible copy locations is significantly increased, so as to allow repetition to be discovered along any angle of orientation, rather than horizontal or vertical. Also, by copying smaller groups of pixels at a time, repetition in layout patterns is easier to find and take advantage of. As a side effect, this increases the total number of copy locations to transmit; this is combated with an extra region-growing step, which enforces spatial coherence among neighboring copy locations, thereby improving compression efficiency. We characterize the performance of Block RGC3 in terms of compression efficiency and encoding complexity on a number of rotated Metal 1, Poly, and Via layouts at various angles, and show that Block RGC3 provides higher compression efficiency than existing lossless compression algorithms, including JPEG-LS, ZIP, BZIP2, and Block GC3.

Self Aligned Double Patterning (SADP) has the advantage of dense array definition with good pitch control and is hence useful for memory devices; but its feasibility of two-dimensional circuit patterns definition is restricted on the other hand. In SPIE 2009, we had proposed the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array) decomposition by SADP, based on manual design. The concerns of process integration as well as SADP alignment algorithm for each mask step were investigated and countermeasures were presented. In this paper, the previous works on manual-based pattern decomposition are extended to a more sophisticated use on full-area NAND FLASH critical layer layout decomposition by utilizing an automated electronic design (EDA) tool. The decomposition tool together with OPC and simulation tools are integrated to optimize the lithographic performance of local critical patterns in each decomposed mask step, and comparisons have been made as well to investigate the differences in layout splitting algorithm between EDA-based and manual-based decomposition. Finally, the full-area (9350×12800um) layout decomposition has been successfully demonstrated on NAND FLASH Gate and Metal critical layers by using the EDA tool with improved 2D structure handling algorithms.

A novel lithography process for 3D (Three-dimensional) interconnect was developed using an optical direct-writing exposure tool. A reflective IR (Infra-red) alignment system allows a direct detection of alignment marks both on front-side and back-side of wafer, and consequently allows feasible micro-fabrication for 3D interconnect using the reversed wafer. A combination of the optical direct-writing exposure tool of Dainippon Screen MFG. Co., Ltd. with the reflective IR alignment system and a high aspect chemically amplified resist of Tokyo Ohka Kogyo Co., Ltd. provides the lithography process exclusively for 12-inch wafer level 3D interconnect.

Electron-beam lithography is promising for future manufacturing technology because it does not suffer from wavelength limits set by light sources. Since single electron-beam lithography systems have a common problem in throughput, a multi-electron-beam lithography (MEBL) system should be a feasible alternative using the concept of massive parallelism. In this paper, we evaluate the advantages and the disadvantages of different MEBL system architectures, and propose our novel Massively Parallel MaskLess Lithography System, MPML2. MPML2 system is targeting for cost-effective manufacturing at the 32nm node and beyond. The key structure of the proposed system is its beamlet array cells (BACs). Hundreds of BACs are uniformly arranged over the whole wafer area in the proposed system. Each BAC has a data processor and an array of beamlets, and each beamlet consists of an electron-beam source, a source controller, a set of electron lenses, a blanker, a deflector, and an electron detector. These essential parts of beamlets are integrated using MEMS technology, which increases the density of beamlets and reduces the system cost. The data processor in the BAC processes layout information coming off-chamber and dispatches them to the corresponding beamlet to control its ON/OFF status. High manufacturing cost of masks is saved in maskless lithography systems, however, immense mask data are needed to be handled and transmitted. Therefore, data compression technique is applied to reduce required transmission bandwidth. The compression algorithm is fast and efficient so that the real-time decoder can be implemented on-chip. Consequently, the proposed MPML2 can achieve 10 wafers per hour (WPH) throughput for 300mm-wafer systems.

Patterning of sub-30 nm features using high resolution nano-imprint lithography (NIL) requires use of quartz templates. To this end, various fabrication methods such as e-beam lithography, edge lithography, and focused ion beam lithography were employed for the template formation. Despite significant advances using these methods, NIL template formation process suffers from low throughput and high cost of fabrication when compared with the fabrication of masks used in optical lithography. This is largely owing to a 4X difference in feature sizes involved for the fabrication of NIL template and optical lithography mask. In this paper, we report on a simple, cost-effective method for the fabrication of sub-30 nm NIL templates. Typical fabrication-time required for the formation of sub-30 nm HP templates using conventional Gaussian beam electron beam lithography, runs into several days. Additionally, complicated etch procedures must be employed for pattern transfer onto quartz substrates. Here we propose a low cost, simplified fabrication process for the formation of high resolution NIL templates using wafer pattern replication. We fabricated sub- 30nmHP poly-silicon lines and spaces on silicon wafer using multiple patterning technique. These patterns were subsequently transferred onto quartz substrates using NIL technique. Several types of features were studied to realize a template using the triple patterning technique described above. Results of wafer printing using the said template will be discussed.

The CP (character projection) based multi-beam EBDW system MCC (Multi Column cell) seems to be most practical from the view point of the extension of single beam CP based methodology which we have already introduced to device production. But drastic enhancement approach is indispensable to attain higher throughput of more than 100 WPH for 22nm node and beyond. The three key factors are the multi-beam number, the cluster chamber number and the CP shot count reduction rate. In this report, we show the estimation results of beam number, cluster chamber number, CP reduction rate and current density to attain the throughput of 100 WPH with MCC.

The reflection of back-scattered electrons (BSE) at the objective lens of an electron beam writer leads to a diffuse resist exposure which extends over several millimetres. The deposed energy of this unintentional exposure is much lower than the direct one. However, if the area of the direct electron beam exposure is large enough the accumulated energy is no longer negligible and may cause significant CD variations. Therefore, it is of crucial importance to study possible ways of reducing this dose contribution to a minimum and in order to perform a correct proximity correction targeting to determine its radial distribution. In this work a model of a 50kV E-Beam writer was developed, consisting of a resist-coated silicon wafer and an opposing low-reflection disk mounted at the pole piece of the objective lens. In order to improve the low-reflection disk, different material compositions as well as an optimized surface topography of the disk are modelled.

Pitch doubling technologies are necessary for the 32nm half-pitch (HP) and beyond in order to extend optical lithography. Many different techniques have been examined including Litho-Litho-Etch (LLE), Litho-Etch, Litho-Etch (LELE), and Sidewall Image Transfer (SIT). Keeping all of the processes inside the litho cluster, as LLE achieves, affords process simplification and potential for the lowest cost of ownership for pitch doubling. Within LLE alone, there are varying approaches including spin-on chemical freeze materials, thermal cure, UV curable materials, among others. The challenge is to provide robust process performance while still achieving the lowest cost of ownership. For this paper, we are concentrating on the evaluation of the UV cure process. Our findings are the results of optimization of the UV cure dose and bake conditions and its affect on the lithographic performance. The optimized process was investigated for defectivity, critical dimension (CD), repeatability, pattern distortion, etch performance and readiness for high volume manufacturing. With respect to CD, the investigation included absolute value change (shrinkage or growth) and CD uniformity (CDU). For pattern distortion, we investigated line shrinkage, corner rounding, and line end pull back. Defectivity checks were conducted for full wafer comparison pre and post the UV cure process. Manufacturability measures include throughput, cost of ownership and process stability.

A model-based proximity effect correction methodology is proposed and tested for electron-beam-direct-write lithography. It iteratively modulates layout geometry by feedback compensation until the correction error converges. The energy intensity distribution is efficiently calculated by fast convolving the modulated layout with a point-spread function which models electron beam shape and proximity effects primarily due to electron scattering in resist. The effectiveness of this methodology is measured by iteration numbers required for meeting the patterning fidelity specifications. It is examined versus process parameters including acceleration voltage and resist thickness with several regular mask geometries and practical design layouts.

In order to realize industrial level manufacturing using Nano Imprint Lithography, one of the key challenges is to supply stamps for the high volume machines. The master stamp is typically time consuming to produce and thus very expensive. It is therefore preferable to produce the maximum amount of replicated stamp from a master and to ensure that each stamp replica can deliver as many imprints as possible without losing yield. Currently, stamp replication is an area of intense development. How to produce a replicated a stamp and how many replicas that can be achieved from each master depend both on feature sizes, pattern density as well as aspect ratio of the structures. Several different techniques can be combined in order to obtain a large number of stamp replicas from each master. The ability to combine several different techniques enables the choice of the ideal technique suited for each structure type. This paper will focus on how to address stamp replication challenges in order to secure an adequate supply of stamps to enable high volume manufacturing with Nano Imprint Lithography. Results will be presented on the number of stamps that can be manufactured from each master as well as the lifetime of each individual stamp.

At the end of 2008, the College of Nanoscale Science and Engineering (CNSE) formally accepted a Vistec VB300 Gaussian electron beam lithography system. The system is a key component of the overall lithography strategy of the College and complements existing state of the art tooling for 193nm immersion, Extreme Ultra Violet and nanoimprint. The demonstrated resolving power of the system easily exceeds that of the facility's optical scanners. Together with 300mm wafer compatibility, and a class 1 mini environment, the system is well poised to execute its primary mission of supporting a variety of programs in post CMOS device integration. For a 300mm tool to be able to exchange wafers with other tooling in a full flow line it is necessary to pass stringent backside metal contamination testing. TXRF (total reflection x-ray fluorescence) testing performed with 300mm wafers on the VB300 satisfied the permitted metal contamination levels and cleared the way for introduction of ebeam patterned wafers into the process flow. Most of the tooling in the 300mm line handles wafers in front opening universal pods (FOUPS). With the relatively low throughput of the system (hours per wafer, not wafers per hour), this type of interface is not required. In order to maintain a low level of defects, 300mm wafers are removed from the FOUPS in the class 1 mini environment and loaded into the system. In addition to the 300mm capability, the system supports a wide range of wafer sizes, photomasks and piece parts. This enables the platform to support the 200mm activities at the College as well as the small samples frequently encountered with novel materials that have no support tooling available for 200mm and 300mm wafer sizes. The VB300 platform readily met the Vistec standard acceptance test specifications. The paper presents details of the acceptance test together with examples of additional work in progress that includes implementation of rigorous tool monitor standards, imprint template fabrication and mix and match overlay between the VB300 and optical patterning tools.

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing in combination with high speed optical data transport for switching the electron beams. With 13,000 electron beams each delivering a current of 13nA on the wafer, a throughput of 10 wph is realized for 22nm node lithography. By clustering several of these systems together high throughputs can be realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV. The most mature and reliable electron source currently available that combines a high brightness, a high emission current and uniform emission is the dispenser cathode. For this electron source a reduced brightness of 10⁶ A/m²SrV has been measured, with no restrictions on emission current. With this brightness however it is possible to realize a beam current of 0.3nA (@ 25nm spotsize), which is almost a factor 50 lower than the 13nA that is required for 10 wph. Three methods can be distinguished to increase the throughput: 1. Use an electron source with a 50× higher brightness 2. Increase the number of beams and lenses 50× 3. Patterned beams: Image multiple sub-beams with each projection lens MAPPER has selected option 3) 'Patterned beams' as the method to increase the beam current to 13nA. This because an electron source with a 50x higher brightness is simply not available at this time, and increasing the number of beams and lenses 50× leads to undesirable engineering issues. During the past years MAPPER has been developing the concept of 'Patterned beams'. By imaging 7×7 sub-beams per projection lens the beam current is increased to the required 13nA level. This technique will also be used to maintain throughput at 10 wph for smaller technology nodes by further increasing the number of sub-beams per projection lens. In this paper we will describe the electron optical design used to image these multiple sub-beams per lens, as well as experimental demonstration of this electron optical configuration. Also the writing strategy will be discussed, as well as the first patterning results. One of the key components for 'Patterned beams' is the beam blanker array, since each subbeam must be switched on and off individually. The design of the blanker deflectors, the circuitry, as well as experimental results of the blanker array will be shown. Finally the roadmap to further technology nodes will be discussed.

The ability of fabrication structure in nano-scale with high precise has established technologies like nanoimprinting via hard stamps, where the stamps are usually produced via Electron Beam Lithography (EBL) for applications in the microelectronic industry. On the other hand, nanopatterning with self ordered structures or via holographic patterns provide the basis for large area imprints. In this work we report on a technology for enabling the mass replication of custom-designed and e-beam lithographically prepared structures for pattern transfer into UV curable pre-polymers. The new nano-fabrication technology is based on the concept of Disposal Master Technology (DMT) capable of patterning areas up to 1 x 1 m² and is suitable for mass volume manufacturing of large area arrays of sub-wavelength photonic elements. As an example to show the potential of the application of the new nanoimprint technologies, we choose the fabrication of a photonic crystal (PhC) structure with integrated light coupling devices for low loss interconnection between PhC light wave circuits and optical fiber systems. In experiment we use 260nm of positive resist 950K PMMA for EBL exposure. Resist thickness, exposure dose, development time and parameter for etching have been optimized and a photonic crystal of air-holes in silicon was fabricated, then use this sample as master stamp to fabricate imprinted photonic crystal on UV curable resist.

In this paper the first order analysis of the scatterometry sensitivity up to 45nm HP resin pattern and beyond by using RCWA (Rigorous Coupled Wave-analysis) simulation is described. A criterion, defined as the sum of the absolute difference of the reflectivity values between the nominal and varied conditions thorough the spectrum, is introduced. The criterion of this analysis is a kind of quantification of the sensitivity comparing with 65 nm HP resist pattern of ArF immersion process. Furthermore, the simulated result in this analysis can be used to discuss the extendibility of scatterometry.