This PDF file contains the front matter associated with SPIE Proceedings Volume 7641, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

The semiconductor industry has pursued a rapid pace of technology scaling to achieve an exponential component cost reduction. Over the years the goal of technology scaling has been distilled down to two discrete targets. Process engineers focus on sustaining wafer costs, while manufacturing smaller dimensions whereas design engineers work towards creating newer IC designs that can feed the next generation of electronic products. In doing so, the impact of process choices made by manufacturing community on the design of ICs and vice-versa were conveniently ignored. Hoever, with the lack of cost effective lithography solutions at the forefront, the process and design communities are struggling to minimize IC die costs by following the described traditional scaling practices. In this paper we discuss a framework for quantifying the economic impact of design and process decisions on the overall product by comparing the cost-per-good-die. We discuss the intricacies involved in computing the cost-per-good-die as we make design and technology choices. We also discuss the impact of design and lithography choices for the 32nm and 22nm technology node. The results demonstrate a strong volume dependence on the optimum design style and corresponding lithography and strategy. Most importantly, using this framework process and design engineers can collaborate to define design style and lithography solutions that will lead to continued IC cost scaling.

The 20nm node, with a targeted wiring pitch of 64nm, is the first technology node to dip below the fundamental k1=0.25 resolution limit of high-NA 193nm immersion lithography. Double-patterning has been applied in previous technology nodes to address specific image quality issues such as line-end shortening or poor process window on contacts and vias, but never before has double-patterning been used to form images below the frequency-doubled resolution-limit of optical lithography. This paper describes the design-technology co-optimization efforts exercised by the alliance program for Bulk CMOS technology development at IBM in pursuit of cost-effective double-patterning for the 20nm technology node. The two primary double-patterning contenders, pitch-splitting and sidewall-image-transfer, are reviewed and their unique layout decomposition requirements are contrasted. Double-patterning design enablement solutions and their particular applicability to each step in the design flow are described. The paper closes with a review of the costeffectiveness of current double-patterning solutions, highlighting the important role of design-technology cooptimization in ensuring continued cost-effective semiconductor scaling.

In this paper, we present the challenges of the realization of a large 45nm modern Media Processing SoC with multiple design teams distributed across many countries and time zones. We also describe the complex design methodology deployed to ensure the design is "closable" in the timing and manufacturability domain. Silicon variability impacts both the physical integrity and the parametric performance of the design. Lithography and CMP can cause enough context-dependent systematic variations, requiring exhaustive lithography and CMP physical verification and optimization of the layout. We present the physical and electrical DFM methodology at NXP. We will show how NXP has developed a manufacturing-aware design flow based on early prevention, detection and fixing using a hierarchical approach for model-based lithography checks and model-based CMP checks, from IP level to full-chip. We also present results of variability-aware timing sign-off.

In current and next generation nodes lithography is pushed to low k1 lithography imaging regimes. A gridded design approach with lines and cuts has previously been shown to allow optimizing illuminator conditions for critical layers in logic designs.[1] The approach has shown good pattern fidelity and is expected to be scalable to the 7nm logic node. [2] A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip.[3,4] However, modern SOC's include large amounts of SRAM as well. The proposed approach truly optimizes both, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches. The biggest problem in co-optimizing logic cells and SRAM bit cells is the orientation of critical layers. For SRAMs, the gate and metal1 layers have lines in parallel directions, while in standard cells they are perpendicular. This would require abandoning dipole illumination for the combined optimization, and at best using some form of quadrupole. The alternative is to design the logic and SRAMs to be unified from the beginning. In this case, critical layer orientations as well as pitches could be matched and each of the layers optimized for both functional sets of patterns. Choices of patterns can be made to achieve DSMO (Design-Source-Mask-Optimization). In the 28nm to 22nm logic nodes - with contacted pitches from 110nm to 90nm and metal1 pitches from 90nm to 70nm - one of the questions to answer is when and for which layers double patterning is needed. The limit of single patterning immersion lithography can only be explored through a smart combination of restricted designs and powerful sourcemask optimization tools. In this paper a 28nm SRAM block with bit and word line periphery will be used to look at choices for Design-Source-Mask-Optimization.

It is argued that computational lithography is made tractable by limiting the number of unique layout patterns in the design. The use of regular design fabrics have been proposed and successfully used to create designs by introducing deviations to an underlying regular fabric. However, using a pessimistic optical interaction ranged baded on theoretical calculations has shown that we are not able to sufficiently limit the layout patterns even after using a very regular layout methodology. In this paper we describe a methodology to determine a more realistic optical interaction range for regular design fabrics and apply it to the 32nm technology node to demonstrate that the optical interaction range can be limited to 2-3 pitches as compared to 10 pitches based on a pessimistic theoretical estimation. We discuss results that demonstrate that layouts created using templates on a regular design fabric enable sufficient pattern control for deterministic source mask optimization (SMO). We also discuss the methodology for classifying patterns into equivalent pattern classes to reduce the total number of patterns required for process characterization.

Gridded Design Rules (GDR) in combination with lines/ cuts double patterning allow imaging of 16nm designs with 193nm immersion lithography. Highly regular lines/ cut patterns result in the existence of a well-defined optimal set of lithographic conditions. Since cuts are all of identical shape and relatively sparse, good image quality can be obtained with minimal or simplified pattern correction (OPC equivalent) to compensate for proximity effects. The use of local interconnect (LI) is shown to offer further reduction of the required number of cuts and improves pattern uniformity and image quality. Critical cut patterns of poly and M1 layers in selected worst case standard GDR cells were considered. Simultaneous co-optimization of cut geometry as well as lithographic conditions such as scanner entrance pupil illumination was used to bring all cuts within ~1nm of target CDs at best focus. Optimized conditions significantly reduced the sensitivity of printed patterns to proximity effects. Manufacturability was verified using DOF and NILS metrics before and after co-optimization. Experimental lens entrance pupil illumination and lens aberrations including polarization effects were included in the analysis.

With the delay of a next-node lithography solution, lithographers are required to evaluate double patterning techniques such as double pattern/double etch (DP/DE) to meet scaling targets for the 22nm logic node. The tightest design rule level to pattern has traditionally been the first metal level. For this node, target minimum pitches are below 32 nm half pitch in order to meet cell area requirements. In this paper, we explore implications of the DP/DE approach when applied to complex 2D metal patterns. In addition to evaluating stitching rules for line ends, we move into complicated patterning structures such as landing pads neighboring metal runners and arrays of dense landing pads. These feature types are critical for area scaling; however, when these structures are patterned in a DP/DE scheme, the minimum area of the features needed for each pattern layer can be quite small. In this work, we explore minimum area rules for stitching together patterns as function of overlap with first pattern, minimum area and proximity to unrelated trench features on the same pattern. These results are shown thru simulation and on the wafer scale using a DP/DE approach which uses current 28 nm node imaging techniques.

In this paper we will demonstrate how a 3D physical patterning model can act as a forensic tool for OPC and ground-rule development. We discuss examples where the 2D modeling shows no issues in printing gate lines but 3D modeling shows severe resist loss in the middle. In absence of corrective measure, there is a high likelihood of line discontinuity post etch. Such early insight into process limitations of prospective ground rules can be invaluable for early technology development. We will also demonstrate how the root cause of broken poly-line after etch could be traced to resist necking in the region of STI step with the help of 3D models. We discuss different cases of metal and contact layouts where 3D modeling gives an early insight in to technology limitations. In addition such a 3D physical model could be used for early resist evaluation and selection for required ground-rule challenges, which can substantially reduce the cycle time for process development.

In this paper, we have presented an effective yield improvement methodology that can help both manufacturing foundries, fabless and fab-lite companies to identify systematic failures. It uses the physical addresses of failing bits from wafer sort results to overlay to inline wafer defect inspection locations. The inline defect patterns or the design patterns where overlay results showed matches were extracted and grouped by feature similarity or cell names. The potentially problematic design patterns can be obtained and used for design debug and process improvement.

Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state-of-the-art lithography process; meanwhile, the design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depend on contact area and shape, larger CER results in significant change in a device current. In this paper, we first propose a CER model based on power spectral density function which is a function of RMS edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress induced CMOS cells. Using the results of CER, we analyze the impact of CER variation on the S/D contact resistance and the device saturation current. Results show that when the rms value of CER is 10nm, the S/D contact resistance and the device saturation current can vary by as much as 57.8% and 2.1%, respectively.

Layout sizing in the mask preparation step is commonly used on critical layers to improve printing process windows. The current flow of yield calculation based on critical areas of a layout typically does not take into account this sizing step. In this paper, we propose a new and simple flow that accounts for the sizing to improve the accuracy of yield calculation. We compare the calculated results using the current and sizing-aware flow to demonstrate the differences. We also show that results from the sizing-aware flow better match the calculated circuit switching power, which already takes into account this sizing step.

With process technologies advancing to 65nm, 45nm, and below, device timing uncertainty due to lithography and other process variations has easily exceeded 50% and is still growing. In this paper, we present the development of a variability methodology, its correlation with silicon and application to cell and full-chip design verification and optimization. We describe both a methodology for variability analysis of standard cells and a full-chip screening methodology to identify potential chip variability excursions. This methodology relies on model-based analysis and integrates with our existing design-to-manufacturing flow. Based on silicon measurement data of one of our 65nm cell libraries, this methodology has achieved significant improvement in accuracy of estimating timing variations compared to a traditional rule-based method.

We have previously analyzed spatial process variation using 45nm ring oscillator arrays. Our hierarchical variability model had proven to be very useful in revealing interesting systematic patterns, and in separating them from native random variability. To further understand the underlying mechanism of the process variation, we continue to work on the analysis and modeling of spatial variation of transistors made on the same 45nm technology test chips. A novel statistical compact device modeling procedure is used to extract the systematic and random variation of device parameters across wafer and within die. Statistical SPICE simulation is then performed based on the extracted variation model of device parameters. The results compare well with actual ring oscillator and SRAM measurements, in that the characteristic systematic, spatial and random patterns have been captured for circuit-level simulation.

Standard cell timing variations are caused by process non-idealities that are not traditionally captured within standard timing characterization tools. This paper presents two approaches to creating variability aware standard cell timing models in the presence of lithographic variations. The first approach uses circuit simulation of rectangular transistors to create delay sensitivity tables to transistor length and transistor width for each cell. The second approach utilizes lithography contours to characterize cell performance. The contour based approach is used to characterize two standard cells in the presence of active and poly layer focus exposure variations, misalignment, and layout proximity effects. The delay response to focus and exposure exhibits Bossung-like delay behavior and can be fit with a compact parameter delay model. Both approaches lead to the creation of variability aware timing models in the form of delay variability tables or compact parameter timing models. These models enable static timing analysis tools to perform critical path variability aware delay analysis using a presumed layout-dependent distribution of process parameters with little expense in runtime.

Process window (PW) is a collection of values of process parameters that allow circuit to be printed and to operate under desired specifications. Conventional process window which is determined through geometrical fidelity, geometric process window (GPW), does not account for lithography effects on electrical metrics such as delay and power. In contrast to GPW, this paper introduces electrical process window (EPW) which accounts for electrical specifications. Process parameters are considered within EPW if the performance (delay and leakage power) of printed circuit is within desired specifications. Our experiment results show that the area of EPW is 1.5~6x larger than that of GPW. This implies that even if a layout falls outside geometric tolerance, the electrical performance of the circuit may satisfy desired specifications. In addition to process window evaluation, we show that EPW can be enlarged by 10% on average using gate length biasing and Vth push. We also propose approximate methods to evaluate EPW, which can be used in the absence of any design information. Our results show that the proposed approximation method can estimate more than 80% of the area of reference EPW.

The cost of photomasks has been rising year by year as the process node gets finer and the mask cost is becoming one of the headaches in the semiconductor industry. For the purpose of the mask cost reduction, ASET started Mask D2I (Mask Design, Drawing and Inspection Technology) project in 2006. In earlier papers[1-4], we introduced the idea of photomask data prioritization method which is referred to as Mask Data Rank (MDR). We have built our software system to convert Design Intent (DI) to MDR with cooperation of STARC. Then we showed the results of preliminary experiments with mask data provided by STARC. In this paper we explain the software mechanism of design intent extraction flow. Then we show the experimental results with actual chip data in three semiconductor companies and address the related issues. Finally we introduce a new idea to extract design intent from analog circuits.

Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step. Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully considered. Electrical behavior is carefully verified in both cell and chip design phases with respect to timing, IR drop, signal integrity, crosstalk, etc., using various electronic design automation (EDA) tools. However, once the design data is converted to layout data and signed off, most of the design intention is abandoned and unrecognized in the process phase. Thus, instead of essential tolerance according to layout-related design intention, uniform and redundant tolerance is used, and therefore excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intention has been discussed. In this paper, a test flow is developed and application to 45nm node test chip is examined.

Experimental results are reported for ring oscillators (ROs) fabricated using 45nm generation CMOS technology and inverter layouts that are designed to identify and quantify sources of circuit performance variation due to gate etch/lithography, gate-to-active misalignment, and CESL-induced stress. The measured RO frequency data show that within-chip variation is negligible in comparison with chip-to-chip variation. Standard-deviation over mean (σ/μ) values among 36 RO instances show a slight channel area dependence of 0.2% versus sqrt(area)^-1. For a typical wafer, 3% RO frequency change due to gate etch/focus variations, 2-3nm overlay error, and a 5% increase by doubling the length of diffusion (LOD) can be measured.

A layout design that passes the design rule check (DRC) may still have manufacturing problems today, especially around areas of critical patterns. Thus a design-for-manufacturability (DfM) model, which can simulate the process from designed layout to wafer and predict the final contours, is necessary. A new kind of DfM model called free-elementmodel (FEM) is proposed in this paper. The framework of FEM is borrowed from the forward process model, which is basically a set of convolution kernels in matrix form, yet the unknown variables are the kernel elements instead of process parameters. The modeling process is transformed into a non-linear optimization problem, with equality constraints which involve norm-2 regulation of kernels and inner production of any two kernels to keep the normalization and orthogonality of optimized kernels. Gradient-based method with Lagrange penalty function is explored to solve the optimization problem to minimize the difference between simulated contours and real contours. The dimension of kernels in FEM is determined by the cutoff frequency and the ambit. Since kernels are calculated by optimization method instead of decomposition of transmission cross coefficient (TCC), every element of kernels becomes a factor to describe the process. FEM is more flexible, and in it all effects that can be integrated into convolution kernels join naturally, such as the resist deviation and asymmetry of the process. No confidential process parameters, for example NA and defocus, appear in FEM explicitly, and thus the encapsulated FEM is suitable for IC manufacturers to publish. Moreover, enhancements and supplements to FEM are discussed in this paper, including the sufficiency of test patterns. In our experiments, DfM models for 2 process lines are generated based on test patterns, and the results show that the simulated shapes have an area error less than 2% compared to the real shapes of test patterns and an area error less than 3% compared to the shapes in typical blocks chosen from chip for verification purpose. The root mean square error of contour deviation between the 2 simulation results from FEM and conventional lithographic model is 10nm in a 65nm process.

As interconnect densities increase with each technology generation, the lithographic processes required to print all features with acceptable irregularities have become more complex. Restricted design rules (RDR) and modelbased Design for Manufacturability (DFM) guidelines have been added to the existing Design Rule Check (DRC) software to prevent unprintable patterns to be drawn on the mask by predicting their imprint on the wafer. It is evident from analyses of predicted patterns that edge placement errors have a continuous distribution, hence a pass/fail cut-off is somewhat arbitrary. In this paper, we describe a methodology to perform Statistical Lithography Rules Check (Stat-LRC) involving design yield based on interconnect linewidth distribution for variation in lithographic input error sources. In this scheme, a list of error locations indicating polygons that have yield below a user specified threshold are listed. The overall design yield is recovered by trading-off slightly poorer EPE distributions for lines with short runs with excellent ones. The simulation/analysis environment is fully automated and yield recovery improvement has been demonstrated.

As technology processes continue to shrink, standard design rule checking (DRC) has become insufficient to guarantee design manufacturability. DRCPlus is a powerful technique for capturing yield detractors related to complex 2D situations1,2. DRCPlus is a pattern-based 2D design rule check beyond traditional width and space DRC that can identify problematic 2D configurations which are difficult to manufacture. This paper describes a new approach for applying DRCPlus in a router, enabling an automated approach to detecting and fixing known lithography hotspots using an integrated fast 2D pattern matching engine. A simple pass/no-pass criterion associated with each pattern offers designers guidance on how to fix these problematic patterns. Since it does not rely on compute intensive simulations, DRCPlus can be applied on fairly large design blocks and enforced in conjunction with standard DRC in the early stages of the design flow. By embedding this capability into the router, 2D yield detractors can be identified and fixed by designers in a push-button manner without losing design connectivity. More robust designs can be achieved and the impact on parasitics can be easily assessed. This paper will describe a flow using a fast 2D pattern matching engine integrated into the router in order to enforce DRCPlus rules. An integrated approach allows for rapid identification of hotspot patterns and, more importantly, allows for rapid fixing and verification of these hotspots by a tool that understands design intent and constraints. The overall flow is illustrated in Figure 1. An inexact search pattern is passed to the integrated pattern matcher. The match locations are filtered by the router through application of a DRC constraint (typically a recommended rule). Matches that fail this constraint are automatically fixed by the router, with the modified regions incrementally re-checked to ensure no additional DRCPlus violations are introduced.

The concept of template-based design-technology co-optimization as a means of curbing escalating design complexity and increasing technology qualification risk is described. Data is presented highlighting the design efficacy of this proposal in terms of power, performance, and area benefits, quantifying the specific contributions of complex logic gates in this design optimization. Experimental results from 32nm technology node bulk CMOS wafers are presented to quantify the variability and design-margin reductions as well as yield and manufacturability improvements achievable with the proposed template-based design-technology co-optimization technique. The paper closes with data showing the predictable composability of individual templates, demonstrating a fundamental requirement of this proposal.

Intel has reported on three separate styles and applications of strong phase shift masks (PSMs) over the last decade including alt-PSM for gate patterning, alt-PSM with assist features for contact patterning and Pixelated Phase Masks (PPMs) for metal layer patterning. Each had a prominent role in Intel's Design For Manufacturing (DFM) infrastructure development in terms of design rules and DFM tooling. By gradually inserting design rule changes for alt-PSM for gate patterning starting from the 130nm technology node, density and design impact were minimally effected. Alt-PSM for contact layer required development of complex methods of SRAF placement and coloring while also forcing advances in phase shift mask manufacturing infrastructure. Pixelated phase masks for metal patterning when combined with Inverse Lithography Techniques (ILTs) were successful in supporting a high level of flexibility for metal design rules including multiple feature sizes, pitches and two-dimension content.

Spacer technology, a self-aligned double patterning (SADP) technique, has been drawing more and more attention due to its less stringent overlay requirements compared to other double-patterning methods. However, use of SADP techniques was previously limited by the lack of flexibility in terms of decomposition options , and significant developments were mainly implemented for 1D-type applications for memory. In this paper, we extend the SADP technique into the logic field. A matrix of design rule extraction structures was created by GLOBALFOUNDRIES, which was then decomposed into 2-mask SADP patterning solutions by Cadence Design Systems, and wafers were manufactured by Applied Materials. The wafers were processed in both positive and negative spacer tones, and then we evaluate the design capabilities of SADP for logic BEOL patterning on pitches from 56nm to 64nm. It shows that the SADP has big advantage over other pitch splitting techniques such as LELE in terms of design rules, overlay, and CD uniformity control. With SADP, the most challenging design rules for BEOL such as tip-to-tip and tip-to-line can be reduced 50% from 80 nm to 40 nm.

Just as the simulation of photolithography has enabled resolution-enhancement through Optical Proximity Correction, the physical simulation of nanoimprint lithography is needed to guide the design of products that will use this process. We present an extremely fast method for simulating thermal nanoimprint lithography. The technique encapsulates the resist's mechanical behavior using an analytical function for its surface deformation when loaded at a single location. It takes a discretized stamp design and finds resist and stamp deflections in a series of steps. We further accelerate the simulation of feature-rich patterns by pre-computing dimensionless relationships between the applied pressure, the resist's mechanical properties, and the residual layer thickness, for stamps patterned with uniform arrays of a variety of common feature shapes. The approach is fast enough to be used iteratively when selecting processing parameters and refining layouts. The approach is demonstrated in action with three nanoimprint test-patterns, and describes experimentally measured residual layer thickness variations to within 10-15% or better. Finally, our technique is used to propose nanoimprint-aware design rules.

An accurate model for the self-stop copper chemical mechanical polishing (Cu-CMP) process has been developed using CMP modeling technology from Mentor Graphics. This technology was applied on data from Sony to create and optimize copper electroplating (ECD), Cu-CMP, and barrier metal polishing (BM-CMP) process models. These models take into account layout pattern dependency, long range diffusion and planarization effects, as well as microloading from local pattern density. The developed ECD model accurately predicted erosion and dishing over the entire range of width and space combinations present on the test chip. Then, the results of the ECD model were used as an initial structure to model the Cu-CMP step. Subsequently, the result of Cu-CMP was used for the BM-CMP model creation. The created model was successful in reproducing the measured data, including trends for a broad range of metal width and densities. Its robustness is demonstrated by the fact that it gives acceptable prediction of final copper thickness data although the calibration data included noise from line scan measurements. Accuracy of the Cu-CMP model has a great impact on the prediction results for BM-CMP. This is a critical feature for the modeling of high precision CMP such as self-stop Cu-CMP. Finally, the developed model could successfully extract planarity hotspots that helped identify potential problems in production chips before they were manufactured. The output thickness values of metal and dielectric can be used to drive layout enhancement tools and improve the accuracy of timing analysis.

In this paper, we present a dummy metal fill method based on co-optimization of both ECP and CMP processes. We present the layout dependent, minimum variance algorithm that matches not only metal densities across two-dimensional tiles of layout, but also the perimeters and shapes of metal lines in each tile. Using co-optimization as the fill criterion, our algorithm effectively minimizes the metal height differences as verified by model based CMP simulations. In addition, it also renders pre-characterization of fill constraints with respect to timing and signal integrity assurance. We also show our silicon data measured on a 65nm process that sufficiently provide proof of the method.

Conventional geometrical EPE-based OPC approach often results in complicated mask and requires expensive computational effort. To address the mask complexity issue, a device performance-based OPC (DPB-OPC) algorithm which operates based on parametric current, rather than desired layout pattern as in conventional OPC, has been proposed to achieve considerable mask data saving. However, the performance gain is currently limited by the comparatively longer run-time. To improve run-time efficiency of the previous work, we present a library-based DPBOPC methodology in the paper. In particular, cell-wise OPC concept is deployed to explore its merit of run-time saving. To counteract the performance degradation shift that caused by different surrounding environment, a localized DPBOPC refinement can be selectively performed. When compared to full chip OPC, substantial run-time reduction is achieved in the benchmark design.

For mature technology nodes, main yield detractor is random defectivity. Nevertheless, some devices can show higher defectivity than rest of devices. Out of process accident, design related defect is one of suspected root cause. Also, design-based defect category is expected to increase as technology node decreases. Determining origin of these additional systematic defects is not easy as these defects are usually residual for technologies in production, not always predictable by OPC simulator (ex: void defect in active STI structure), and at least hidden by random defectivity after in-line wafer inspection control. In this paper, an automatic flow to track systematic defects within global defectivity is presented. This flow starts with a relevant selection of several inspection defect files for a given device. Then the Design Based Binning (DBB) tool performs a fine alignment of the whole multi wafer inspection data set with design file. The resulting aligned defect file is treated by an efficient pattern matching algorithm to generate a design-based binning (DBB) defect file. The integration of this output defect file into a Yield Management System (YMS) allows easy defect analysis and statistical correlation to electrical results. An example of design-based defects tracking analysis and their impact on yield of a mature technology node device is presented in this paper.

A simple methodology to predict transistors performances due to systematic lithography and etch effects is presented. It is based on physical silicon simulation, followed by device modeling, incorporated in the silicon simulation software. This method enables an easy and efficient analysis of device parameters with the same simulation tool usually used for process analysis. The method is demonstrated on small and large arrays of standard cell blocks, designed for TS013SL (0.13μm Standard Logic for General Purposes) Platform. Electrical parameters, like drive current (Idsat), and Off current (Ioff) were predicted. Comparison between different transistors types, having the same W/L but different layout configuration and various layout environments (around the transistor) was made in terms of performances as well as process variability.

Semiconductor foundries at 65nm, 45nm, and more advanced technologies have witnessed high-yield mass production to be intimately correlated to the practice of adaptive DFM (Design for Manufacturability). With device performance variance easily exceeding 50% for 65nm and below, adaptive actions by designers, such as modifying layouts to relieve potential DFM risks, is found to be a very efficient approach to high yield manufacturing. Rigorous MEEF estimation based methods have been proposed to achieve adaptive DFM by predicting mask writing variations at early stages (cell/block levels) of designs. In a recent study, we discovered that by adding MEEF check in simulation contour based OPC verification flow, and by comparing MEEF changes of pre and post OPC hotspots, it is possible to separate OPC issues from design issues, in particular, for hotspot patterns with tight spaces with little room for any biases. We found that hotspot patterns with tight spaces usually create OPC conflict edges-correcting one edge will result in increasing MEEF at other edge, or vice versa. While advancement in OPC technology continues to improve MEEF performance, nevertheless OPC-conflicting edges almost always exist in designs at 65nm and below. In this paper, we first demonstrate the existence of OPC conflict edge hotspots using MEEF analysis. In particular, the increase of MEEF after OPC on those edges indicates that they have smaller process window than pre-OPC ones. In certain cases, design modification is necessary to correct such OPC conflicting edges. Based on the finding, we propose a practical methodology of detecting design related OPC edge conflicting hotspots in a pattern centric software-based DFM (design for manufacturability) flow. The methodology is aiming to detect patterns containing such conflicting edges, and pursuing layout actions on the design side to eliminate this issue. We will validate the flow using a real design case. In addition, the OPC edge conflicting hotspots can be clipped and saved in a designated pattern library as hotspot templates, and incoming designs can be quickly screened using exact and similar pattern search with those saved templates in the library.

In May 2006, the Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) at the Association of Super-Advanced Electronics Technologies (ASET) launched a 4-year program for reducing mask manufacturing cost and TAT by concurrent optimization of MDP, mask writing, and mask inspection. As one of the tasks being pursued at the Mask Design Data Technology Research Laboratory, we have evaluated the effect of reducing the drawing shot counts by utilizing the repeating patterns, and showed positive impact on mask making by using CP drawing. During the past four years, we have developed a software to extract repeating patterns from fractured OPCed mask data which can be used to minimize the shot counts. In this evaluation, we have used an actual device production data obtained from the member companies of MaskD2I. To the extraction software we added new functions for extracting common repeating patterns from a set of multiple masks, and studied how this step can reduce the counts in comparison to the shot counts required during the conventional mask writing techniques. We have also developed software that uses the extraction result of repeating patterns and prepares drawing-data for the MCC/CP drawing system, which has been developed at the Mask Writing Equipment Technology Research Laboratory. With this software, we have simulated EB proximity effect on CP writing and examined how it affect the shot count reduction where CP shots with large CD errors are to be divided into VSB shots. In this paper, we will report the evaluation result of the practical application of repeating patterns in mask writing with this software.

Design for Manufacturability (DFM) involves changes to the design and CAD tools to help increase pattern printability and improve process control. Design for Reliability (DFR) performs the same to improve reliability of devices from failures such as Electromigration (EM), gate-oxide break down, hot carrier injection (HCI), Negative Bias Temperature Insatiability (NBTI) and mechanical stress effects. Electromigration (EM) occurs due to migration or displacement of atoms as a result of the movement of electrons through a conducting medium. The rate of migration determines the Mean Time to Failure (MTTF) which is modeled as a function of temperature and current density. The model itself is calibrated through failure analysis (FA) of parts that are deemed to have failed due to EM against design parameters such as linewidth. Reliability Verification (RV) of a design involves verifying that every conducting line in a design meets certain MTTF threshold. In order to perform RV, current density for each wire must be computed. Current itself is a function of the parasitics that are determined through RC extraction. The standard practice is to perform the RC extraction and current density calculation on drawn, pre-OPC layouts. If a wire fails to meet threshold for MTTF, it may be resized. Subsequently, mask preparation steps such as OPC and PSM introduce extra features such as SRAFs, jogs,hammerheads and serifs that change their resistance, capacitance and current density values. Hence, calibrating EM model based on pre-OPC layouts will lead to different results compared to post-OPC layouts. In this work, we compare EM model calibration and reliability check based on drawn layout versus predicted layout, where the drawn layout is pre-OPC layout and predicted layout is based on litho simulation of post-OPC layout. Results show significant divergence between these two approaches, making a case for methodology based on predicted layout.

A computational lithography solution addressing accuracy, speed and affordability requirements is presented. In particular, the cost of computational hardware should be affordable and that the speed and accuracy of the algorithm should be sufficient to complete a full-chip computation overnight. Given the issues associated with present tools, the presented solution uses graphic processors (GPUs) as well as CPUs as computation hardware to achieve a breakthrough improvement in speed and affordability. Scalability to large scale clusters has been addressed so that the solution can be simultaneously used by chip designers as well as manufacturers to provide consistency.

An inverse lithography solution based on optimization is presented. The optimization approach, in effect, operates as an inverse lithography tool, based on modeling and simulation of the manufacturing process. Given the associated computational requirements, the proposed solution intentionally uses graphic processors (GPUs) as well as CPUs as computation hardware. Due to the approach we employed, the results are optimized towards manufacturability and process window maximization.

The role of the gate width in the effects of Line Width Roughness (LWR) on transistor performance is investigated. Two mathematical results regarding the statistical nature of LWR are presented and discussed. The implications of these results on the effects of LWR on transistor performance are investigated through a 2D modeling approach. It is found that, for fixed LWR induced by manufacturing processes, transistors designed with large gate widths seem to mitigate the degradation effects of LWR on transistor performance.