Layout pattern minimization for next-generation technologies

Tejas Jhaveri; Andrzej J. Strojwas

doi:10.1117/12.846367

2 April 2010 Layout pattern minimization for next-generation technologies

Tejas Jhaveri, Andrzej J. Strojwas

Proceedings Volume 7641, Design for Manufacturability through Design-Process Integration IV; 764108 (2010) https://doi.org/10.1117/12.846367
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

It is argued that computational lithography is made tractable by limiting the number of unique layout patterns in the design. The use of regular design fabrics have been proposed and successfully used to create designs by introducing deviations to an underlying regular fabric. However, using a pessimistic optical interaction ranged baded on theoretical calculations has shown that we are not able to sufficiently limit the layout patterns even after using a very regular layout methodology. In this paper we describe a methodology to determine a more realistic optical interaction range for regular design fabrics and apply it to the 32nm technology node to demonstrate that the optical interaction range can be limited to 2-3 pitches as compared to 10 pitches based on a pessimistic theoretical estimation. We discuss results that demonstrate that layouts created using templates on a regular design fabric enable sufficient pattern control for deterministic source mask optimization (SMO). We also discuss the methodology for classifying patterns into equivalent pattern classes to reduce the total number of patterns required for process characterization.

Citation Download Citation

Tejas Jhaveri and Andrzej J. Strojwas "Layout pattern minimization for next-generation technologies", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 764108 (2 April 2010); https://doi.org/10.1117/12.846367

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