This PDF file contains the front matter associated with SPIE Proceedings Volume 7985, including the Title Page, Copyright information, Table of Contents, Foreword, Sponsor Page, and Conference Committee listing.

Microelectronics industry leaders consistently cite the cost and cycle time of mask technology and mask supply as top critical issues. A survey was designed with input from semiconductor company mask technologists and merchant mask suppliers and support from SEMATECH to gather information about the mask industry as an objective assessment of its overall condition. This year's assessment was the ninth in the current series of annual reports. Its data were presented in detail at BACUS, and the detailed trend analysis is presented at EMLC. With continued industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. Results will be used to guide future investments in critical path issues. This year's survey is basically the same as the 2005 through 2010 surveys. Questions are grouped into six categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services. Within each category are multiple questions that ultimately create a detailed profile of both the business and technical status of the critical mask industry.

We propose changing the shot pattern between passes in multi-pass vector e-beam writing in order to reduce total shot count. One pass is detailed while the other is simplified. Mask process correction is used to produce the correct image from the sum of the exposures; a fundamental contstraint is enforced to retain process latitude. Results from a software implementation show a total shot savings in the range of 18 to 31 percent for two-pass writing versus the conventional writing scheme in which each pass writes identical shot sets. Simulation results demonstrate the feasibility of the technique.

Multi Shaped Beam (MSB) throughput simulation results have already been published in the past. An IC mask set of a 32nm node logic device was one of the applications that had been analyzed in more detail. In this paper we want to highlight results of shot count and write time evaluations done for Inverse Lithography Technology (ILT) masks targeting the 22nm technology node. The test pattern data we used for these practice-oriented analyses was designed by DNP / Japan and created by Luminescent Technologies, Inc. / USA. To achieve reliable evaluation results, the influence of different MSB configurations on shot count and mask write time has been taken into account and will be discussed here. Exposure results of pattern details are presented and compared with the fracturing result. The MSB engineering tool we used for our investigations covers such major components like an electron-optical column, a precision x/y stage and the MSB data path.

Semiconductor lithography candidates toward 2xnm node and beyond include wide variety of options, such as extension of 193i, EUVL, NIL, and ML2. Most of those candidates, except ML2, need critical mask feature to realize effective high volume manufacturing. In this presentation, EUVL mask technology update and future issues will be presented.

During hybrid lithography of thermal nanoimprint with optical lithography, where both steps are performed within one single resist layer, changes of the lithographic performance of the material used during the first step, the thermal imprint, are essential for the overall lithography result. In order to characterize such changes two positive tone photoresists, AZ-1505 and ARP- 3510, were characterized by measurement of dose curves (relative resist layer thickness remaining after exposure and development) after a specific temperature treatment simulating the thermal imprint step. Obviously the two materials are affected in a somewhat different way. After temperature treatment at 120°C, ARP-3510 still features a higher sensitivity than AZ-1505, but the latter shows a higher contrast.

Chip manufacturing with multilayer reticles offers the possibility to reduce reticle cost at the expense of scanner throughput, and is therefore an attractive option for small-volume production and test chips. Since 2010, GLOBALFOUNDRIES Fab 1 uses this option for the 28nm IP shuttles and test chips offered to their customers for development and advance testing of their products. This paper discusses the advantages and challenges of this approach and the practical experience gained during implementation. One issue that must be considered is the influence of the small image field and the asymmetric reticle illumination on the lithographic key parameters, namely layer to layer overlay. Theoretical considerations and experimental data concerning the effects of lens distortion, lens heating, and reticle heating on overlay performance are presented, and concepts to address the specific challenges of multilayer reticles for high-end chip production are discussed.

This paper presents a backside-to-frontside alignment technique for the backside processing of Si wafers. Integrated MEMS components like BiCMOS-embedded RF-MEMS switches require accurate (1-2μm) alignment. We demonstrate an alignment technique providing overlay values of less than 500 nm by using a backside alignment layer. The approach is enabled by a new non-contact wafer pre-alignment system of the Nikon Scanner S207D allowing precise loading (<5μm) of the wafer onto the exposure stage. Before starting the back-side MEMS process, the misalignment between frontside devices and backside alignment layer has to be measured. The alignment errors are applied as lithography overlay corrections to the backside MEMS process. For the specific application of deep Si etching (Bosch process), moreover, one has to consider the etch profile angle deviation across the wafer (tilting), which turned out in our experiments to amount up to 8 μm. During initial experiments with a Nikon i-line stepper NSR-2205 i- 11D the overlay has been corrected by the stepper offset parameters. These parameters have been obtained by summing up both the wafer and intra-field scaling errors caused by deep Si etching and backside-to-frontside alignment errors. Misalignments and tilting errors were all measured with a MueTec MT 3000 IR optical metrology system using overlay marks. The developed alignment technique is applied to BiCMOS-embedded MEMS devices, i.e. mm-wave RF switches and a viscosity sensor chip based on the IHP's high-speed SiGe technology. It turned out to be very promising for backside processed MEMS components with critical alignment requirements.

As commercialization of extreme ultraviolet lithography (EUVL) progresses, direct industry activities are being focused on near term concerns. The question of long term extendibility of EUVL, however, remains crucial given the magnitude of the investments yet required to make EUVL a reality. Extendibility questions are best addressed using advanced research tools such as the SEMATECH Berkeley microfield exposure tool (MET) and actinic inspection tool (AIT). Utilizing Lawrence Berkeley National Laboratory's Advanced Light Source facility as the light source, these tools benefit from the unique properties of synchrotron light enabling research at nodes generations ahead of what is possible with commercial tools. The MET for example uses extremely bright undulator radiation to enable a lossless fully programmable coherence illuminator. Using such a system, resolution enhancing illuminations achieving k1 factors of 0.25 can readily be attained. Given the MET numerical aperture of 0.3, this translates to an ultimate resolution capability of 12 nm. Using such methods, the SEMATECH Berkeley MET has demonstrated resolution in resist to 16-nm half pitch and below in an imageable spin-on hard mask. At a half pitch of 16 nm, this material achieves a line-edge roughness of 2 nm with a correlation length of 6 nm. These new results demonstrate that the observed stall in ultimate resolution progress in chemically amplified resists is a materials issue rather than a tool limitation. With a resolution limit of 20-22 nm, the CAR champion from 2008 remains as the highest performing CAR tested to date. To enable continued advanced learning in EUV resists, SEMATECH has initiated a plan to implement a 0.5 NA microfield tool at the Advanced Light Source synchrotron facility. This tool will be capable of printing down to 8-nm half pitch.

Defect-free reticle availability has consistently been among the top two challenges in implementing EUV high volume manufacturing (HVM) in 2013. This paper will provide an updated industry survey of EUV mask readiness and challenges for the 22 nm half-pitch and beyond. Device makers, exposure and inspection equipment suppliers, mask makers, and blank suppliers submitted responses to the survey. Focus areas were EUV mask readiness for pilot line DRAM in 2011, DRAM HVM in 2013, and logic pilot line in 2013. The paper will also provide updates on various key technology areas including defect reduction activities in multilayer deposition; challenges and progress in blank and mask cleans, mask handling, and storage; and key inspection infrastructure progress to support EUV HVM implementation.

There is a strong demand for standalone actinic tools for mask blank and mask metrology. We expect to deliver contributions to key issues for the infrastructure tools such as actinic reflectometer, actinic defect inspection and components like high brightness sources together with our partners. With our EUV-reflectometer EUV-MBR we are ready to fulfill HVM requirements in accurate and sensitive spectral metrology. Migrating from mask blanks to masks is supported with integrated fiducial mark detection and small spot sizes of down to < 0.03 mm². Hence, the EUV-MBR is able to detect minimal variations on mask blank and can support process monitoring for our partners in European EXEPT project. For actinic blank inspection a proof of concept experiment based on an EUV microscope at BASC's EUV-Lamp allows for comparing actinic signatures with AFM scans. Results allow for extrapolation to sub 30 nm sensitivity and fast full blank scan. For LPP sources we demonstrated a new concept utilizing a laser, with parameters optimized for high brightness EUV generation and a new regenerative target concept for high position stability, gain, repetition rate operation and efficiency in the first proof of concept experiment. Up to 350 W/(mm² sr) from < 20 μm source size have been demonstrated.

One of the most challenging requirements for the next generation EUV lithography is an extremely low amount of critically sized defects on mask blanks. Fast and reliable inspection of mask blanks is still a challenge. Here we present the current status of the development of our actinic Schwarzschild objective based microscope operating in dark field with EUV discharge produced plasma source. For characterization of the microscope performance, several programmed defect structures - artificial pits and bumps were created on top of multilayer mirror (ML) surfaces and investigated both with EUV microscope and atomic force microscope (AFM). Defect size sensitivity of actinic inspection in dark field mode without resolving the defects is under study. The dependency between defect shape, size and position in relation to the ML surface and its scattering signal will be discussed. Furthermore, first results of a defect mapping algorithm are presented.

The image placement is and remains an important aspect of photomask metrology. Not only the position accuracy of features for an individual mask - representing one layer in a complete chip design have to meet stringent requirements, the complete mask set for all layers have to match in order to get a functional device. At a time were registration and overlay errors were counted in micrometer it was enough to compare one mask with another by a so called overlay machine. This approach works sufficiently until placement specification reached the "nanometre range" and the development of dedicated 2D coordinate measurement systems became necessary. Since then, pattern placement metrology tools became "enabler" for the continuous improvement of pattern placement accuracy on photomask and the improvement of the final wafer overlay error. This paper reviews and discuss current trends of pattern placement metrology on photomasks, highlighting the major error drivers and will focus on current and future requirements for in - die registration.

The new photomask registration and overlay metrology system PROVE^TM at Carl Zeiss has been developed and already delivered to customers to meet the increased industry requirements for pattern registration tools in terms of resolution and in-die measurement capability. Main drivers of the tool performance specifications are double exposure and double patterning approaches which will help to extend the 193nm lithography platforms while keeping the semiconductor industry conform to ITRS roadmap requirements. To guarantee the demanding tool performance, PROVE^TM features highly stable hardware components for the stage and environmental control. Moreover, sophisticated image analysis algorithms as for instance correlation methods have been developed to overcome limitations of standard approaches. In this paper we focus on mask-to-mask overlay metrology as one of the critical components of modern lithography. To achieve the challenging requirements with the PROVE^TM tool, an overlay reproducibility budget is prepared that takes into account stage, image analysis and global effects like mask loading and environmental control. The corresponding parts of the budget are quantified by means of PROVE^TM overlay measurements, performed on typical box-in-frame structures. This allows the identification of critical error contributions and the corresponding improvement strategies. In particular, it will be shown, that the new developed correlation methods of PROVE^TM will significantly reduce image analysis and camera noise contributions.

Wafer overlay requirement for the 32nm HP node for DRAM volume production is targeted at 6.4nm (single exposure) in 2013. Consequently, this is placing a significantly tighter demand on the pattern placement accuracy on photomasks: at or below 3.8nm (3sigma). In case Double Patterning Lithography (DPL) becomes the manufacturing technique for 32nm and 22nm node devices, the pattern placement specification of dependent layers is less than 3nm, according to the ITRS roadmap. In addition to photomask lithography pattern placement instability, the distortion influence of the pellicle on plate bending is also an error contributor especially when the pellicle distortions are not repeatable substrate to substrate. The combination of increased demand for greater accuracy and the influence of pellicle distortions are key factors in the need for high resolution through-pellicle in-die measurements based on actual device features. A new registration metrology tool dedicated for the 32nm HP node and beyond is under beta testing. Actual status and performance data of the beta evaluation system is provided to verify registration metrology capability for DPL reticle manufacturing; to characterize the reticle contribution to total wafer overlay error; and help keep such error within the required tolerances.

Scatterometry is a common technique for the characterization of nano-structured surfaces. The goal is to establish scatterometry as a traceable and absolute metrological method for dimensional measurements. Scatterometry is an indirect measuring method. There are three aspects to be investigated for a proper estimation of the measurement uncertainties. Firstly, the measured optical properties will have measurement uncertainties. The optimization theory provides well-proven algorithms to propagate the uncertainties of the input parameters to the output, using covariance or Monte Carlo methods. Secondly, it must be assured that the model represents the measurement object sufficiently well. Due to the large number of parameters it takes to model a real object, it is not possible to simultaneously determine all of them from the measured data. Therefore, a priori knowledge about reasonable values for certain model parameters and their associated variances is needed. Their impact on the uncertainties of the reconstructed parameters describing the nano-structured surface has to be considered too. Thirdly, there are assumptions in the model which are inherent properties of the mathematical methods used. The assumption that the structures are periodic over a sufficiently large area, i.e. the measurement field, is of the most importance. Line-edge or line-width roughness are obviously effects disturbing the periodicity and the corresponding uncertainty contribution can be derived by an analytical approach to estimate their influence on the diffracted intensities. In our example the latter contribution is the dominant one.

As leading edge lithography is moving to 2x-nm design rules, lithography control complements resolution as one of the main drivers and enablers to meet the very stringent overlay, focus and CD requirements. As part of ASML's holistic lithography roadmap, ASML is developing several application-specific optimization and control applications, such as LithoTuner Pattern Matcher and BaseLiner. These applications are all explicitly designed to improve the scanner process window (overlay, focus, CDU and matching). All these applications have in common that they require vast amounts of precise, accurate and process robust wafer data (either taken on product stacks or on so-called monitor wafers). To provide such essential data in a cost-effective manner, ASML developed a metrology platform, called YieldStar. This platform is based on an angle-resolved high-NA scatterometer. It is versatile, as YieldStar's sensor can measure overlay, CD and focus in a single measurement. Thanks to its high speed, large amounts of measurements can be quickly collected. In this paper the latest generation YieldStar is presented, the so-called 200 platform. This YieldStar 200 can be used in a stand-alone configuration (S-200) or as an integrated module in a lithography track (T-200). First overlay results show good TMU results without comprising speed. Furthermore, data is shown that demonstrate YieldStar's capability to reconstruct 3D CD patterns as well.

In this paper we perform a fundamental study on the impact of mask absorber in ArF immersions lithography: the mask 3D effects. From simulations and analysis of diffraction coefficients we could identify a range of relevant features and imaging and placement phenomena. For these features, experimental results were obtained to pinpoint the mask 3D effects. We will demonstrate how to model and understand the mask 3D effects and give solutions to counteract the mask 3D effects.

For the high volume manufacturing at the 45nm node and beyond it is crucial to match the OPC behaviour of all scanners used at a given process step. For this task the ASML LithoTuner PatternMatcher software was used. LithoTuner PatternMatcher is a tool to improve the proximity differences between a reference scanner and one or more so called 'to be matched' scanners. The optimization uses the concept of sensitivities of CDs of critical features towards adjustable scanner parameters in combination with the delta CD's of those critical features. To perform the scanner matching it is very important to have accurate and repeatable CD data. Therefore we investigated the use of scatterometry as a replacement for the traditional CDSEM measurement. Scatterometry significantly enhances the measurement precision while simultaneously reduces the measurement time. In a first step we determined the sensitivities of the structures by measuring the CD response to small perturbations of the individual scanner parameter settings. CD through pitch and repeating 2 dimensional line end structures were measured using the ASML YieldStar tool and a Hitachi CDSEM. The scatterometry- and CDSEM based sensitivities of the scanner parameter settings are compared. Finally a scanner matching based on both sets of sensitivities has been performed. In this article we will show that both methods are suited to perform the scanner matching. We will also present the differences between the two sets of sensitivities obtained with scatterometry and CDSEM. At the end we will present the results of the tool matching and show the results of a cross check. In the cross check sensitivities obtained with the use of scatterometry were used for the scanner matching next to SEM metrology used for verification.

For the next years optical lithography stays at 193nm with a numerical aperture of 1.35. Mask design becomes more complex, mask and lithography specifications tighten. The k1 factor comes close to 0.25 which leads to a tremendously increased Mask Error Enhancement Factor (MEEF). This means that CD errors on mask are getting highly amplified on wafer. Process control becomes more important than ever. Accurate process control is a key factor to success to maintain a high yield in chip production. One key parameter to ensure a high and reliable functionality for any integrated circuit is the critical dimension uniformity (CDU). There are different contributors which impact the intra-field CD performance at wafer such as mask CD uniformity, scanner fingerprint, resist process etc. In the present work we focus on improvement of mask CD signature which is one of the main contributors to intra-field CD uniformity. The mask CD uniformity has been measured by WLCD32 which measures the CD based on proven aerial image technology. Based on this CD input the CD uniformity was corrected by CDC200^TM and afterwards verified by WLCD32 measurement. The CDC200^TM tool utilizes an ultrafast femto-second laser to write intra-volume shading elements (Shade-In Elements^TM) inside the bulk material of the mask. By adjusting the density of the shading elements, the light transmission through the mask is locally changed in a manner that improves wafer CDU when the corrected mask is printed. Additionally, the impact of the improved CD uniformity on the lithography process window was investigated. Goal of the work is to establish a process flow for mask CD uniformity improvement based on mask CD metrology by WLCD32 and mask CD uniformity control by CDC200^TM and to verify its impact on the lithography process window. The proposed process flow will be validated by wafer prints. It was shown that the WLCD32 has an excellent correlation to wafer data and an outstanding CD repeatability. It provides a reliable input for CD uniformity correction and is the tool of choice to verify the CD uniformity improvement after CDC200^TM treatment.

Traditional scanner matching methods have been based in 1D proximity matching targets and the use of wafer-based CD metrology to characterize both the initial mismatch as well as the sensitivity of CDs to scanner tuning knobs. One such method is implemented in ASML Pattern Matcher, which performs a linear optimization based on user provided CD sensitivities and pre-match data. The user provided data usually comes from wafer exposures done at multiple scanner illumination conditions measured with CD-SEM. In the near future ASML plans to provide the capability to support YieldStar CD data for Pattern Matcher which will collect CD data with higher precision and much faster turn-around-time that CD-SEM. Pattern Matcher has been used successfully in multiple occasions. Results for one such occasion are shown in Figure 1 which presents the through pitch mismatch behavior of one ASML XT:1400F with respect to an ASML XT:1400E for a 32nm contact layer.

The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

Extreme Ultraviolet Lithography (EUVL) is considered the leading lithography technology choice for semiconductor devices at 16nm HP node and beyond. However, before EUV Lithography can enter into High Volume Manufacturing (HVM) of advanced semiconductor devices, the ability to guarantee mask integrity at point-of-exposure must be established. Highly efficient, damage free mask cleaning plays a critical role during the mask manufacturing cycle and throughout the life of the mask, where the absence of a pellicle to protect the EUV mask increases the risk of contamination during storage, handling and use. In this paper, we will present effective EUVL mask cleaning technology solutions for mask manufacturing and in-fab mask maintenance, which employs an intelligent, holistic approach to maximize Mean Time Between Cleans (MBTC) and extend the useful life span of the reticle. The data presented will demonstrate the protection of the capping and absorber layers, preservation of pattern integrity as well as optical and mechanical properties to avoid unpredictable CD-linewidth and overlay shifts. Experiments were performed on EUV blanks and pattern masks using various process conditions. Conditions showing high particle removal efficiency (PRE) and minimum surface layer impact were then selected for durability studies. Surface layer impact was evaluated over multiple cleaning cycles by means of UV reflectivity metrology XPS analysis and wafer prints. Experimental results were compared to computational models. Mask life time predictions where made using the same computational models. The paper will provide a generic overview of the cleaning sequence which yielded best results, but will also provide recommendations for an efficient in-fab mask maintenance scheme, addressing handling, storage, cleaning and inspection.

The aim of this study is to determine the different types of haze contamination that occur in industrial conditions, using direct physico-chemical analyses on full 6" masks leaving their pellicle intact. Contaminated masks coming from end users (ST - France) or masks fab (Toppan Photomask) have been analysed. First, references XPS analyses on specially designed blanks from Toppan have been performed. Four references have been studied by angle resolved XPS. These studies show the absence of nitrogen and sulfur contamination on SiO₂ side for the four references. On Cr side, a weak residual sulfur contamination has been observed as well as a very significant nitrogen concentration for the masks treated with a standard process. Concerning the masks treated with a sulfate free process, on Cr side, no residual sulfur has been detected by XPS, whereas few trace of nitrogen amount has been detected. Then a mask coming from the ST fab contaminated in real industrial conditions has been studied with several complementary characterisation techniques such as XPS, SEM, Raman and Tof-SIMS. Theses analyses confirm that the back glass haze on the mask is on a particle form. Two types of defects have been found: small particles (a few μm size), having a stick shape, with a very typical form indicating a crystal growth mechanism, and big particles (a few 10 μm size).The detailed physico-chemical results show the composition of the particles. Raman and Tof-Sims clearly show that small particle (with a stick form) are made of ammonium sulfate (NH₄)₂SO₄ crystals. XPS, Raman and Tof-Sims indicate that big particles are a nitrogen containing polymer with a weak sulphate contamination.

Photomask technology has attained feature sizes of about 50nm and below. Whereas the main feature size is still above 70-80nm at 20nm technology node recently reported e.g. by Toppan Printing Company as developed, assist features for this node are in the range of 50-60nm. One of the critical aspects of this technology development is the cleaning process. Processes are supposed to clean off contamination and particles down to a defect size of about 40nm and at the same time prevent damage to assist features in the same size range. Due to obvious trade offs between cleaning power and Feature Damage Probability (FPD), this task becomes tricky. Improvement of cleaning processes by raising the power of megasonic (MS) cleaning, or adjusting the speed and size of droplets for spray cleaning occurs at the expense of increased feature damage. Prolongation of physical cleaning steps does not necessarily leads to improvement of the cleaning as shown previously. Susceptibility to feature damage occurs predicatively according to dimension and orientation. This allows us to extrapolate a Feature Damage Limit (FDL) which approximates the smallest feature size for which a process has an acceptable probability of success. In a practical sense, the most advantageous approach seems to be to adjust the cleaning power to the maximum allowed by the FDP and then optimize to the lowest process time necessary to reach expected cleaning efficiency. Since there are several alternative physical cleaning principles, we have to pick the best one for a given application. At this point we have to raise the question of how to compare the cleaning efficiency of processes. The goal of this work is to provide a method for evaluation and comparison of cleaning efficiency between physical cleaning processes and demonstrate the method on an example. We will focus on comparing two physical cleaning processes 1MHz megasonic and binary spray process.

Cleanroom technology is a principle pre-condition and the enabling technology for contamination free manufacturing. With the transition from large cleanroom facilities for semiconductor manufacturing to localized encapsulated cleanroom solutions which are called minienvironments the traditional cleanroom technology is extended into a new field of applications. With view to the highest requirements in semiconductor industries and especially in the mask area, extraordinary concepts and solutions has to be developed and applied. In this contribution the fundamental considerations about the different concepts for minienvironments are outlined and reviewed. A set of various parameters involved in a design process for a state of the art minienvironment are given and discussed in detail. The resulting different concepts are presented and the strength of each concept is discussed. The resulting minienvironment solutions are demonstrated on three characteristic examples and options, alternatives and the advantages of the individual concepts are mentioned. Based on the current status of minienvironment technology an out-look is given about future challenges and open questions to be solved.

Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a reasonable range (a few hundred). The proposed test cells have been inserted in the scribe lanes of an engineering Gate mask of one of STMicroelectronics' high volume products. Real Hot Spots, detected in the product chosen as the test vehicle, have also been submitted to the same variations and inserted in scribe blocks. In parallel with OPC-like scribe layouts, four best-guess treatments were applied, on the same critical mask, to assess transistor performance and yield impact by standard wafer splitting on engineering lots. The advanced binary 4×6" reticle for 193nm exposure has been manufactured by Toppan Photomasks in the AMTC facility in Dresden using the standard production process on the NuFlare5000 e-beam writing platform. The exploration of the parameter space around the current working point will determine if the current process settings already represent an optimum or if there is room for significant improvement of the wafer manufacturing process.

For current and future semiconductor technology nodes with critical dimensions of 32 nm or below, the e-beam lithography is faced with increasing challenges to achieve a reasonable patterning of structures, especially if a process with a chemically amplified resist is used. The reasons for these limitations are the physical properties of the transfer process used to print a structure onto the resist-coated substrate, which inherently contains an unavoidable blurring of the deposited e-beam energy around the desired shape. This blurring is usually described by a so called process proximity function (PPF) and mostly approximated by a superposition of two or more Gaussian functions. The PPF includes the e-beam blur, electron forward scattering and resist effects (often described altogether by the so called alpha parameter of the PPF [K. Keil et al, "Resolution and total blur: Correlation and focus-dependencies in e-beam lithography," J. Vac. Sci. Technol. B 27, 2722 (2009)]) as well as the backscattering effect (often described by the so called beta parameter of the PPF). When the desired critical dimensions of structures are near or below the alpha parameter of the PPF, depending on their environment it may be just impossible to print the structures because of the vanishing image contrast. The PPF model confirms this well-known behavior but also shows ways and limits for improvements. This paper provides real pattern lithography results - comparing classical and GIDC correction - for exposures done on a Vistec SB3050DW shaped e-beam writer. A performance comparison of the GIDC method and the classical dose correction in terms of data preparation and writing time is presented.

For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below 32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a proximity effect correction (PEC) which is mostly based on a dose modulation. This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.

On the road to and beyond the 22nm half-pitch on chip patterning technology, 13.5nm EUVL is widely considered the best next technology generation following deep ultraviolet lithography. The availability of an actinic measurement system for the printability analysis of mask defects to ensure defect-free mask manufacturing and cost-effective high-volume EUV production is an infrastructural prerequisite for the EUVL roadmap and represents a significant step toward readiness for commercialization of EUV for high-volume-manufacturing . Carl Zeiss and SEMATECH's EUVL Mask Infrastructure (EMI) program started a concept study and feasibility plan for a tool that emulates the aerial image formed by a EUV lithography scanner supporting the 22 nm half-pitch node requirements with extendibility to the 16nm half-pitch node. The study is targeting a feasible concept for the AIMS^TM EUV platform, bridging a significant gap for EUV mask metrology.

Extreme Ultra Violet Lithography (EUVL) is one of the most advanced patterning technologies to overcome the critical resolution limits of current ArF lithography for 30nm generation node and beyond. Since EUVL mask manufacturing process has not been fully stabilized yet, it is still suffering from many defect issues such as blank defects, defects inside multilayer causing phase defects, CD defects, LERs (Line Edge Roughness), and so on. One of the most important roles in mask manufacturing process belongs to mask inspection tools, which monitor and visualize mask features, defects and process quality for the EUVL process development. Moreover, as the portion of EUV mask production has been increased due to the EUV Pre-Production Tool (PPT) development, mask inspection technologies for EUVL become highly urgent and critical to guarantee mask quality. This paper presents a promising inspection technique for increasing the contrast of pattern imaging and defects capture rate using configurable illumination conditions in 193nm wavelength inspection tool.

In this follow-up paper for our contribution at BACUS 2010, first evidence is shown that also the more advanced Lasertec M7360 has missed a few printing reticle defects caused by an imperfection of its EUV mirror, a so-called multilayer defect (ML-defect). This work continued to use a combination of blank inspection (BI), patterned mask inspection (PMI) and wafer inspection (WI) to find as many as possible printing defects on EUV reticles. The application of more advanced wafer inspection, combined with a separate repeater analysis for each of the multiple focus conditions used for exposure on the ASML Alpha Demo Tool (ADT) at IMEC, has allowed to increase the detectability of printing MLdefects. The latter uses the previous finding that ML-defects may have a through-focus printing behavior, i.e., they cause a different grade of CD impact on the pattern in their neighborhood, depending on the focus condition. Subsequent reticle review is used on the corresponding locations with both SEM (Secondary Electron Microscope) and AFM (Atomic Force Microscope). This review methodology has allowed achieving clear evidence of printing ML defects missed by this BI tool, despite of an unacceptable nuisance rate reported before. This is a next step in the investigation if it is possible to avoid actinic blank inspection (ABI) at all, the only presently known technique that is expected to be independent from the presence of a (residual) topography of the ML-defect at the top of the EUV mirror, in detecting those defects. This is considered an important asset of blank inspection, because the printability of a ML-defect on the EUV scanner and its detectability by ABI is determined by the distortion throughout the multilayer, not that at the surface.

EUVL requires the use of reflective optics including a reflective mask. The mask contains a reflecting multilayer, tuned for 13.5 nm light, and an absorber which defines the dark areas. The EUV mask itself is a complex optical element with many more parameters than just the mask CD uniformity of the patterned features that impact the final wafer CDU. One of these parameters is absorber height. It has been shown that the oblique incidence of light in combination with the small wavelength compared to the mask topography causes a so-called shadowing effect manifesting itself particularly in an HV wafer CD offset. It was also shown that this effect can be essentially decreased by reducing absorber height and, in addition, it can be corrected by means of OPC. However, reduction of absorber height has a side effect that is an increased reflectivity of a mask black border resulting in field-to-field stray light due to parasitic reflections. One of the solutions to this problem is optical process correction (OPC) at field edges. In this paper we will show experimental data obtained on ASML EUV Alpha tool illustrating the black border effect and will demonstrate that this effect can be accurately predicted by Brion Tachyon EUV model allowing for a significant cross field CD uniformity improvement with mask layout correction technique. Also we show by means of rigorous 3D simulations that it is possible to improve the imaging performance significantly by performing global optimization of mask absorber height and mask bias in order to increase exposure latitude, decrease CD sensitivity to mask making variations such as CD mask error and absorber stack height variations. By sacrificing some exposure latitude throughput of exposure tool can be increased essentially and HV mask biasing can be reduced. For four masks with different absorber thicknesses from 44 nm to 87 nm it is proven experimentally by means of the EUV Alpha tool exposures of 27 nm L/S that the absorber thickness can be tuned to maximize exposure latitude. It was also proven that dose to size grows with absorber height and optimal feature bias depends on mask absorber height.