This PDF file contains the front matter associated with SPIE Proceedings Volume 9050, including the Title Page, Copyright Information, Table of Contents, and the Conference Committee listing.

There has been significant interest in hybrid metrology as a novel method for reducing overall measurement uncertainty and optimizing measurement throughput (speed) through rigorous combinations of two or more different measurement techniques into a single result. This approach is essential for advanced 3-D metrology when performing model-based critical dimension measurements. However, a number of fundamental challenges present themselves with regard to consistent noise and measurement uncertainty models across hardware platforms, and the need for a standardized set of model parameters. This is of paramount concern when the various techniques have substantially different models and underlying physics. In this paper we present realistic examples using scanning electron microscopy, atomic force microscopy, and optical critical dimension (CD) methods applied to sub-20 nm dense feature sets. We will show reduced measurement uncertainties using hybrid metrology on 15 nm CD features and evaluate approaches to adapt quantitative hybrid metrology into a high volume manufacturing environment.

Integrated Circuit (IC) technology is changing in multiple ways: 193i to EUV exposure, planar to non-planar device architecture, from single exposure lithography to multiple exposure and DSA patterning etc. Critical dimension (CD) control requirement is becoming stringent and more exhaustive: CD and process window are shrinking., three sigma CD control of < 2 nm is required in complex geometries, and metrology uncertainty of < 0.2 nm is required to achieve the target CD control for advanced IC nodes (e.g. 14 nm, 10 nm and 7 nm nodes). There are fundamental capability and accuracy limits in all the metrology techniques that are detrimental to the success of advanced IC nodes. Reference or physical CD metrology is provided by CD-AFM, and TEM while workhorse metrology is provided by CD-SEM, Scatterometry, Model Based Infrared Reflectrometry (MBIR). Precision alone is not sufficient moving forward. No single technique is sufficient to ensure the required accuracy of patterning. The accuracy of CD-AFM is ~1 nm and precision in TEM is poor due to limited statistics. CD-SEM, scatterometry and MBIR need to be calibrated by reference measurements for ensuring the accuracy of patterned CDs and patterning models. There is a dire need of measurement with < 0.5 nm accuracy and the industry currently does not have that capability with inline measurments. Being aware of the capability gaps for various metrology techniques, we have employed data processing techniques and predictive data analytics, along with patterning simulation and metrology models, and data integration techniques to selected applications demonstrating the potential solution and practicality of such an approach to enhance CD metrology accuracy. Data from multiple metrology techniques has been analyzed in multiple ways to extract information with associated uncertainties and integrated to extract the useful and more accurate CD and profile information of the structures. This paper presents the optimization of scatterometry and MBIR model calibration and feasibility to extrapolate not only in design and process space but from one process step to a previous process step. Well calibrated scatterometry model or patterning simulation model can be used to accurately extrapolate and interpolate in the design and process space for lithography patterning where AFM is not capable to accurately measure sub-40 nm trenches. Uncertainty associated with extrapolation can be large and needs to be minimized. We have made use of measurements from CD-SEM and CD-AFM, along with the patterning and scatterometry simulation models to estimate the uncertainty associated with extrapolation and methods to reduce it. First time we have reported the application of machine learning (Artificial Neural Networks) to the resist shrinkage systematic phenomenon to accurately predict the preshrink CD based on supervised learning using the CD-AFM data. The study lays out various basic concepts, approaches and protocols of multiple source data processing and integration for hybrid metrology approach. Impacts of this study include more accurate metrology, patterning models and better process controls for advanced IC nodes.

Today, metrology toolsets report out more information than ever. This information applies not only to process performance but also metrology toolset and recipe performance through various diagnostic metrics. This is most evident on the Critical Dimension Scanning Electron Microscope (CD-SEM). Today state of the art CD-SEMs report out over 250 individual data points and several images per measurement. It is typical for a state of the art fab with numerous part numbers to generate at least 20TB of information over the course of a year on the CD-SEM fleet alone pushing metrology toolsets into the big data regime. Most of this comes from improvements in throughput, increased sampling and new data outputs relative to previous generations of tools. Oftentimes, these new data outputs are useful for helping to determine if the process, metrology recipe or tool is deviating from an ideal state. Many issues could be missed by singularly looking at the key process control metric like the bottom critical dimension (CD) or a small subset of this available information. By leveraging the entire data set the mean time to detect and finding the root cause of issues can be significantly reduced. In this paper a new data mining system is presented that achieves this goal. Examples are shown with a focus on the benefits realized using this new system which helps speed up development cycles of learning and reducing manufacturing cycle-time. This paper concludes discussing future directions to make this capability more effective.

In an ongoing study of the physical characterization of Gate-All-Around Silicon Nano Wires (GAASiNW), we found that the thin, suspended wires are prone to buckling as a function of their length and diameter. This buckling takes place between the fixed source and drain regions of the suspended wire, and can affect the device performance and therefore must be studied and controlled. For cylindrical SiNW, theory predicts that buckling has no directional preference. However, 3D CDSEM measurement results indicated that cylindrical wires prefer to buckle towards the wafer. To validate these results and to determine if the electron beam or charging is affecting our observations, we used 3D-AFM measurements to evaluate the buckling. To assure that the CDSEM and 3D-AFM measure the exact same locations, we developed a design based recipe generation approach to match the 3D-AFM and CDSEM coordinate systems. Measuring the exact same sites enables us to compare results and use 3D-AFM data to optimize CDSEM models. In this paper we will present a hybrid metrology approach to the characterization of GAASiNW for sub-nanometer variations, validating experimental results, and proposing methods to improve metrology capabilities.

In recent years Hybrid Metrology has emerged as an option for enhancing the performance of existing measurement toolsets and is currently implemented in production¹. Hybrid Metrology is the practice to combine measurements from multiple toolset types in order to enable or improve the measurement of one or more critical parameters. While all applications tried before were improved through standard (sequential) hybridization of data from one toolset to another, advances in device architecture, materials and processes made possible to find one case that demanded a much deeper understanding of the physical basis of measurements and simultaneous optimization of data. This paper presents the first such work using the concept of co-optimization based hybridization, where image analysis parameters of CD-SEM (critical dimensions Scanning Electron Microscope) are modulated by profile information from OCD (optical critical dimension – scatterometry) while the OCD extracted profile is concurrently optimized through addition of the CD-SEM CD results. Test vehicle utilized in this work is the 14nm technology node based FinFET High-k/Interfacial layer structure.

The shape and dimensions of a challenging pattern have been measured using a model-based library scanning electron microscope (MBL SEM) technique. The sample consisted of a 4-line repeating pattern. Lines were narrow (10 nm), asymmetric (different edge angles and significant rounding on one corner but not the other), and situated in a complex neighborhood, with neighboring lines as little as 10 nm or as much as 28 nm distant. The shape cross-section determined by this method was compared to transmission electron microscopy (TEM) and critical dimension small angle x-ray scattering (CD-SAXS) measurements of the same sample with good agreement. A recently-developed image composition method was used to obtain sharp SEM images, in which blur from vibration and drift were minimized. A Monte Carlo SEM simulator (JMONSEL) produced a model-based library that was interpolated to produce the best match to measured SEM images. Three geometrical and instrument parameterizations were tried. The first was a trapezoidal geometry. In the second one corner was significantly rounded. In the last, the electron beam was permitted to arrive with stray tilt. At each stage, the fit to the data improved by a statistically significant amount, demonstrating that the measurement remained sensitive to the new parameter. Because the measured values represent the average unit cell, the associated repeatabilities are at the tenths of a nanometer level, similar to scatterometry and other area-averaging techniques, but the SEM’s native high spatial resolution also permitted observation of defects and other local departures from the average.

In this paper, Frontier Semiconductor will introduce a new technology that is referred to as Virtual Interface Technology (VIT™). VIT™ is a Fourier domain technique that utilizes temporal phase shear of the measurement beam. The unique configuration of the sensor enables measurement of wafer and bonded stack thicknesses ranging from a few microns to millimeters with measurement repeatability ~ nm and resolution of approximately 0.1% of nominal thickness or depth. We will present data on high aspect ratio via measurements (depth, top critical dimension, bottom critical dimension, via bottom profile and side wall angle), bonded wafer stack thickness, and Cu bump measurements. A complimentary tool developed at FSM is a high resolution μRaman spectrometer to measure stress-change in Si lattice induced by Through Silicon Via (TSV) processes. These measurements are important to determine Keep-Out-Zone in the areas where devices are built so that the engineered gate strain is not altered by TSV processing induced strain. Applications include via post-etch; via post fill, and bottom Cu nail stress measurements. The capabilities of and measurement results from both tools are discussed below.

At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R² being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R² being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.

A new SEM technology is becoming available that allows image-based 3D profile metrology of nanoscale features. Using patented multi-channel detector technology, this system can acquire information of surface concave and convex features, and sidewall angle (SWA) and height of profiles, quickly and non-destructively for nanoscale structures such as fin field-effect transistors (FinFETs), using electron beam technology with its well-known long probe lifetime, stability and small probe size. Here we evaluate this new technology and demonstrate its applicability to contemporary advanced structures such as FinFETs, including not only CD, but also profile, SWA, top corner rounding (TCR) and bottom corner rounding (BCR).

3D integration technology offers an alternative to traditional packaging designs. In traditional Moore’s law scaling, features are added to the die, with graphics, memory control and logic coprocessors all integrated onto the silicon chip. TSV (through silicon via) processing utilizes vertical electrical interconnects that provide the shortest possible path to establish an electrical connection from the device side to the backside of a die. This indirectly allows continues “Moore”- like scaling while only affecting the device packaging. White light interferometry (WLI) has been used for the measurement of topography, step height and via depth using its short coherence length. The nanometer level resolution of this technique is ideal for TSV measurements in the high aspect ratio vias. In this work, six white light interferometer measurements for TSV processing are discussed along with the importance of these measurements to TSV processing, namely: 1. Post-TSV etch: depth, top CD (TCD) and bottom CD (BCD) 2. Post-TSV liner BCD 3. Post-TSV barrier seed BCD 4. TSV electro-chemically plated (ECP) copper bump step height 5. Post-annealing bump step height 6. TSV CMP dishing These measurement steps have been implemented in-line for advanced technology node TSV process flows at GLOBALFOUNDRIES. The measurements demonstrate 90% correlation to reference metrology and <0.5% repeatability. Cross section SEM was used as a reference for TSV profile and Cu bump measurements while AFM was used as a reference for dishing measurements.

Line-edge roughness (LER) and linewidth roughness (LWR) in lithography are best characterized by the roughness power spectrum density (PSD), or similar measures of roughness frequency and correlation. The PSD is generally thought to be described well by three parameters: standard deviation, correlation length, and roughness exponent. The next step toward enabling these metrics for pertinent industrial use is to understand how real metrology errors interact with these metrics and what should be optimized on the critical dimension scanning electron microscopy (CD-SEM) to improve error budgets. In this work, Java Monte Carlo Simulator of Secondary Electrons (JMONSEL) simulation is used to better understand how various SEM parameters, beam size/shape, and sample profile influence SEM line edge uncertainty and also some of the systematic shifts in edge location assignment. A thorough understanding of the impact of the SEM on the measurement results enables better measurement of LER PSD and better interpretation of measurement results.

A new Monte Carlo code is presented that includes among others definition of arbitrary geometries with sub-nanometer resolution, high performance parallel computing capabilities, trapped charge, electric field calculation, electron tracking in electrostatic field, and calculation of 3D dose distributions. These functionalities are efficiently implemented thanks to the coupling of the Monte Carlo simulator with a TCAD environment. Applications shown are the synthesis of SEM linescans and images that focus on the evaluation of the impact of proximity effects and self charging on the quantitative extraction of critical dimensions in dense photoresist structures.

We have proposed a new method for correcting electron beam (EB)-induced photoresist shrinkage in two-dimensional pattern contours extracted from a scanning electron microscope image. This method restores the original shrinkage-free contour from the experimentally determined “shrunk contour”, based on a shrinkage model which takes into account of the elastic nature of the shrinkage phenomena caused by the photoresist-volume reduction. Verification of this shrinkage model was demonstrated by using ArF resist patterns as follows. First, the model was calibrated with the shrinkage data of several line patters with different linewidth prior to the contour correction. Next, the amount of shrinkage of elbow patterns was measured by comparing its contours obtained with small and sufficiently large EB dosages. It was found that the shrinkage of the inner edge of the elbow corner was smaller than that of the outer edge, which can be interpreted as a result of the elastic deformation. Finally, validity of shrinkage correction was examined. The model calculation correctly reproduced the observed shrinkage including its dependence on the location in the pattern. The restored contour showed a good consistency with the experimental results and the total root-mean-square error of the shrinkage correction was 0.5 nm. This result confirmed that our shrinkage model adequately describes the shrinkage of two dimensional patterns. Consequently, proposed shrinkage correction method is expected to improve the accuracy of contour measurements by a critical dimension-scanning electron microscope.

Systematic understanding of the mechanism of secondary-electron (SE) emission is important to simulate an SEM image of a high-aspect-ratio (AR) structure. The simulation technique for a high-AR structure is useful for optimizing the observation conditions of SEM. Trench patterns with AR between 0.5 and 8 were fabricated on the same substrate, and dependence of SE yield on AR of the trench patterns was determined from SEM images for several landing energies of primary electrons. In addition, to understand the SE emission inside a trench, Monte-Carlo simulation of the signal intensity for Si was performed. The SEM observations and simulation results indicate that SEM image contrast at the bottom of a trench improves with decreasing landing energy (owing to a positive charging effect) and that reflection of SEs at the sidewall of a trench is essential for accurately estimating SE emission for the high-AR structure with AR over eight.

We investigated off-line metrology for LER determination in low-dose SEM images to reduce the acquisition time and the risk of shrinkage. Our first attempts are based on filtering noisy (experimental) SEM images and use peak detection to measure the edge displacements and calculating the discrete PSD. However, the result of the filtering is that the power spectrum of the filter leaks into the PSD. So it is better to avoid a filter at all. We subsequently developed a method to detect edge displacements without the use of a filter. This method considers the signal profile of a SEM by integrating an experimental image of lines in the direction of the edges. The signal profile of an isolated edge is modeled as two merged Gaussians. This signal profile is then fitted against the raw (unfiltered) data of the edge pattern using an interior trust-region-reflective minimization procedure. This gives the edge displacements without the use of a filter and a filter-free version of the discrete PSD is obtained. The determination of edge displacements without the use of a filter, enables us to study how much noise is acceptable and still determine LER. To answer this question we generate random lines using the model of Palasantzas and the algorithm of Thorsos. This gives random generated edge displacements for typical values of experimental lines for the parameters of the model: 2 μm long lines (256 pixels), a correlation length ξ of 25 nm and a roughness exponent of 0.75. A noise-free top-down SEM-like image of lines is created by shifting the profile signal according to the random generated edge displacements. The image is further processed by adding Poisson-distributed noise. We consider three noise cases where the average electron density is about 2, 20 and 200 electrons per pixel. This corresponds to a charge density of (in respective order) 10 μC/cm², 100 μC/cm² and 1000 μC/cm². The edge displacements of the random generated images are determined using our new developed filter-free displacement detection. The difference between the random generated displacements and the detected displacements (after adding Poisson-distributed noise) shows how pixel noise translates to noise in edge displacements. We conclude from running many simulations that this pixel noise translates to a noise in the edge displacements which is uniform (flat line) in the PSD. This means that pixel noise is classified as white noise in the edge displacements. Finally, we study simulated discrete PSDs as a function of the number of averages and analyze the convergence of the parameters (σ, σ_n, ξ and α) of the Palasantzas model extended with a white noise term. One of the conclusions is that a very noisy image with 12 lines and about 2 electrons per pixel on average (charge density ≈ 10 μC/cm²) already produces an estimation for LER with a relative error of about 10%.

Topographic profiles are reconstructed from top-view images in scanning electron microscope (SEM) by predicting a local slope angle based on how surface roughness (morphology) looks from top-view. Careful analysis of Line edge roughness (LER) reveals that LER obtained in top-view SEM images is decomposed into three components, parallel shift, cross-sectional shape deformation, and surface roughness, and the local slope angle of pattern surface is estimated from the surface roughness component, which corresponds to the projection of surface roughness onto the substrate plain. Cross-sectional profiles reconstructed by scanning this procedure across top-view SEM images showed good agreements with the results obtained by other metrology methods such as an atomic force microscope.

Directed self-assembly (DSA) shows considerable promise as a cost-effective manufacturing technique for advanced sub-20 nm patterning. Along with continued progress, the patterning process requires advances in both CD metrology and high-speed characterization of DSA defectivity. This work is a report on the study of Mueller matrix spectroscopic ellipsometry (MMSE) scatterometry measurements of 28 nm pitch DSA line/space patterns consisting of polystyrene-block- polymethylmethacrylate (PS-b-PMMA) block copolymer sample fabricated using a chemical epitaxy process. Generalized ellipsometric data (all 16 Mueller elements) is collected over a spectral range from 245 to 1700 nm for various different pre-pattern pitch/guide strip combinations created by modulating the pre-pattern photoresist CD. Scatterometry is used to evaluate and calculate the CD, line shapes, and thicknesses of the plasma developed PS patterns (PMMA removed). Likewise, spectral comparisons based on anisotropy and depolarization are used to determine the DSA pattern defectivity. CD-SEM metrology and imaging is also conducted as a comparative metric for scatterometry. The sensitivity of MMSE to pre-pattern pitch and pitch multiplication on PS line CD and defectivity is demonstrated. Slight imperfections in the line/space pattern as well as fingerprint like patterns (undirected assembly) can be distinguished from aligned patterns using MMSE scatterometry.

One of the major challenges associated with insertion of a directed self-assembly (DSA) patterning process in high volume manufacturing (HVM) is finding a non-destructive, yield-compatible, consistent critical dimension (CD) metrology process. Current CD scanning electron microscopy (CD-SEM) top-down approaches do not give the profile information for DSA patterns, which is paramount in determining the subsequent pattern transfer process (etch, for example). SEMATECH, in cooperation with some of the leaders of the metrology and DSA materials supply chain, has led an effort to address such metrology challenges in DSA. We have developed and evaluated several techniques (including a scatterometry-based method) that are potentially very attractive in determining DSA pattern profiles and have embedded bridging in such patterns without resorting to destructive cross-section imaging. We show how such processes could be fine-tuned to enable their insertion for DSA pattern characterization in an HVM environment.

Evaluating pattern sensitivity to variability of the process parameters is of increasing importance to improve resolution enhancement techniques. In this paper, we propose an efficient algorithm to extract printed shapes from SEM images, a novel quality metric which analyzes the topology of the extracted printed shapes with respect to the target mask shape and a unique set of descriptors that define the sensitivity of a pattern. Compared to traditional CD methods, the proposed method has better accuracy, increased robustness and ability to spot global changes. Compared to contours distance methods, it is designed to expose most critical regions and capture context effects.

The quest to create robust control solutions for Photolithography processes is an ongoing matter. Over the past few decades several threaded and non-threaded Run-to-Run (RtR) control solutions have been introduced addressing various specific Lithography process control requirements. With continually shrinking semiconductor technology nodes, greater interdependencies are being observed between processes requiring more complex control solutions that rely on increasing process context. With higher product mixes, associated metrology costs add to this growing complexity in using existing control solutions effectively. A new dynamic RtR control solution approach in GLOBALFOUNDRIES high mix manufacturing environment offering coverage to all Lithography process steps in Fab8 has been architected and implemented. This approach not only addresses the issues caused in most commonly used ‘Threaded’ and ‘Non-Threaded’ control approaches in Lithography but also offers a dynamic thread definition implementation approach.

This paper introduces to improve inter-field CDU with on-product focus control by diffraction based focus (DBF) method. For DBF target selection, a robust focus metrology for focus control was obtained, and the selected DBF target was integrated on each seven spot of a product reticle. For on-product focus control, previously on-product focus monitoring was performed, and the monitored lots showed a stable focus fingerprint. Based on the result, Z and Z/ Rx/Ry corrections per field on wafers were applied. Focus uniformity of controlled wafers was improved up to 29% in comparison with non-corrected ones. To demonstrate the improvement of inter-field CDU, Full CDs on wafers were measured by SEM. As a result, inter-field CDU for controlled wafers was improved by 16% (3σ) compared with noncontrolled wafers.

In order to meet current and future node overlay, CD and focus requirements, metrology and process control performance need to be continuously improved. In addition, more complex lithography techniques, such as double patterning, advanced device designs, such as FinFET, as well as advanced materials like hardmasks, pose new challenges for metrology and process control. In this publication several systematic steps are taken to face these challenges.

This paper will explore the possibilities of critical dimension scanning electron microscope (CD-SEM) metrology at sub- 10 nm feature sizes using modeling. JMONSEL simulations will be used to illustrate SEM waveforms for very small features, as a function of beam energy, feature size, profile height and sidewall angle. It will also be shown that the dimensions of the electron beam and interaction volume have very strong influence on the results. Using modeled results, an assessment on required image quality for future tools will be presented, along with a framework for linking spot size and image resolution. Additionally, from the generated waveforms, various measurement algorithms will be evaluated for such future nanometer-scale applications.

The most decent scanning electron microscopy (SEM) can provide image magnification up to 500kX which seems to be suitable to image semiconductor devices for the advanced technology nodes. However, SEM images at such a high magnification often suffer from the drift and space related displacement errors, potentially causing image blur and distortion. To circumvent this, we apply the super-resolution (SR) technique to enhance the resolution of the CD-SEM metrology by using the advanced signal processing algorithms. The resolution enhancement can be realized by exploiting the multiple low resolution (LR) images that include unique information of an imaging target by looking at a slightly different position. We experimentally demonstrate image quality improvement gained by the SR technique after correcting the time-dependent drift/displacement and mapping estimated information onto the high resolution (HR) pixel grid with the non-linear pixel interpolation scheme. In addition, estimating the time-dependent drifts of the wafer position could be useful to investigate the drift properties of the CD-SEM tool.

We developed a new measurement method enabling to quantitatively and accurately evaluate 2D pattern shapes, which becomes critical in patterning control of Metal layer patterns transferred by Litho-Etch-Litho-Etch (LELE) process. In LELE, a split patterning of a Metal-A (MA) layer and a Metal-B (MB) layer makes patterning control more challenging. Hence, it is essential to evaluate the shape of transferred patterns after final etching in order to verify that the patterning control of MA and MB layer patterns is performed within an allowable budget. For this, our Pattern Shape Quantification (PSQ) method [1][2][3], which enables to measure dimensional difference of the transferred pattern shape from their target-design, is an effective metrology. Patterns transferred through a LELE process contain the effects of two types of shape modifications. The first is the fidelity of the individual pattern shapes (e.g. pattern-end pull-back or push-out) whose determinative factors are adopted design (e.g. OPC and SRAF), process condition (of e.g. lithography and etching), etc. The second is the shift in position between MA and MB patterns induced by Pattern Placement Error (PPE) of MB with respect to MA. That means that the edge-placement errors (EPE) in the final pattern are not only due to the fidelity of the transferred pattern shape, but are also impacted by the PPE. Also, a space between MA and MB patterns will be affected by the PPE as well. A failure to maintain a required minimum space between patterns could lead to a leak-current between patterns (and hence directly affect device performance), so it is important that the PPE can be measured accurately. Therefore, we developed a method to measure local PPE in actual device patterns, from CD-SEM images, that also outputs a pattern-contour in which this PPE has been removed. Utilizing such a pattern-contour into the PSQ method enables to quantitatively determine the fidelity of transferred pattern shape solely induced by the 1^st shape modification, while providing PPE data from the device patterns themselves. We believe that a high-quality patterning control (by e.g. optimization of process condition) of MA and MB can be performed only by using such a measurement result. This paper demonstrates and discusses the capability and effectiveness of our newly developed method.

In this paper technology of scanning probe microscopy (SPM) surface metrology using arrays of piezoresistive thermally actuated cantilevers is discussed. The cantilever architecture presented here makes it possible to image surface topography using sensors operating in parallel. In this way the throughput of the sample imaging is increased, which is of crucial importance in measurements of large area samples. Application of piezoresistive detection scheme makes it possible to investigate quantitatively the interaction between the microprobe and the imaged surface. Integration of the thermal deflection actuator with the spring beam decreases the response time and enables fast and high resolution control of the tip sample distance. The results of topography parallel measurement using 1×4 cantilever array will be presented.

The aim of the semiconductor industry to decrease the feature size of integrated circuits poses a huge technological endeavor. Consequently, new challenges are arising for metrology on structures in the nanometer regime. Scatterometry is a fast method which provides non-contact non-destructive characterization of structures on photomasks or exposed wafers. However, the determination of important line structure parameters with subnanometer accuracy still needs further investigation. Grazing incidence small-angle X-ray scattering (GISAXS) is a scatterometry technique to measure both vertical and lateral structural features in the nanometer range with high sensitivity. We apply GISAXS to the investigation of structural parameters such as period length, sidewall angle, linewidth and height on silicon gratings. Our test structures with nominal widths of 35 nm to 100 nm and a pitch from 100 nm to 250 nm were fabricated by electron beam lithography. The diffraction patterns have been analyzed by power spectral density analysis which directly yields periodical modulations of the structured surface such as line width or groove width. We also apply a finite element method (FEM) to the diffraction peak intensity of the grating structure obtained with GISAXS for the geometric reconstruction of the line shape.

Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

As design rule of semiconductor decreases continuously, overlay error control gets more and more important and challenging. It is also true that On Product Overlay (OPO) of leading edge memory device shows unprecedented level of accuracy, owing to the development of precision optics, mechanic stage and alignment system with active compensation method. However, the heating of reticle and lens acts as a dominant detriment against further improvement of overlay. Reticle heating is more critical than lens heating in current advanced scanners because lens heating can be mostly compensated by feed-forward control algorithm. In recent years, the tools and technical ideas for reticle heating control are proposed and thought to reduce the reticle heating effect. Nevertheless, it is not still simple to predict the accurate heating amount and overlay. And it is required to investigate the parameters affecting reticle heating quantitatively. In this paper, the reticle pattern density and exposure dose are considered as the main contributors, and the effects are investigated through experiments. Mask set of various transmittance are prepared by changing pattern density. After exposure with various doses, overlay are measured and analyzed by comparing with reference marks exposed in heating free condition. As a result, it is discovered that even in the case of low dose and high transmittance, reticle heating is hardly avoidable. It is also shown that there is a simple relationship among reticle heating, transmittance and exposure dose. Based on this relationship, the reticle heating is thought to be predicted if the transmittance and dose are fixed.

The introduction of double and triple patterning tightened the Overlay current nodes’ specifications across the industry to levels of 5nm and 3nm respectively. Overlay error is a combination of Intra-field and field-to-field errors. The Intra-field error includes several systematic signatures, such as overlay magnitude differences between X and Y axes, field center vs edge and more. The recent developments in scanner technology improved the intra-field Overlay to high orders. In this work we have quantified the state-of-the-art residual overlay errors and applied the RegC® (registration/overlay control) process, a new solution of deep sub-nanometer pattern shift, to further improve the overlay process control, in addition to the current lithography’s state-of-the-art capabilities. As a result we managed to reduce the baseline overlay error by more than one nanometer and reduced systematic intrafield non-uniformities, by removing the 3 sigma difference between X and Y to zero. The combination of intra-field control by RegC® with high order correction per exposure (CPE) by the scanner provides a new era of overlay control required for the 2x and 1x multiple patterning processes.

We have previously introduced a new data analysis method that more thoroughly utilizes scattered optical intensity data collected during defect inspection using bright-field microscopy. This volumetric approach allows conversion of focus resolved 2-D collected images into 3-D volumes of intensity information and also permits the use of multi-dimensional processing and thresholding techniques to enhance defect detectability. In this paper, the effects of wafer noise upon detectability using volumetric processing are assessed with both simulations and experiments using the SEMATECH 9 nm node intentional defect array. The potential extensibility and industrial application of this technique are evaluated.

Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2^nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

Historically when we used to manufacture semiconductor devices for 45 nm or above design rules, IC manufacturing yield was mainly determined by global random variations and therefore the chip manufacturers / manufacturing team were mainly responsible for yield improvement. With the introduction of sub-45 nm semiconductor technologies, yield started to be dominated by systematic variations, primarily centered on resolution problems, copper/low-k interconnects and CMP. These local systematic variations, which have become decisively greater than global random variations, are design-dependent [1, 2] and therefore designers now share the responsibility of increasing yield with manufacturers / manufacturing teams. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. The semiconductor industry is currently limited to 193 nm scanners and no relief is expected from the equipment side to prevent / eliminate these systematic hotspots. Hence we have seen a lot of design houses coming up with innovative design products to check hotspots based on model based lithography checks to validate design manufacturability, which will also account for complex two-dimensional effects that stem from aggressive scaling of 193 nm lithography. Most of these hotspots (a.k.a., weak points) are especially seen on Back End of the Line (BEOL) process levels like Mx ADI, Mx Etch and Mx CMP. Inspecting some of these BEOL levels can be extremely challenging as there are lots of wafer noises or nuisances that can hinder an inspector’s ability to detect and monitor the defects or weak points of interest. In this work we have attempted to accurately inspect the weak points using a novel broadband plasma optical inspection approach that enhances defect signal from patterns of interest (POI) and precisely suppresses surrounding wafer noises. This new approach is a paradigm shift in wafer inspection by leveraging systematic defect locations for high sensitivity inspection, thereby enhancing the discovery and monitoring of yield-limiting defects at traditional optical inspection throughput.

Scatterometry-based CD, also known as Optical CD (OCD) significantly matches CD-SEM in accuracy and precision, in addition to offering superior full-profile reconstruction. OCD, however, is computationally intensive. In this paper, we construct an extremely fast screening tool that determines whether a sample should or should not proceed to subsequent manufacturing steps. To this end we examine the diffraction signals of the grating in order to determine whether a sample is in or out of its specification limits. This allows us to allocate traditional metrology resources only on samples that show unusual behavior. Support vector machines (SVM) are trained to classify each incoming sample as in-spec or outof- spec. The constructed classifier is applied to gratings exposed with a focus-exposure matrix for a rectangular silicon- BARC-photoresist stack, which include erroneous samples with under-over exposure, necking, and bridging problems. The misclassification rates as well as false and missed alarm rates are analyzed. Results show that our prototype screening system has misclassification errors on the order of 5-10 %, while the computation time is on the order of one vector dot product.

For sub-10nm lithography for semiconductor devices, inspection technologies for detecting nanometer size defects become quite important. In the case of optical inspection, it is difficult to detect a defect whose size is less than 23nm because of optical resolution limit. This paper describes a cost-effective inspection technology for detecting a nanometer size defect with the optical inspection technology using replicated soft template which is able to enlarge a defect size by expanding. Feasibility of detecting 9.6nm defect with optical inspection is reported.

With the device dimensions moving towards the 1X node, the semiconductor industry is rapidly approaching the point where 10 nm defects become critical. Therefore, new methods for improving the yield are emerging, including inspection and review methods with sufficient resolution and throughput. Existing industrial tools cannot anymore fulfill these requirements for upcoming smaller and 3D features, since they are performing at the edge of their performance. Scanning probe microscopy (SPM) has the ability to accurately measure dimensions in the micrometer to nanometer scale. Examples of applications are surface roughness, channel height and width measurement, defect inspection in wafers, masks and flat panel displays. In most of these applications, the target area is very large, and, therefore, the throughput of the measurement plays an important role in the final production cost. Single SPM has never been able to compete with other inspection systems in terms of measurement speed, thus has not fulfilled the industry needs in throughput and cost. Further increase of the speed of the single SPM helps, but it still is far from the required throughput and, therefore, insufficient for high-volume manufacturing. Over the past three years, we have developed a revolutionary concept for a multiple miniaturized SPM heads system, which can inspect and measure many sites in parallel. The very high speed of each miniaturized SPM unit allow the user to scan many areas, each with the size of tens of micrometers, in a few seconds. This paper presents an overview of the technical developments and experimental results of the parallel SPM system for wafer and mask inspection.

With EUV lithography on the ITRS roadmap for sub-2X half-pitch patterning, it has become increasingly essential to ramp up efforts in being able to manufacture defect-free reticles or at least ones with minimal defects initially. For this purpose, much of the focus in recent years has been in finding ways to adequately detect, characterize, and reduce defects on both EUV blanks and patterned masks. For detection purposes, the current high-resolution DUV or e-beam inspection platforms are being extended to inspect EUV blanks and patterned masks but being non-actinic, make it very challenging to assess the real impact of the detected defects on EUV plane. Even with the realization of the EUV beta AIMS™ aerial-image based metrology in 2014-2015, the exact nature of each critical defect needs to be determined in order to be able to come up with an appropriate repair strategy. In this paper, we demonstrate the application of computational techniques to non-actinic supplemental metrology data collected on EUV mask defects to effectively determine the nature and also predict printability of these defects. The fundamental EUV simulation engine used in this approach is the EUV Defect Printability Simulator (DPS), which uses simulation and modeling methods designed specifically for the individual EUV mask components, and achieves runtimes several orders of magnitude faster than rigorous FDTD and RCWA methods while maintaining adequate accuracy. The EUV DPS simulator is then coupled with supplemental inspection and metrology measurements of real defects to effectively predict wafer printability of these defects. Several sources of such supplementary data are explored here, and may sometimes be dependent on the actual nature of defect. These sources include AFM height-profile data, SEM top-down images, and 193nm high-NA inspection images of single or multiple focus plane capture. From each of these supplemental data sources, the mask pattern and defect information is first extracted or recovered, and then forward-simulated in DPS to generate EUV aerial images subsequently analyzed for wafer printability. Each of the data sources have their strengths and limitations vis-à-vis use in a production pilot line. We exploit a mix and- match approach to effectively filter down to the defects that really matter. The 193nm inspection image data are readily available and although the pixel-sizes are somewhat coarse compared with the mask pattern widths, computationally predicting EUV printability off these images provides a quick filter of the obvious false and nuisance defects. SEM images on the other hand provide a much better two-dimensional top-down resolution of the patterns and hence work well for full-height excess or missing absorber defects but not so well for three-dimensional defects such as pits and bumps in the EUV multilayer or foreign material defects such as contamination. AFM height profile measurements generally provide the best available resolution on three-dimensional defects and thereby are well-suited for further simulations to EUV, however, AFM tip and image stability, and data acquisition time need to be comprehended. Computationally exploiting these supplemental defect inspection and metrology data in this mix-and-match approach effectively filters defects down to those that really matter on printed wafer. We see this approach as being vital to getting comprehensive defect learnings during the EUV pilot phase implementation and delivering well-characterized EUV masks to the wafer fab at substantially lower cost-of-ownership.

Coherent diffraction imaging (CDI) has matured into a versatile phase-contrast microscopy technique capable of producing diffraction limited images without the need for high precision focusing elements. CDI has been most appropriately applied in the EUV/X-ray region of the spectrum where imaging optics are both difficult to produce and inefficient. By satisfying basic geometric constraints (such as Nyquist sampling of scattered intensities) diffraction imaging techniques essentially replace any imaging elements with sophisticated computer algorithms. We demonstrate the utility of our CDI-based, phase-contrast EUV microscope by quantitatively imaging objects in both transmission and reflection. Patterned feature depth is obtained in transmission using keyhole coherent diffraction imaging (KCDI) and feature height is quantitatively extracted in the first general, table-top reflection mode CDI microscope.

Integrated circuits from 22nm node and beyond utilize many innovative techniques to achieve features that are well beyond the resolution limit of 193nm immersion lithography. The introduction of complex 3D structures in device design presents additional challenges that require more sophisticated metrology with high accuracy and precision. One such example is pitch walking induced by multiple-patterning techniques. Quantification of pitch walking has traditionally been a challenge. In this paper, we present two ways of detecting pitch walking using optical and X-ray techniques. In scatterometry, this work investigates the feasibility of non-orthogonal azimuth angle spectroscopic reflectometry setups for Fin pitch walking measurements, which is useful for in-line monitoring in 14nm node microelectronics manufacturing. Simulations show a significant improvement in pitch walking sensitivity using 45 degree azimuth scan. Other relevant considerations for pitch walking modeling in scatterometry, such as parameter correlations, are also discussed. Another approach is using high-resolution X-ray diffraction (HRXRD).Which is sensitive to the crystalline films. Pitch walking is seen as additional peaks in the diffraction and the intensities can be used to quantify the pitch walking. In addition, additional information about the Fin profiles, e.g. sidewall angle, CD and height, can be obtained. Note that in HRXRD measurements, all the parameters are deconvolved from the pitch walking. In this paper, we will discuss the results from measurements using the two techniques and how the combination of the two techniques can give complete information about the fins needed for in-line monitoring.

The capacity to measure nanoscale features rapidly and accurately is of central importance for the monitoring of manufacturing processes in the production of computer integrated circuits. Parameters of interest include, for example, trench depth, duty cycle, wall angle and oxide layer thickness. The measurement method proposed here uses focused beam scatterometry, in which the illumination consists of a focused field with a suitably tailored spatially-varying polarization distribution. In an analysis that is analogous to classical off-null measurements as well as weak measurements in quantum mechanics, we predict that four or more parameters can be measured and distinguished with an accuracy consistent with the needs laid out in the semiconductor roadmap.

Reducing parameter correlations to enhance scatterometry measurement accuracy, precision and tool matching is a crucial component of every modeling effort. Parameter sensitivity can largely depend on the orientation of the plane of incidence relative to the grating orientation. Conventional scatterometry is done with the plane if incidence normal to the grating orientation, whereas azimuthal scatterometry allows measurements at an arbitrary angle or set of angles. A second technique examined in this paper is hybrid metrology where inputs from source tools such as CD-SEM and CD-AFM are used to determine values of critical parameters. The first examples shows LER sensitivity gains by measuring narrow resist lines in an orientation parallel with the long axis of the grating. Hybridization of LER results in a CD and SWA FMP improvement of about 60%. We also showcase the benefits of azimuthal scatterometry measuring resist lines with CD larger than the wavelengths of the incident light. A CD and SWA FMP reduction of about 60% and 30% is obtained using azimuthal scatterometry at 0, 45 and 90 degrees azimuth angles. Hybridization of the ARC SWA after RIE results in CD and resist SWA FMP improvements by over 60% and 30%, respectively.

Monitoring and control of the various processes in the semiconductor require precise metrology of relevant features. Optical Critical Dimension metrology (OCD) is a non-destructive solution, offering the capability to measure profiles of 2D and 3D features. OCD has an intrinsic averaging over a larger area, resulting in good precision and suppression of local variation. We have studied the feasibility of process monitoring and control in AEI (after etch inspection) applications, using the same angular resolved scatterometer as used for CD, overlay and focus metrology in ADI (after develop inspection) applications¹. The sensor covers the full azimuthal-angle range and a large angle-of-incidence range in a single acquisition. The wavelength can be selected between 425nm and 700nm, to optimize for sensitivity for the parameters of interest and robustness against other process variation. In this paper we demonstrate the validity of the OCD data through the measurement and comparison with the reference metrology of multiple wafers at different steps of the imec N14 fabrication process in order to show that this high precision OCD tool can be used for process monitoring and control.

Si lattice stress at or near the surface, and overall quality of the Si surface and interface were characterized using multi-wavelength, high resolution Raman and photoluminescence (PL) spectroscopy. Depth profiling of Si lattice stress and electrically active defects/traps, at or near the Si surface and interface, was done using ultraviolet (UV) to infrared (IR) light sources, with different probing depths. Significant variations in Si lattice stress, Si bond lengths and electrically active defects/traps were found from Si wafers undergoing various process steps. Visualization of Si surface and interface quality was done on Si wafers following various device fabrication steps.

Integrated metrology in the lithography cluster is a promising solution to tighten process control. It is shown that optical CD metrology using YieldStar, an angular resolved scatterometer, meets all requirements in terms of precision, process robustness, throughput and matching to CD-SEM, the current tool-of-reference. The same metrology tool supports also diffraction-based overlay metrology. Using an appropriate sampling plan and the full scanner correction capabilities, overlay control can be improved. The throughput of the integrated tool is sufficient to support high volume sampling plans for combined CD and overlay monitoring and control, with 100% lot coverage.

The novel method of sub-nanometer uncertainty for the line width measurement and the line profile measurement using STEM (Scanning Transmission Electron Microscope) images is proposed to calibrate CD-SEM line width measurement and the standardization of line profile measurement as reference metrology. In accordance with the proposed method, we already have established the methodology of profile of Si line and photoresist feature for reference metrology. In this article, we applied the proposed method to the sidewall roughness measurement of photoresist features and line profile measurement of finFET features. Using the proposed method, specimens of photoresist feature and finFET feature are sliced as thin specimens of 100 nm thickness by FIB (Focused Ion Beam) micro sampling system. Then the cross-sectional images of the specimens are obtained by STEM and TEM. The sidewall roughness of photoresist features is estimated by the maximum slope of the image intensity graph at the edge. Then, the sidewall roughness is also measured by CD-AFM (Critical Dimension Atomic Force Microscope); we compared the results by STEM image and CD-AFM. Moreover, the line profile of finFET features is defined using TEM images for reference metrology. We compared the line width of fin measured by the proposed method and CD value by CD-SEM measurement.

For robustness improvement of inline metrology tools, we propose inline reference metrology system “Verification Metrology System (VMS)”. This system combines inline metrology tools and non-destructive reference metrology tools. VMS can detect the false alarm error and the not-detectable error caused by measurement robustness decay of inline metrology tools. GI-SAXS was selected as the inline reference metrology tool. GI-SAXS has high robustness capability for under-layer structure changes. VMS with scatterometry and GI-SAXS was evaluated for measurement robustness. The potential to detect metrology system errors was confirmed using VMS. Cost reduction effect of VMS was estimated for the false alarm case. Total cost is obtained as a sum of the false alarm loss and the metrology cost. VMS is effective for total cost reduction with low sampling. And it is important that sampling frequency of reference metrology is optimized based on process qualities.

When designing an experiment to assess the accuracy of a tool as compared to a reference tool, semiconductor metrologists are often confronted with the situation that they must decide on the sampling strategy before the measurements begin. This decision is usually based largely on the previous experience of the metrologist and the available resources, and not on the statistics that are needed to achieve acceptable confidence limits on the final result. This paper shows a solution to this problem, called inverse TMU analysis, by presenting statistically-based equations that allow the user to estimate the needed sampling after providing appropriate inputs, allowing him to make important “risk vs. reward” sampling, cost, and equipment decisions. Application examples using experimental data from scatterometry and critical dimension scanning electron microscope (CD-SEM) tools are used first to demonstrate how the inverse TMU analysis methodology can be used to make intelligent sampling decisions before the start of the experiment, and then to reveal why low sampling can lead to unstable and misleading results. A model is developed that can help an experimenter minimize the costs associated both with increased sampling and with making wrong decisions caused by insufficient sampling. A second cost model is described that reveals the inadequacy of current TEM (Transmission Electron Microscopy) sampling practices and the enormous costs associated with TEM sampling that is needed to provide reasonable levels of certainty in the result. These high costs reach into the tens of millions of dollars for TEM reference metrology as the measurement error budgets reach angstrom levels. The paper concludes with strategies on how to manage and mitigate these costs.

As overlay margins shrink for advanced process nodes, a key overlay metrology challenge is finding the measurement conditions which optimize the yield for every device and layer. Ideally, this setup should be found in-line during the lithography measurements step. Moreover, the overlay measurement must have excellent correlation to the device electrical behavior. This requirement makes the measurement conditions selection even more challenging since it requires information about the response of both the metrology target and device to different process variations. In this work a comprehensive solution for overlay metrology accuracy, used by UMC, is described. This solution ranks the different measurement setups by their accuracy, using Qmerit, as reported by the Archer 500. This ranking was verified to match device overlay using electrical tests. Moreover, the use of Archer Self Calibration (ASC) allows further improvement of overlay measurement accuracy.

Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties, several innovative resolution enhancement technologies, based on 193nm wavelength, were introduced and implemented to keep the trend of device scaling. Scanner makers keep developing state-of-the-art exposure system which guarantees higher productivity and meets a more aggressive overlay specification. “The scaling reduction of the overlay error has been a simple matter of the capability of exposure tools. However, it is clear that the scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieve the desired performance.(2)” In a manufacturing fab, the overlay error, determined by a conventional overlay measurement: by using an overlay mark based on IBO and DBO, often does not represent the physical placement error in the cell area of a memory device. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion, caused by etching or CMP, also can be a source of the mismatch. Therefore, the requirement of a direct overlay measurement in the cell pattern gradually increases in the manufacturing field, and also in the development level. In order to overcome the mismatch between conventional overlay measurement and the real placement error of layer to layer in the cell area of a memory device, we suggest an alternative overlay measurement method utilizing by design, based metrology tool. A basic concept of this method is shown in figure1. A CD-SEM measurement of the overlay error between layer 1 and 2 could be the ideal method but it takes too long time to extract a lot of data from wafer level. An E-beam based DBM tool provides high speed to cover the whole wafer with high repeatability. It is enabled by using the design as a reference for overlay measurement and a high speed scan system. In this paper, we have demonstrated that direct overlay measurement in the cell area can distinguish the mismatch exactly, instead of using overlay mark. This experiment was carried out for several critical layer in DRAM and Flash memory, using DBM(Design Based Metrology) tool, NGR2170™.

As photolithography will continue with 193nm immersion multiple patterning technologies for the leading edge HVM process node, the production overlay requirement for critical layers in logic devices has almost reached the scanner hardware performance limit. To meet the extreme overlay requirements in HVM production environment, this study investigates a new integrated overlay control concept for leading edge technology nodes that combines the run-to-run (R2R) linear or high order control loop, the periodic field-by-field or correction per exposure (CPE) wafer process signature control loop, and the scanner baseline control loop into a single integrated overlay control path through the fab host APC system. The goal is to meet the fab requirements for overlay performance, lower the cost of ownership, and provide freedom of control methodology. In this paper, a detailed implementation of this concept will be discussed, along with some preliminary results.

Shrinking wafer overlay budgets raise the importance of careful characterization and control of the contributing components, a trend accelerated by multi-patterning immersion lithography [1]. Traditionally, the mask contribution to wafer overlay has been estimated from measurement of a relatively small number of standard targets. There are a number of studies on test masks and standard targets of the impact of mask registration on wafer overlay [2],[3]. In this paper, we show the value of a more comprehensive characterization of mask registration on a product mask, across a wide range of spatial frequencies and patterns. The mask measurements will be used to obtain an accurate model to predict mask contribution to wafer overlay and correct for it.

Overlay metrology performance as Total Measurement Uncertainty (TMU), design rule compatibility, device correlation and measurement accuracy are been challenged at 2x nm node and below. Process impact on overlay metrology becoming critical, and techniques to improve measurement accuracy becomes increasingly important. In this paper, we present an innovative methodology for improving overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with least process impacts and reliable accuracies. Using the quality metric, an innovative calibration method, ASC (Archer Self Calibration) is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as CDSEM data collected on DCM (Device Correlated Metrology) hybrid target or electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. In this paper we bring an example of such use case.

While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system’s sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.

Directed self-assembly (DSA) applying chemical epitaxy is one of the promising lithographic solutions for next generation semiconductor device manufacturing. We introduced Fingerprint Edge Roughness (FER) as an index to evaluate edge roughness of non-guided lamella finger print pattern, and found its correlation with the Line Edge Roughness (LER) of the lines assembled on the chemical guiding patterns. In this work, we have evaluated both FER and LER at each process steps of the LiNe DSA flow utilizing PS-b-PMMA block copolymers (BCP) assembled on chemical template wafers fabricated with Focus Exposure Matrix (FEM). As a result, we found the followings. (1) Line widths and space distances of the DSA patterns slightly differ to each other depending on their relative position against the chemical guide patterns. Appropriate condition that all lines are in the same dimensions exists, but the condition is not always same for the spaces. (2) LER and LWR (Line Width Roughness) of DSA patterns neither depend on width nor LER of the guide patterns. (3) LWR of DSA patterns are proportional to the width roughness of fingerprint pattern. (4) FER is influenced not only by the BCP formulation, but also by its film thickness. We introduced new methods to optimize the BCP formulation and process conditions by using FER measurement and local CD valuation measurement.

Publisher’s Note: This paper, originally published on 2 April 2014, was replaced with a corrected/revised version on 14 May 2014. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

The NTD (Negative Tone Developer) process has been embraced as a viable alternative to traditionally, more conventional, positive tone develop processes. Advanced technology nodes have necessitated the adopting of NTD processes to achieve such tight design specifications in critical dimensions. Dark field contact layers are prime candidates for NTD processing due to its high imaging contrast. However, reticles used in NTD processes are highly transparent. The transmission rate of those masks can be over 85%. Consequently, lens heating effects result in a non-trivial impact that can limit NTD usability in a high volume mass production environment. At the same time, Source Mask Optimized (SMO) freeform pupils have become popular. This can also result in untoward lens heating effects which are localized in the lens. This can result in a unique drift behavior with each Zernike throughout the exposing of wafers. In this paper, we present our experience and lessons learned from lens heating with NTD processes. The results of this study indicate that lens heating makes impact on drift behavior of each Zernike during exposure while source pupil shape make an impact on the amplitude of Zernike drift. Existing lens models should be finely tuned to establish the correct compensation for drift. Computational modeling for lens heating can be considered as one of these opportunities. Pattern shapes, such as dense and iso pattern, can have different drift behavior during lens heating.

Defect review is a time consuming job. Human error makes result inconsistent. The defects located on don’t care area would not hurt the yield and no need to review them such as defects on dark area. However, critical area defects can impact yield dramatically and need more attention to review them such as defects on clear area. With decrease in integrated circuit dimensions, mask defects are always thousands detected during inspection even more. Traditional manual or simple classification approaches are unable to meet efficient and accuracy requirement. This paper focuses on automatic defect management and classification solution using image output of Lasertec inspection equipment and Anchor pattern centric image process technology. The number of mask defect found during an inspection is always in the range of thousands or even more. This system can handle large number defects with quick and accurate defect classification result. Our experiment includes Die to Die and Single Die modes. The classification accuracy can reach 87.4% and 93.3%. No critical or printable defects are missing in our test cases. The missing classification defects are 0.25% and 0.24% in Die to Die mode and Single Die mode. This kind of missing rate is encouraging and acceptable to apply on production line. The result can be output and reloaded back to inspection machine to have further review. This step helps users to validate some unsure defects with clear and magnification images when captured images can’t provide enough information to make judgment. This system effectively reduces expensive inline defect review time. As a fully inline automated defect management solution, the system could be compatible with current inspection approach and integrated with optical simulation even scoring function and guide wafer level defect inspection.

Nonlinearity and non-uniformity of phase-shifts significantly contribute to the error of the evaluated phase in phase-shifting interferometry. However, state of the art error-compensating algorithms can counteract the linear mis-calibration and first-order nonlinearity associated with the phase-shift. We describe an error expansion method that is utilized to construct a phase-shifting algorithm that can compensate the second-order nonlinearity and non-uniformity of phase-shifts. The conditions for eliminating the effect of second-order nonlinearity and non-uniformity of phase-shifts are given as a set of linear equations for the sampling amplitudes. We developed a novel 11-sample phase-shifting algorithm that can compensate for the second-order nonlinearity and non-uniformity of phase-shifts and is robust up to a 4^th harmonic. Experimental results show that the surface shape of a transparent plate could be measured with a precision of 1 nm, over the 120-mm-diameter aperture.

Evaluation of resist shrinkage and precision by critical dimension scanning electron microscope (CD-SEM) for EUV resist patterns at around 20 nm exposed by 0.33 NA EUV tool was conducted. To investigate interaction between EUV resist and electron beam, an accurate and fast measurement method of resist shrinkage was established. Our method can avoid saturation of shrinkage at large dose conditions which was a demerit in conventional method. By applying the new method, pattern size dependence of shrinkage was measured with various line and space (L/S) patterns down to 20 nm. The result shows that resist shrinkage of fine L/S EUV resist pattern largely depends on line width rather than space width. A well-known trade-off relationship between shrinkage and precision was observed for EUV resist pattern as well as ArF resist pattern. Shrinkage of 1.6 nm and precision of 0.13 nm for 18 nm EUV resist pattern were obtained at a typical CD-SEM condition. We also measured shrinkage and precision for a dense L/S pattern at various exposure focus and dose conditions using a FEM wafer to examine the impact of process variability. To investigate the influence of EUV shadowing effect, we measured them for both horizontal and vertical patterns at different slit locations in exposure field. No systematic change of shrinkage and precision was observed through exposure focus and dose in the process window across slit location for both horizontal and vertical L/S patterns.

As leading edge lithography moves to advanced nodes in high-mix, high-volume manufacturing environment, automated control of critical dimension (CD) within wafer has become a requirement. Current control methods to improve CD uniformity (CDU) generally rely upon the use of field by field exposure corrections via factory automation or through scanner sub-recipe. Such CDU control methods are limited to lithography step and cannot be extended to etch step. In this paper, a new method to improve CDU at post etch step by optimizing exposure at lithography step is introduced. This new solution utilizes GLOBALFOUNDRIES’ factory automation system and KLA-Tencor’s K-T Analyzer as the infrastructure to calculate and feed the necessary field by field level exposure corrections back to scanner, so as to achieve the optimal CDU at post etch step. CD at post lithography and post etch steps are measured by scatterometry metrology tools respectively and are used by K-T Analyzer as the input for correction calculations. This paper will explain in detail the philosophy as well as the methodology behind this novel CDU control solution. In addition, applications and use cases will be reviewed to demonstrate the capability and potential of this solution. The feasibility of adopting this solution in high-mix, high-volume manufacturing environment will be discussed as well.

The influence of metal ions within track filter on the micro-bridge defect is investigated. We focus on the chemical reaction between immersion ArF photoresist and metal ions and then try to figure out the root cause/mechanism by systematic methods and DOE splits. Micro-bridge defect is produced by immersion ArF resist and metal ions reaction. Track filter with higher level metal extract has higher probability of creating higher micro-bridge level and hence has an impact on defect density. In the experiments, different immersion ArF resists are tested. Eventually, from the outcomes we find out the trend which can well explain the hypothesis. Following the final result, we can easily make prediction before filter inline test. Moreover, optimization of our clean track performance via proper filter selection can be achieved as well. We adopt the new methodology and conclusion at current advanced node volume production. More interestingly, in the course of investigation we find out a countermeasure which can effectively reduce filter metal extract concentration and which is applicable to next generation lithography. New filter for verification is the next stage CIP(Continue Improvement Project) and we plan to start it in the near future.

Refractory compounds such as Trimethylsilanol (TMS) and other organic compounds such as propylene glycol methyl ether acetate (PGMEA) used in the photolithography area of microelectronic cleanrooms have irreversible dramatic impact on optical lenses used on photolithography tools. There is a need for real-time, continuous measurements of organic contaminants in representative cleanroom environment especially in lithography zone. Such information is essential to properly evaluate the impact of organic contamination on optical lenses. In this study, a Proton-Transfer Reaction-Time-of-Flight Mass spectrometer (PTR-TOF-MS) was applied for real-time and continuous monitoring of fugitive organic contamination induced by the fabrication process. Three types of measurements were carried out using the PTR-TOF-MS in order to detect the volatile organic compounds (VOCs) next to the tools in the photolithography area and at the upstream and downstream of chemical filters used to purge the air in the cleanroom environment. A validation and verification of the results obtained with PTR-TOF-MS was performed by comparing these results with those obtained with an off-line technique that is Automated Thermal Desorber – Gas Chromatography – Mass Spectrometry (ATD-GC-MS) used as a reference analytical method. The emerged results from the PTR-TOF-MS analysis exhibited the temporal variation of the VOCs levels in the cleanroom environment during the fabrication process. While comparing the results emerging from the two techniques, a good agreement was found between the results obtained with PTR-TOF-MS and those obtained with ATD-GC-MS for the PGMEA, toluene and xylene. Regarding TMS, a significant difference was observed ascribed to the technical performance of both instruments.

Multi-patterning is one of the commonly used processes to shrink device node dimensions. With the miniaturization of the device node and the increasing number of coated layers and lithography processes, needs for defect reduction and control are getting stronger. Although there are needs for detecting in-film defects during the lithography process, it is difficult to verify in-film defects detected by an optical inspection tool because in-film defects usually appear as SEM Non-Visuals (SNV) during defect review using a scanning electron microscope (SEM). This makes the tuning of optical inspection tools difficult since these defects may be considered as noise. However, if these defects are “real defects”, they will have a negative impact to manufacturing yield. In this paper, we investigate a new methodology to detect in-film defects with high sensitivity utilizing a broadband plasma inspection tool. This methodology is expected to allow the early detection of in-film defects before the pattern formation, hence improving device manufacturing yield.

The Double Patterning lithography (DPL) process is a well known method to overcome the k1 limit below 0.25, but the pattern final performance (OVL/CD) get more sensitive with the initial core CD uniformity, one of the main factors is across wafer CD uniformity control. Previous improvements applying scanner dose or PEB temperature multi-zone control, the others use the vacuum PEB plate design. In this study, we adopt various DPL sacrificial layers to modify wafer warpage level, it can adjust a suitable wafer warpage profile. By this method, we can achieve 30% CD uniformity improvement without the scanner dose/ PEB multi-zone heating compensation,

Next-generation lithography technology is required to meet the needs of advanced design nodes. Directed Self Assembly (DSA) is gaining momentum as an alternative or complementary technology to EUV lithography. We investigate defectivity on a 2xnm patterning of contacts for 25nm or less contact hole assembly by grapho epitaxy DSA technology with guide patterns printed using immersion ArF negative tone development. This paper discusses the development of an analysis methodology for DSA with optical wafer inspection, based on defect source identification, sampling and filtering methods supporting process development efficiency of DSA processes and tools.

Different linear patterns obtained from the directed self-assembly of the block copolymer (BCP) polystyrene-b-polyethylene oxide (PS-b-PEO) were analysed and compared. The hexagonal phase PS-b-PEO in a thin film exhibits linear pattern morphology, by conventional solvent annealing in an atmosphere saturated in chloroform. The surface energy of the silicon substrates was varied using surface functionalization of a self-assembly monolayer (SAM) and a polymer brush, chosen to investigate the influence of the surface energy on the self-assembly of the BCP. The linear patterns formed were analyzed with innovative image analysis software specifically developed in our laboratory to identify elements and defects of line arrays from block copolymer self-assembly. The technique starts by performing dimensional metrology to calculate the pitch size and estimate the linewidth of the lines. Secondly, the methodology allows identification and quantification of typical defects observable in BCP systems, such as turning points, disclination or branching points, break or lone points and end points. The defect density and the quantification of the alignment were estimated using our technique. The methodology presented here represents a step forward in dimensional metrology and defect analysis of BCP DSA systems and can be readily used to analyze other lithographic or non-lithographic patterns.

Grapho-epitaxy based hole shrink process of Directed Self-assembly (DSA) is one of the candidates for less than 30 nm hole pattern fabrication. The guide patterns of grapho-epitaxy are made by using ArF immersion scanner under the condition of near resolution limit to the 193-nm exposure. Hence, guide patterns have measurable level of edge roughness and edge placement errors. Those errors cause serious size errors and placement errors of DSA hole patterns. RED (Robust Edge Detection) is a new measurement function of CD-SEM for qualifying guide pattern shapes and DSA pattern shapes simultaneously. We also propose GBM (Grid Based Metrology) for the measurement of DSA hole's absolute placement error. In this paper, we applied the two methods for qualifying about 20 nm-node’s different polymer film thickness of DSA hole process. The DSA placement error from GBM result and relative DSA placement error obtained by RED are almost same as about 3nm (3sigma). This indicates both RED and GBM methods are correct to measure the DSA process error.

The measurement of parts-per-trillion (ppt) level acidic and basic airborne molecular contamination (AMC) is essential for process protection and yield control in semiconductor photo-lithography and adjacent applications. Real-time monitoring solutions are highly desired, as they provide instantaneous and continuous measurement. However, even the most advanced monitors cannot achieve detection limits in the low parts-per-trillion (ppt) range and many restrictions apply for the detection of acidic AMC. High cost of ownership is another disadvantage. Discontinuous sampling with sample traps is capable of achieving ppt-level measurement, but the currently accepted methods use sample traps filled with de-ionized water (impingers) to capture soluble acidic and basic AMC. Several inherent disadvantages of these methods result in inconsistent data and increased detection limits. Some proprietary solid state solutions have been reported, but involve complex preparation, have high background signals and require 24-72 hour sample duration, or they are protected trade secrets that are not available as an industry standard. To eliminate these disadvantages, we developed a liquid-free sample trap that allows parts-per-quadrillion level (ppq) measurement of acidic and basic AMC within one work shift, typically a 4-6 hour sample period. The traps can easily be manufactured and prepared in small lab operations, are sealed and protected from the outside and operator handling in the field, have months of shelf life and show high capture efficiencies while minimizing reactions and artifacts. Capacity results for the liquid-free base trap using ammonia (NH₃) as a test gas yielded more than 200 ppb-h at 100% capture efficiency without any moisture (simulating sampling of CDA or N₂) and 350 ppb-h at 40% RH. The capacity results for sulfur dioxide (SO₂) were highly dependent on moisture content of the sample gas and yielded 5 ppb-h at 90% capture efficiency and 0% RH, but increased exponentially to more than 1200 ppb-h at 40% RH. Performance testing indicates that the liquid-free trap provides both more precise and more accurate results for NH₃, SO₂ and HF in comparison to standard impinger in lab testing, with a relative standard deviation not exceeding 8% and capture efficiency greater than 95% for all three compounds. Acetic acid was the only compound that shows slightly decreased performance but still maintained a precision and accuracy comparable to the other compounds tested. In-field validation deployment to external and internal customers in parallel with standard wet impingers resulted in less than 10% difference between the traps, providing the necessary evidence that liquid-free traps are suitable for replacement of and better than wet impingers.

Monitoring airborne molecular contamination (AMC) at the parts per trillion (ppt) level in cleanroom environments, scanner applications and compressed gas lines is essential for processes, equipment and yield-control. For the operation of EUV tools, in particular, volatile organic contamination is known to have as much impact as condensable organic compounds, which requires a suitable sampling and measurement methodology. Some of the current industry standards use sample traps comprised of porous 2,6-diphenylene-oxide polymer resin, such as Tenax®, for measuring volatile organic (<6 C-atoms, approximately IPA/acetone to toluene) and condensable organic (>6 C atoms, about toluene and higher) AMC. Inherent problems associated with these traps are a number of artifacts and chemical reactions that reduce accuracy of reported organic AMC concentrations. The break-down of the polymeric material forms false positive artifacts when used in the presence of reactive gases, such as nitrous acid and ozone, which attack and degrade the polymer to form detectable AMC. Most importantly, these traps have poor capture efficiency for volatile organic compounds (VOC). To address the disadvantages of polymer-based sample traps, we developed a method based on carbonaceous, multi-layered adsorbent traps to replace the 2,6-diphenylene-oxide polymer resin sample trap type. Along with the new trap’s ability to retain volatile organics, the trap was found to provide artifact-free results. With industry trends towards detecting more contaminants while continuously reducing required reporting limits for those compounds, artifact-free and accurate detection of AMC is needed at the parts per quadrillion (ppq) level. The proposed, multi-layered trap substantially increases laboratory productivity and reduces cost by eliminating the need to analyze condensable and volatile organic compounds in two separate methods. In our studies, even some organic compounds with six C-atoms, that are part of exposure tool OEM requirements, were not effectively retained by polymeric traps, but were fully retained on the multi-layered adsorbent trap. This demonstrates that the standard trap used in the industry will result in significantly underreporting actual AMC concentrations for volatile organic compounds, including some siloxanes (TMS, HMDSO, D3). Performance of the proposed trap was excellent at both zero and 50% relative humidity, an important metric, as the trap is used for AMC detection in dry supply gases and humidified environments. Retention of all organic compounds was quantitative for more than 30 liters of air, sufficient for ppq-level detection limits. Desorption efficiency was 94% for C26 compounds. Pressure drop through the new trap was comparable to that of polymer-based traps and much lower than other, commercially available carbonaceous traps. Precision of repeated analyses was 5%, a very good result. Resolution of IPA and acetone was complete and that of a mix of halogenated refrigerants was much improved over existing methods. We propose to adopt this methodology as a new industry standard to overcome widespread inaccuracy in the reporting of volatile organic AMC and false positive condensable AMC.

The MATRIX platform integrates new types of modules for handling and alignment capability and this represents two new and innovative aspects for multi-beam lithography. Results on performances in terms of robustness of the different modules in real manufacturing conditions, including the interface of the MATRIX platform with the SOKUDO DUO track will be reported. A new type of alignment solution was developed by MAPPER. This paper will show the first results on alignment sensor repeatability. Preliminary results on the overlay performance of the MATRIX platform will be presented and discussion will be engaged to position the MAPPER alignment concept with respect to the ITRS roadmap expectations.

As design rule shrinks down, on-product focus control became more important since available depth of focus (DOF) is getting narrower and also required critical dimension uniformity (CDU) becomes tighter. Thus monitoring, control the scanner focus error and reducing the focus control budget of scanner are essential for the production. There are some critical layers which has so narrow DOF margin that hardly be processed on old model scanners. Our study mainly focused on the analysis of the scanner focus control budget of such layers. Among the contributors to the focus budget, inter-field focus uniformity was turned out to be the most dominant. Leveling accuracy and intra-field focus uniformity were also dominant.

Micro/nanotechnologies evolve causing an evolution of surface characterization systems of thin films. Today, these systems are not adapted to the future needs (or current) to characterize and qualify a large effective area within industrial production. This concerns the thin film active layers or simple mask for structuring the surface. This paper proposes a quality control method for thin films of self-assembled particles and high quality. This method is founded on the intersection of several skills available in our laboratories: Industrial process of visual inspection, optical methods for quality control (large area relative to the state of the art) and advances in micro/nanotechnology (CEA/Liten).

Photo resist micro bubble and void defect is reported as a typical and very puzzle defect type in photo lithography process, it becomes more and more significantly and severely with the IC technology drive towards 2× node. Introduced in this paper, we have studied the mechanism of photo resist micro bubble at different in-coming wafer surface condition and tested a series of pre treatment optimization method to resolve photo resist micro bubble defect on different wafer substrate, including in the standard flat and smooth wafer surface and also in special wafer surface with high density line/space micro-structure substrate as is in logic process FinFET tri-gate structure and Nor type flash memory cell area Floating Gate/ONO/Control Gate structure. As is discovered in our paper, in general flat and smooth wafer surface, the photo resist micro bubble is formed during resist RRC coating process (resist reduction coating) and will easy lead to Si concave defect after etch; while in the high density line/space micro-structure substrate as FinFET tri-gate, the photo resist void defect is always formed after lithography pattern formation and will final cause the gate line broken after the etching process or localized over dose effect at Ion IMP layers. The 2^nd type of photo resist micro bubble is much more complicated and hard to be eliminated. We try to figure out the interfacial mechanism between different type of photo resist (ArF, KrF and I-line) and pre-wet solvent by systematic methods and DOE splits. And finally, we succeeded to dig out the best solution to eliminate the micro bubble defect in different wafer surface condition and implement in the photolithography process.

There are various data mining and analysis tools in use by high-volume semiconductor manufacturers throughout the industry that seek to provide robust monitoring and analysis capabilities for the purpose of maintaining a stable lithography process. These tools exist in both online and offline formats and draw upon data from various sources for monitoring and analysis. This paper explores several possible use cases of run-time scanner data to provide advanced overlay and imaging analysis for scanner lithography signatures. Here we demonstrate several use-cases for analyzing and stabilizing lithography processes. Applications include high order wafer alignment simulations in which an optimal alignment strategy is determined by dynamic wafer selection, reporting statistics data and analysis of the lot report and the sub-recipe as a sort of non-standard lot report, visualization of key lithography process parameters, and scanner fleet management (SFM)

In this paper, we examine the sensitivity of scatterometry for the isolation mounts on the substrate by applying PML in RCWA. We analyze the reflectance from the silicon and resist single mount and the silicon double mounts on the silicon substrate. First, we investigate the mode convergences and the beam width dependences of reflectance. Second, we show the propagation properties of the electromagnetic fields propagating for the isolation mounts on the silicon substrate. Finally, we examine the wavelength properties of reflectance calculated by changing the beam width, the mount width and the mount height for single mount and the silicon mount positions for the double silicon mounts. Then, we understand that the scatterometry observation is possible in several decade microns beam width.

The manufacturing of next generation semiconductor devices forces metrology tool providers for an exceptional effort in order to meet the requirements for precision, accuracy and throughput stated in the ITRS. In the past years hybrid metrology (based on data fusion theories) has been investigated as a new methodology for advanced metrology [1][2][3]. This paper provides a new point of view of data fusion for metrology through some experiments and simulations. The techniques are presented concretely in terms of equations to be solved. The first point of view is High Level Fusion which is the use of simple numbers with their associated uncertainty postprocessed by tools. In this paper, it is divided into two stages: one for calibration to reach accuracy, the second to reach precision thanks to Bayesian Fusion. From our perspective, the first stage is mandatory before applying the second stage which is commonly presented [1]. However a reference metrology system is necessary for this fusion. So, precision can be improved if and only if the tools to be fused are perfectly matched at least for some parameters. We provide a methodology similar to a multidimensional TMU able to perform this matching exercise. It is demonstrated on a 28 nm node backend lithography case. The second point of view is Deep Level Fusion which works on the contrary with raw data and their combination. In the approach presented here, the analysis of each raw data is based on a parametric model and connections between the parameters of each tool. In order to allow OCD/SEM Deep Level Fusion, a SEM Compact Model derived from [4] has been developed and compared to AFM. As far as we know, this is the first time such techniques have been coupled at Deep Level. A numerical study on the case of a simple stack for lithography is performed. We show strict equivalence of Deep Level Fusion and High Level Fusion when tools are sensitive and models are perfect. When one of the tools can be considered as a reference and the second is biased, High Level Fusion is far superior to standard Deep Level Fusion. Otherwise, only the second stage of High Level Fusion is possible (Bayesian Fusion) and do not provide substantial advantage. Finally, when OCD is equipped with methods for bias detection [5], Deep Level Fusion outclasses the two-stage High Level Fusion and will benefit to the industry for most advanced nodes production.

Contour extraction of complicated optical proximity correction (OPC) patterns for advanced photomasks is increasingly needed in addition to the conventional mask CD measurement. The lithography simulation based on contour extraction from the SEM images on photomasks is one of the efficient methods to assure adequacy of OPC patterns. In this paper, the function of the above-mentioned contour extraction, and the performance requirements for the CD-SEM for this function using Mask CD-SEM 'Z7', the latest product of HOLON, and the scheme to correct the distortion are explained. Furthermore, the perspectives of the application of our contour extraction method are outlined.

CD-SEM is now attracting attention as a tool that can accurately measure positional error of device patterns. However, the measurement accuracy can get worse due to pattern asymmetry as in the case of image based overlay (IBO) and diffraction based overlay (DBO). For IBO and DBO, a way of correcting the inaccuracy arising from measurement patterns was suggested. For CD-SEM, although a way of correcting CD bias was proposed, it has not been argued how to correct the inaccuracy arising from pattern asymmetry using CD-SEM. In this study we will propose how to quantify and correct the measurement inaccuracy affected by pattern asymmetry.

The overlay performance and alignment strategy optimization for a triple patterning (LELELE) were studied based on the Monte Carlo simulation method. The simulated results show that all of the combined or worst case overlay, alignment strategy, mean target of the upper level, and mean tolerance of the lower level are dependent on the means of the lower level. A dynamic mean control method is proposed to be integrated into the APC system to improve the overlay performance.

As the process nodes continue to shrink, overlay budgets are approaching theoretical performance of the tools. It becomes even more imperative to improve overlay performance in order to maintain the roadmap for advance integrated circuit manufacturing. One of the critical factors in 20nm manufacturing is the overlay performance between the Middle of Line (MOL) and the Poly layer. The margin between these two layers was a process limiter, it was essential that we maintain a very tight overlay control between these layers. Due to various process and metrology related effects, maintaining good overlay control became a challenge. In this paper we describe the various factors affecting overlay performance and the measures taken to mitigate or eliminate said factors to improve overlay performance.

In advanced semiconductor N14 processes, due to the requirement of shrinking pitches for increased densities, pattern split is introduced. However, each of the two pattern split methods, SADP (Self-Aligned Double Patterning) and LELE (Litho-Etch-Litho-Etch), can incur process variations that might cause “pitch walk” [1, 3]. Pitch walk is a by-product of line critical dimension (CD) and spacer error (in SADP) or overlay variations (in LELE). Pitch walk not only results in different line and spaces but also affect the later steps, for example, different etched depths due to loading effects. Because of those behaviors, it is therefore a requirement to control the CD for better uniformity. This paper demonstrates how to use SCD (Scatterometry Critical Dimension) metrology tools to measure the different critical dimensions and spaces to control CD and overlay at the same process step [2]. Traditionally, wafers have to go through both a CD metrology tool and an overlay tool in order to verify CD uniformity and grid uniformity. The methodology introduced in this paper can efficiently shorten cycle time since only the CD metrology tool will be used to verify both CD and overlay. SpectraShape™ is a proven optical CD platform based on spectroscopic ellipsometry and reflectometry. In optical model type metrology, pitch walk can be a challenging parameter to measure due to inherent low sensitivity. Hence this study is performed on the newest generation system, the SpectraShape™ 9010. A new, laser driven light source [4] on this SCD tool provides higher light intensity, producing better signal-to-noise ratios for critical device parameters. This paper explores the use of SCD to measure both resist and hard mask CD in a single step. In addition, results will be presented on using SCD to measure pitch walk, typically a low sensitivity parameter for optical CD metrology tools.

In General, OLED, LCD, TSP Glass TFT Pattern consists of multi-layer of electrodes separated by a thin insulating film and layers are very close to each other. The inspection of electrode pattern and defect in multilayered devices by using visible light (550nm around) image is too much difficult to define its critical shape among layers, because of deep depth range in conventional optics of moderate numerical aperture (NA). To increase image contrast between materials and layers, this study uses UV wavelength that has larger selective differences of reflectance than visible light. Newly developed optical system and image analysis units are focused to the proper inspection wavelength at the specific UV range to clearly define a top electrode layer and reduce image processing time. To detect defects on the electrode, the resolution of the optical system should be much higher than the spatial frequency of the electrode size. After considering system requirements, two types of different magnification systems (1.2X and 3X) are developed. Direct side illumination is available in 1.2X system which has large back focal length, however, 3X system needs on axis illumination. Line beam illumination from the multi-point LED source (custom made) is used to increase the light efficiency and decrease noise⁽⁴⁾. Illumination beam passing through the common objective lens (in front of imaging optics) and illumination optics (including cylinder lens) can realized uniform intensity of one dimensional Fourier plane on the surface of target electrode. Electric units for high speed data processing and transfer and image processing algorithm are also developed. For processing large capacity image data (8 GB) synchronized with moving sensors in real time, embedded system with hardware optimizing design and FPGA module camera are adopted. Final image shows good selective contrast and resolution between layers even in the high depth condition followed by required NA for the target resolution. This inspection system can be used in inspection of PCB Pattern, LCD, OLED and Mobile Glass including many other film and glass.

Optical critical dimension (OCD) metrology using scatterometry has been widely adopted for fast and non-destructive in-line process control and yield improvement. Recently there has been increased interest in metrology performance enhancement through a holistic approach. We investigate the benefits of feed-forward of metrology information from prior process steps using samples from magnetic hard disk drive manufacturing. The scatterometry targets are composed of rather isolated gratings that are designed to have better correlation with device features. Two gratings, one with pitch ≈ 10CD, and the other with pitch ≈ 15CD, are measured at post develop and post reactive ion etch (RIE) steps. Two methods: parameter feed-forward (PFF) and spectrum feedforward (SFF) are studied in which the measurement results or spectrum collected on the blanket target at photo step are fed forward to the measurements on the grating structures at post develop or post RIE step. Compared with standard measurement without FF, for the more isolated grating at photo step, both PFF and SFF improve CD correlation from R²=0.96 to R²=0.975 using CD-SEM results measured on device as the reference. Dynamic precision and fleet measurement precision are improved by 20-60%. For post RIE step, PFF and SFF significantly improve CD correlation from R²=0.95, slope=1.09 to R²=0.975, slope=1.03 for the denser grating, and from R²=0.90, slope=0.79 to R²=0.96, slope=0.96 for the more isolated grating. Dynamic precision is generally improved by 20-40%. It is observed that both PFF and SFF are equally efficient in reducing parameter correlation for the application studied here.

Directed self-assembly (DSA) is being actively investigated as a potential patterning solution for future generation devices. While SEM based CD measurement is currently used in research and development, scatterometry-based techniques like spectroscopic CD (SCD) are preferred for high volume manufacturing. SCD can offer information about sub-surface features that are not available from CD-SEM measurement. Besides, SCD is a non-destructive, high throughput technique already adopted in HVM in several advanced nodes. The directed self assembly CD measurement can be challenging because of small dimensions and extremely thin layers in the DSA stack. In this study, the SCD technology was investigated for a 14 nm resolution PS-b-PMMA chemical epitaxy UW process optimized by imec. The DSA stack involves new materials such as cross-linkable polysterene (XPS) of thickness approximately 5 nm, ArF immersion resist (subsequently removed), -OH terminated neutral brush layer, and BCP material (Polystyrene-blockmethyl methacrylate of thickness roughly 20 to 30 nm). The mask contains a large CD and pitch matrix, for studying the quality of self-assembly as a function of the guide pattern dimensions. We report on the ability of SCD to characterize the dimensional variation in these targets and hence provide a viable process control solution.

We have developed a practicable measurement technique that can help to achieve reliable inspections for systematic defects in advanced semiconductor devices. Systematic defects occurring in the design and mask processes are a dominant component of integrated circuit yield loss in nano-scaled technologies. Therefore, it is essential to ensure systematic defects are detected at an early stage of wafer fabrication. In the past, printed pattern shapes have been evaluated by human eyes or by taking manual critical dimension (CD) measurements. However, these operations are sometimes unstable and inaccurate. Last year, we proposed a new technique for taking measurements by using a SEM contour [1]. This technique enables a highly precise quantification of various complex 2D shaped patterns by comparing a contour extracted from a SEM image using a CD measurement algorithm and an ideal pattern. We improved this technique to enable the carrying out of inspections suitable for every pattern structure required for minimizing the process margin. This technique quantifies a pattern shape of a target-layer pattern using information on a multi-layered circuit structure. This enabled it to confirm the existence of a critical defect in a circuit connecting upper/lower-layers. This paper describes the improved technique and the evaluation results obtained in evaluating it in detail.

In lithography, overlay control is getting increasingly complex. Advanced Process Control (APC) is introduced to minimize excursions from the process window for the present exposure. APC uses metrology data of previously exposed wafers, hence, there is always a delay of tens of minutes before the required information is available. This paper proposes the combination of a patterned expose beam and a patterned fluorescent marker on a wafer to generate a fluorescent signal that carries real-time information of the focus and/or position error of the expose pattern with the pattern on the wafer. A practical realization requires some changes to the exposure process, stepper design and reticle lay-out. Firstly, a matched pair of markers on the wafer and reticle is required. Secondly, the generated fluorescent signal must be measured, for example with a (spectrally filtered) photon counter close to the expose area of the wafer. At last, the markers from the previous lithography step shall, after development, be filled with fluorescent material. This deposition requires an additional process step. Photon budget calculations suggest an overlay measurement accuracy of less than a tenth of a nm (real-time).

As design rules of advance devices shrink down, not only process-window budget of lithography process is getting tighter, but also CD control to target is more important especially for multiple tool process environment in HVM (High Volume Manufacturing). The tool induced CD bias or CD difference between tools are derived by minute amount of residual imaging parameters even though with strict control in system. The tool to tool CD mismatch is able to be reduced to nanometer or sub-nanometer scale for critical features of concern by using released tools such as LithoTuner PMFC^TM (Pattern Matcher Full Chip). During the matching process, tunable imaging parameters such as pupil shape and stage tilt can be used as matching knobs. In this paper, CD mismatch due to film stack change on same exposure tool was studied to check feasibility of PMFC application. Also, CD variation and its impact on CD mismatch by focus error as amount of intrinsic system was investigated as well. By considering the focus impact on CD proximity bias via simple mathematical ways, the CD matching process could be more accurately performed and verified.

Persistently shrinking design rules and increasing process complexity require tight control and monitoring of the exposure tool parameters [1, 2]. While control of exposure dose by means of resist single metric measurements is common and widely adopted. Focus assessment and monitoring are usually more difficult to achieve. A diffused method to determine process specific dose and focus conditions is based on plotting Bossung curves from single CD-SEM measurements and choosing the best focus setting to obtain the desired target CD with the widest useful window. With this approach there is no opportunity to build a data flow architecture that can enable continuous focus monitoring on nominal production wafers [3-5]. KLA-Tencor has developed a method to enable in-line monitoring of scanner focus on production wafers by measuring resist profile shapes on grating targets using scatterometry, and analyzing the information using AcuShape^TM and K-T Analyzer^TM software. This methodology is based on a fast and robust determination of best scanner focus by analyzing focus-exposure matrices (FEMs). This paper will demonstrate the KT CDFE and FEM Analysis methods and their application in production environment.

Defect classification and characterization on mask substrates and blanks can be used to the identify defect sources within the tool and process. Defect reduction has been achieved in SEMATECH’s EUV Mask Blank Development Center (MBDC), aided by successful classifications of defect populations. Failure analysis of EUV substrate and blank defects in the MBDC begins with automatic classification of defects detected by M1350 and M7360 Lasertec inspection tools. Two sets of defect images and classification emerge from the two detection tools. The M1350 provides a more variegated set of 13 defect class types, while the M7360 provides eight. During manual review of the classifications, the defect class sets for both tools are often collapsed to only two major classes of interests with respect to production and failure analysis: particles and pits. This leaves various other classes ignored before subsequent characterization steps like SEM classification and composition analysis. The usefulness of tracking and verifying more detailed classes of defect needs to be explored. SEM analysis can be used to validate the relative size comparison yielded from inspection data alone, beyond the calibrated comparison of inspection signals from well-understood polystyrene latex spheres. The accuracy of rule-based defect classification of inspection tool data must be quantified by statistical tracking and validation SEM analysis. Classification of false counts increases as sensitivity of detection tools are increased to ensure the capture of smallest defects. The validity of calling a defect “false” is usually a manual review of pixel images created on the detection tool.

The purpose of this study is to understand EUV+SADP defectivity in 15nm line and space (L&S) pattern, and to examine bright-field inspection capabilities at the 1Xnm node. Programmed defects of known size, shape, and location were printed in dense patterned areas using EUV lithography at IMEC. To track these defects throughout development, a defectivity study was conducted using bright-field inspection after four SADP processing steps. The smallest defect routinely detected had a programmed size of 14nm, and the defect signal was enhanced using polarized light. By comparing defect locations at the beginning and end stages of development, it was found that 95% of defects remained the same. This illustrates the importance of post-lithography wafer inspection. This research shows how defect characteristics on the EUV mask affect the final pattern and demonstrate the sensitivity of bright-field inspection at the 1Xnm node.

Advanced IC fabs must inspect critical reticles on a frequent basis to ensure high wafer yields. These necessary requalification inspections have traditionally carried high risk and expense. Manually reviewing sometimes hundreds of potentially yield-limiting detections is a very high-risk activity due to the likelihood of human error; the worst of which is the accidental passing of a real, yield-limiting defect. Painfully high cost is incurred as a result, but high cost is also realized on a daily basis while reticles are being manually classified on inspection tools since these tools often remain in a non-productive state during classification. An automatic defect analysis system (ADAS) has been implemented at a 20nm node wafer fab to automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this paper, we have studied and present results showing the positive impact that an automated reticle defect classification system has on the reticle requalification process; specifically to defect classification speed and accuracy. To verify accuracy, detected defects of interest were analyzed with lithographic simulation software and compared to the results of both AIMS™ optical simulation and to actual wafer prints.

Accurate and fast kernel-based proximity effect correction (PEC) models are indispensable to full-chip proximity effect simulation and correction. The attempt to utilize optical scatterometers for PEC model calibration instead of scanning electron microscopes is primarily motivated by the fact that scatterometry can be faster, more stable, and more informative if carefully implemented. Conventional scatterometry measures periodic patterns and retrieves their dimensional parameters by solving inverse problems of optical scattering with predefined libraries of the periodic patterns. PEC model parameters can be subsequently calibrated with the retrieved dimensional parameters. However, measuring only periodic patterns limits the usage of scatterometry, and the dimensional reconstruction is prone to generate estimation errors for patterns with complex three-dimensional geometry. Previously, we have proposed directly utilizing scattering light for PEC model calibration without the need for the intermediate step of retrieving the dimensional parameters. By iteratively comparing scattered light from predefined calibration patterns measured by a scatterometer to that predicted by the corresponding scattering and lithography models, PEC model parameters can be effectively calibrated with standard numerical optimization algorithms and one-dimensional periodic patterns. In this work, two-dimensional periodic circuit layouts are designed and utilized to study the applicability and potential limitations of the proposed method on the lithography of practical circuit designs.

The background in simple dark field particle inspection shows a high scatter variance which cannot be distinguished from signals by small particles. According to our models, illumination from different azimuths can reduce the background variance. A multi-azimuth illumination has been successfully integrated on the Rapid Nano particle scanner. This illumination method reduces the variance of the background scattering on substrate roughness. It allows for a lower setting of the detection threshold, resulting in a more sensitive inspection system. By implementing this system the lower detection limit of the scanner was reduced from 59 nm to 42 nm LSE. A next improvement, a change of the inspection wavelength to 193 nm will bring the detection limit to sub 20 nm.

Optical metrology system is used as high sampling CD measurement. The optical measurement technology using Fourier image can obtain much information with various optical conditions. We evaluated Fourier image method for CD metrology. Various issues of the optical measurement technology were found for CD measurement uncertainty. Measurement uncertainty depends on the number of position on Fourier image, and measurement uncertainty is improved by using multiple positions data. Top CD value is influenced by under layer pattern CD variance and under layer thickness variance. Optical CD measurement technology is influenced by various process variation like under-layer structure, stacked film thickness, material changes and so on. If optical measurement system applies to CD metrology, Fourier image method should be used in development phase for unfixed process because high number of data and speedy process feedback in no under layer situation is needed.

A virtual multiple-input multiple-output (VMIMO) architecture is proposed recently, which allows cooperatively data exchange among each node in a sensor network. We consider to apply the adaptive filter to design a VMIMO receiver. In order to improve the convergence problem and reduce the complexity of the scalar-form Affine Projection (AP), the method of set-membership filtering (SMF) is applied to the Affine Projection adaptive algorithms. Simulation results show that the SMF is able to reduce the computational complexity effectively and achieves a better performance.

Phase Shift Focus Monitor (PSFM) has been successfully utilized as a focus monitoring tool for scanners and steppers from the g-line era to the most advanced immersion technology nodes. PSFM exhibits high sensitivity, linearity and repeatability for immersion scanners with the illumination conditions of conventional mode and NA0.93. A microlithography model was created using Hyperlith to study the PSFM sensitivity and linearity under the conditions of OAI (off-axis illumination) and high NA (0.95~1.35). The model predicts that a PSFM sensitivity of 700 ~ 1000 nm/um can be achieved when an OAI, 40 nm PSFM target and NA 1.35 are used. The model also studied the influence of various parameters on PSFM sensitivity and linearity. Wafer data verified the simulation results. PSFM linear focus range with the NA1.35 condition is shorter than that of NA0.93. The influence of illumination conditions on PSFM, such as OAI modes (annular, Quadra), NA / Sigma values and PSFM target sizes, has also been investigated by the microlithography model.

In this paper we describe the joint development and optimization of the critical dimension uniformity (CDU) at an advanced 300 mm ArFi semiconductor facility of SK Hynix in the high volume device. As the ITRS CDU specification shrinks, semiconductor companies still need to maintain high wafer yield and high performance (hence market value) even during the introduction phase of a new product. This cannot be achieved without continuous improvement of the on-product CDU as one of the main drivers for yield improvement. ASML Imaging Optimizer is one of the most efficient tools to reach this goal. This paper presents experimental results of post-etch CDU improvement by ASML imaging optimizer for immature photolithography and etch processes on critical features of 20nm node. We will show that CDU improvement potential and measured CDU strongly depend on CD fingerprint stability through wafers, lots and time. However, significant CDU optimization can still be achieved, even for variable CD fingerprints. In this paper we will review point-to-point correlation of CD fingerprints as one of the main indicators for CDU improvement potential. We will demonstrate the value of this indicator by comparing CD correlation between wafers used for Imaging Optimizer dose recipe development, predicted and measured CDU for wafers and lots exposed with various delays ranging from a few days to a month. This approach to CDU optimization helps to achieve higher yield earlier in the new product introduction cycle, enables faster technology ramps and thereby improves product time to market.

The continual increasing demands upon Plasma Etching systems to self-clean and continue Plasma Etching with minimal downtime allows for the examination of SiCN, SiO2 and SiN defectivity based upon Surface Scanning Inspection Systems (SSIS) wafer scan results. Historically all Surface Scanning Inspection System wafer scanning recipes have been based upon Polystyrene Spheres wafer deposition for each film stack and the subsequent creation of light scattering sizing response curves. This paper explores the feasibility of the elimination of Polystyrene Latex Sphere (PSL) and/or process particle deposition on both filmed and bare Silicon wafers prior to Surface Scanning Inspection System recipe creation. The study will explore the theoretical maximal Surface Scanning Inspection System sensitivity based on PSL recipe creation in conjunction with the maximal sensitivity derived from Bidirectional Reflectance Distribution Function (BRDF) maximal sensitivity modeling recipe creation. The surface roughness (Root Mean Square) of plasma etched wafers varies dependent upon the process film stack. Decrease of the root mean square value of the wafer sample surface equates to higher surface scanning inspection system sensitivity. Maximal sensitivity SSIS scan results from bare and filmed wafers inspected with recipes created based upon Polystyrene/Particle Deposition and recipes created based upon BRDF modeling will be overlaid against each other to determine maximal sensitivity and capture rate for each type of recipe that was created with differing recipe creation modes. A statistically valid sample of defects from each Surface Scanning Inspection system recipe creation mode and each bare wafer/filmed substrate will be reviewed post SSIS System processing on a Defect Review Scanning Electron Microscope (DRSEM). Native defects, Polystyrene Latex Spheres will be collected from each statistically valid defect bin category/size. The data collected from the DRSEM will be utilized to determine the maximum sensitivity capture rate for each recipe creation mode. Emphasis will be placed upon the sizing accuracy of PSL versus BRDF modeling results based upon automated DRSEM defect sizing. An examination the scattering response for both Mie and Rayleigh will be explored in relationship to the reported sizing variance of the SSIS to make a determination of the absolute sizing accuracy of the recipes there were generated based upon BRDF modeling. This paper explores both the commercial and technical considerations of the elimination of PSL deposition as a precursor to SSIS recipe creation. Successful integration of BRDF modeling into the technical aspect of SSIS recipe creation process has the potential to dramatically reduce the recipe creation timeline and vetting period. Integration of BRDF modeling has the potential to greatly reduce the overhead operation costs for High Volume Manufacturing sites by eliminating the associated costs of third party PSL deposition.

In this paper, set of wafers with separated processes was prepared and overlay measurement result was compared in two methods; IBO and DBO. Based on the experimental result, theoretical approach of relationship between overlay mark deformation and overlay variation is presented. Moreover, overlay reading simulation was used in verification and prediction of overlay variation due to deformation of overlay mark caused by induced processes. Through this study, understanding of individual process effects on overlay measurement error is given. Additionally, guideline of selecting proper overlay measurement scheme for specific layer is presented.