This PDF file contains the front matter associated with SPIE Proceedings Volume 9052, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

The optimization of illumination in optical lithography has been central to the progress toward λ/5 resolution now commonplace. The tailoring of source shapes to meet increasing demands of imaging has been commercially practiced for over twenty years. The influence of illumination in microscopy and micrography had been explored for centuries before an adequate description was developed in the late nineteenth century. By the mid-twentieth century, the mathematical foundation for the dependency of resolution on illumination was presented, leading to the parameterization of illumination through a partial coherence factor (σ). The role of partial coherence in microscopy, micrography, and microlithography has been critical to the extension of resolution in each of these fields and has allowed for the application of optical lithography toward sub-50nm resolution. Today, source customization, polarized illumination, and source/mask domain co-optimization have become critical tools used to achieve manufacturable lithography resolution at the edge of physical limits. This paper will provide a historical look into how illumination, partial coherence, and source shaping has influenced optical lithography. Aspects relative to future lithography generations are also explored, including illumination influences with 3D effects especially important for EUV wavelength applications.

With Critical Dimension Uniformity requirements in optical lithography getting tighter and tighter, phenomena that previously could be ignored now need a detailed understanding and control strategy. Amongst those are the effects introduced by the finite height of the mask absorber (Mask 3D) and the finite resist height (Resist 3D). We will explain them by analyzing wafer Critical Dimension (CD) data through focus and dose and categorizing those using simple figures of merit: Best focus differences between features, Bossung tilt through focus and sidewall angle through dose. We will study the phenomena and show a methodology and gauges to discriminate between Mask 3D and Resist 3D. This will enable the end-user to judge the effects, which are highly application dependent, and choose to put the effort for future nodes either on Mask 3D or Resist 3D or both. In the second part we will focus on the solutions. The main focus is on immersion lithography we but will show the extendibility of some of the work to EUV.

The ability to incorporate topographic and other effects of previously patterned layers in ground rule formulation could potentially lead to significant cost savings and shortened time needed for technology ramp-up. The effect of topgraphy coupled with the diminishing depth of focus (DOF) associated with design node shrinks could become a significant yield detractor. With migration of transistor architecture from planer CMOS to 3-D FINFETs, such topographic effect could potentially pose a major challenge for future EUV processes even with significantly lower NA (Numerical Aperture) compared to current immersion DUV processes. We review how resist parameters for a given layer can be optimized to minimize imaging artifacts caused by underlying topography of previous layers. We also demonstrate how residual effects after resist parameter optimization could be handled by a sets of interlayer groundrules or novel OPC methods. Initially we study standard immersion ArF processing, then we extend the methodology to evaluate the potential issues with EUV lithography in the presence of topography. We compare the the nature and magnitude of the topography effects of such results with DUV imaging and show how we can design a new resist system to minimize such effects. We also show how future ground rule development might need to incorporate the layout information of the previously patterned layers.

The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.

Advances on techniques that enable small technology nodes printing benefit the lithography with cost. For instance, lens heating draws people's attention when the NTD process is applied together with the bright tone mask. And the study of it requires the investigation of many other variables. In this paper we examine individual impact of several closely related process variables to understand the lens heating behavior. Meanwhile, though it is known that the PTD process is less sensitive to the lens heating effect, we do observe mask topography induced best focus shifts among different patterns with small spaces. It is of interest to discover the extent to which the NTD is affected. Thus in this paper we also compared the two processes with respect to the mask topography effect by simulating the best focus shifts of a series of test patterens.

Due to the importance of errors in lithography scanners, masks, and computational lithography in low-k1 lithography, application software is used to simultaneously reduce them. We have developed “Masters” application software, which is all-inclusive term of critical dimension uniformity (CDU), optical proximity effect (OPE), overlay (OVL), lens control (LNS), tool maintenance (MNT) and source optimization for wide process window (SO), for compensation of the issues on imaging and overlay. In this paper, we describe the more accurate and comprehensive solution of OPE-Master, LNS-Master and SO-Master with functions of analysis, prediction and optimization. Since OPE-Master employed a rigorous simulation, a root cause of error in OPE matching was found out. From the analysis, we had developed an additional knob and evaluated a proof-of- concept for the improvement. Influence of thermal issues on projection optics is evaluated with a heating prediction, and an optimization with scanner knobs on an optimized source taken into account mask 3D effect for obtaining usable process window. Furthermore, we discuss a possibility of correction for reticle expansion by heating comparing calculation and measurement.

For future printing based on multiple patterning and directed self-assembly, critical dimension and overlay requirements become tighter for immersion lithography. Thermal impact of exposure to both the projection lens and reticle expansion becomes the dominant factor for high volume production. A new procedure to tune the thermal control function is needed to maintain the tool conditions to obtain high productivity and accuracy. Additionally, new functions of both hardware and software are used to improve the imaging performance even during exposure with high-dose conditions. In this paper, we describe the procedure to tune the thermal control parameters which indicate the response of projection lens aberration and reticle expansion separately. As new functionalities to control the thermal lens aberration, wavefront-based lens control software and reticle bending hardware are introduced. By applying these functions, thermal focus control can be improved drastically. Further, the capability of prediction of reticle expansion is discussed, including experimental data from overlay exposure and aerial image sensor results.

The extension of 193nm immersion lithography to the 14nm node and beyond directly encounters a significant reduction in image quality. One of the consequences is that the resist profile varies noticeably, impacting the already limited process window. Resist top-loss, top-rounding, T-top and footing all play significant roles in the subsequent etch process. Therefore, a reliable rigorous model with the capability to correctly predict resist 3D (R3D) profiles is acquiring higher importance. In this paper, we will present a calibrated rigorous model of a negative-tone develop resist. Resist profiles can be well simulated through focus and dose, and cases that match well to the experimental wafer data are validated. Such a model can not only provide early investigation of insights into process limitation and optimization, but can also complement existing OPC models to become R3D-aware in process development.

From 28 nm technology node and below optical proximity correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for ionic implantation layers. These effects are complex, especially when multiple sub layers have to be considered: for instance active and poly structures need to be accounted for. A new model form has been developed to address this wafer topography during model calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification (using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction and verification. This paper discusses an exploration of this new model results using extended wafer measurements (including SEM). Current results show good accuracy on various representative structures.

Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm- STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of <1% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as ~0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of >20 % from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to ~0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 % and high-quality (1.1×105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm- or standard 193nmbased patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.

We introduce a complete methodology for process window optimization in proximity mask aligner lithography. The commercially available lithography simulation software LAB from GenISys GmbH was used for simulation of light propagation and 3D resist development. The methodology was tested for the practical example of lines and spaces, 5 micron half-pitch, printed in a 1 micron thick layer of AZ^® 1512HS¹ positive photoresist on a silicon wafer. A SUSS MicroTec MA8 mask aligner, equipped with MO Exposure Optics^® was used in simulation and experiment. MO Exposure Optics^® is the latest generation of illumination systems for mask aligners. MO Exposure Optics^® provides telecentric illumination and excellent light uniformity over the full mask field. MO Exposure Optics® allows the lithography engineer to freely shape the angular spectrum of the illumination light (customized illumination), which is a mandatory requirement for process window optimization. Three different illumination settings have been tested for 0 to 100 micron proximity gap. The results obtained prove, that the introduced process window methodology is a major step forward to obtain more robust processes in mask aligner lithography. The most remarkable outcome of the presented study is that a smaller exposure gap does not automatically lead to better print results in proximity lithography - what the “good instinct” of a lithographer would expect. With more than 5'000 mask aligners installed in research and industry worldwide, the proposed process window methodology might have significant impact on yield improvement and cost saving in industry.

In recent years, the demand for high sensitivity image sensors has become prominent, in correlation with the reduction of pixel size and higher pixel counts. Sensitivity is especially important for mobile applications and as a result, back side illumination (BSI) structure image sensors are emerging. The spread of BSI image sensors causes new technological challenges in the lithographic process. One of the challenges is related to the wafer distortion created during the bonding and thinning of the wafer. The challenge is to reduce the impact of the wafer distortion on the overlay accuracy, and we propose two unique solutions for this challenge: Extended Advanced Global Alignment (EAGA) and Shot Shape Compensator (SSC). EAGA is an alignment measurement function that can measure the position and shape of all shots on the wafer. SSC is an exposure function that adjusts the shape of exposure shots according to the shape of the underlying layer's shot on the distorted wafer, by controlling both the XY magnification difference and skew component of the projection optical system. In order to realize the SSC system in i-line stepper, Canon has introduced a new compensation mechanism featuring “two-dimensional Alvarez” optical elements. One other challenge is to detect alignment marks located on the back surface of the silicon wafer and for this challenge, Canon has employed a new alignment system using infrared light. In this paper, we will provide detailed descriptions along with exposure results using these solutions. We will also delve into the possibility of additional process applications that can benefit from the enhanced overlay accuracy provided by Canon i-line lithography systems.

Cost effective micro lithography tool is demanded for fine micro devices. However, resolution of a conventional proximity exposure system is not sufficient below several micron feature size for deep focus depth. On the other hand, a reduction projection system is sufficient to resolve it but the cost of the tool is too much high compared to proximity exposure systems. To enhance the resolution of photolithography, there has been proposed a number of novel methods beside shorting of wave length. Some of them are utilized in current advanced lithography systems, for example, the immersion lithography¹ enhances effective NA and the phase shift mask² improves optical transmittance function. However, those advanced technology is mainly focused on improvement for advanced projection exposure systems for ultra-fine lithography. On the other hand, coherence holography pattering is recently proposed and expected for 3-dimentional pattering^3-5. Also, Talbot lithography^6-8 is studied for periodical micro and nano pattering. Those novels pattering are based on wave propagation due to optical diffraction without using expensive optical lens systems. In this paper we newly propose novel optical lithography using built-in lens mask to enhance resolution and focus depth in conventional proximity exposure system for micro lithographic application without lens systems. The performance is confirmed by simulation and experimental works.

It is desired to reduce the time required to produce metrology data for calibration of Optical Proximity Correction (OPC) models and also maintain or improve the quality of the data collected with regard to how well that data represents the types of patterns that occur in real circuit designs. Previous work based on clustering in geometry and/or image parameter space has shown some benefit over strictly manual or intuitive selection, but leads to arbitrary pattern exclusion or selection which may not be the best representation of the product. Forming the pattern selection as an optimization problem, which co-optimizes a number of objective functions reflecting modelers’ insight and expertise, has shown to produce models with equivalent quality to the traditional plan of record (POR) set but in a less time.

In this paper, we develop a novel fracturing algorithm with shot overlap that is tailored towards rectilinear masks, such as those generated via edge based OPC software. Our proposed fracturing algorithm generates both the location and dosage of shots given the mask layout and mask making parameters. In the first step we heuristically cover the mask polygon with overlapping shots. Next, we incorporate the forward scattering and resist model in a least squares problem to compute the best dosage for all shots. Finally, we update the locations of the shot edges by computing the edge placement error between our simulated contour and the desired contour. One unique feature of our algorithm is that it can readily trade off between edge placement error and shot count by adjusting two input parameters. Compared to a commercially available non-overlapping shot software package, for a 400μm×400μm micron SRAM unit with about 1 million polygons, our algorithm results in a 23% reduction in shot count, while increasing the weighted average EPE from 0.7 to 1 nanometers.

CMOS logic at the 22nm node and below is being done with a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes have been demonstrated using a “lines and cuts” approach with good pattern fidelity and process margin, with extendibility to ~7nm.[1] In previous studies, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 12nm node.[2,3,4,5,6] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[3,7,8] This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In our present work, we extend the scaling using SMO with “OPC Lite” beyond 12nm. The focus is on the contact pattern since a “hole” pattern is similar to a “cut” pattern so a similar technique should be useful. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous studies. The contact pattern is a relatively dense layer since it connects two underlying layers – active and gate – to one overlying layer – metal-1. Several design iterations were required to get suitable layouts while maintaining circuit functionality. Experimental demonstration of the contact pattern using OPC-Lite will be presented. Wafer results have been obtained at a metal-1 half-pitch of 18nm, corresponding to the 11nm CMOS node. Additional results for other layers – FINs, local interconnect, and metal-1 – will also be discussed.

In the traditional OPC (Optical Proximity Correction) procedure, edges in a layout are broken into fragments and each fragment is iteratively adjusted by multiplying its EPE (Edge Placement Error) with a carefully selected or calculated feedback. However, the ever-shrinking technology nodes in recent years bring stronger fragment to fragment interaction. The feedback tuning approach driven by a single fragment EPE is no longer sufficient to achieve good pattern fidelity with reasonable turn-around-time. Various novel techniques such as matrix OPC [1, 2] have been developed in the past to incorporate the influence of neighboring fragments into each fragment’s movement. Here we introduce a neighboraware feedback controller for full chip level OPC applications, following the concept and algorithms of the matrix OPC that were laid out in Cobb and Granik’s work [1]. We present experimental results and discuss the benefits and challenges of the proposed feedback controller.

This paper investigates the possibility of 193 nm immersion lithography extensions to sub-10 nm technology nodes using the patterning scheme of unidirectional (1D) grating lines and cuttings. Technological feasibility down to 5 nm nodes is examined with experimental data of self-aligned multiple patterning method (SAxP) and Litho-Etch (LE) cuttings. For the cutting by LE repetition, relationship between node definition and the repetition number n (LE^n) is discussed. Cost is evaluated for SADP, SAQP and SAOP to generate unidirectional grating formation, and the following LE^n cutting process. Finally, schemes of gridded cutting and trim are introduced, and found to be advantageous to keep the scaling merit of transistor cost at 7 and 5 nm technology nodes.

As we advances into 14/10nm technology node, single patterning technology is far from enough to fabricate the features with shrinking feature size. According to International Technology Roadmap for Semiconductors in 2011,¹ double patterning lithography is already available for massive productions in industry for sub-32nm half pitch technology node. For 14/10nm technology node, double patterning begins to show its limitations as it uses too many stitches to resolve the native coloring conflicts. Stitches will increase the manufacturing cost, lead to potential functional errors of the chip, and cause the yield lost. Triple patterning lithography and E-Beam lithography are two emerging techniques to beat the diffraction limit for current optical lithography system. In this paper, we investigate combining the merits of triple patterning lithography and E-Beam lithography for standard cell based designs. We devise an approach to compute a stitch free decomposition with the optimal number of E-Beam shots for row structure layout. The approach is expected to highlight the necessity and advantages of using hybrid lithography for advanced technology node.

A Metal1-layer (M1) patterning study is conducted on 20nm node (N20) for random-logic applications. We quantified the printability performance on our test vehicle for N20, corresponding to Poly/M1 pitches of 90/64nm, and with a selected minimum M1 gap size of 70nm. The Metal1 layer is patterned with 193nm immersion lithography (193i) using Negative Tone Developer (NTD) resist, and a double-patterning Litho-Etch-Litho-Etch (LELE) process. Our study is based on Logic test blocks that we OPCed with a combination of calibrated models for litho and for etch. We report the Overlapping Process Window (OPW), based on a selection of test structures measured after-etch. We find that most of the OPW limiting structures are EOL (End-of-Line) configurations. Further analysis of these individual OPW limiters will reveal that they belong to different types, such as Resist 3D (R3D) and Mask 3D (M3D) sensitive structures, limiters related to OPC (Optical Proximity Corrections) options such as assist placement, or the choice of CD metrics and tolerances for calculation of the process windows itself. To guide this investigation, we will consider a ‘reference OPC’ case to be compared with other solutions. In addition, rigorous simulations and OPC verifications will complete the after-etch measurements to help us to validate our experimental findings.

Pattern roughness is expected to be an important issue in semiconductor scaling going forward. We performed smoothing of ArF photoresists (PRs) by a PR hardening technique called direct current superposition (DCS) cure,¹) and we showed that this technique can achieve a roughness smoothing effect for PRs having various line edge roughness (LER) conditions. Additionally, we showed that this smoothing technique has many process advantages from the viewpoint of lithography, such as an improved mask error enhancement factor (MEEF), expanded process window, and improved local critical dimension (CD) uniformity. We consider that these advantages occur because of a CD healing effect caused by linear dependence of shrink amount with line width due to the DCS cure technique.

Mask topography effects need to be taken into consideration for more advanced resolution enhancement techniques in optical lithography. However, rigorous 3D mask model achieves high accuracy at a large computational cost. This work develops a combined source, mask and pupil optimization (SMPO) approach by taking advantage of the fact that pupil phase manipulation is capable of partially compensating for mask topography effects. We first design the pupil wavefront function by incorporating primary and secondary spherical aberration through the coefficients of the Zernike polynomials, and achieve optimal source-mask pair under the condition of aberrated pupil. Evaluations against conventional source mask optimization (SMO) without incorporating pupil aberrations show that SMPO provides improved performance in terms of pattern fidelity and process window sizes.

Source optimization (SO) has become increasing important to improve the process window (PW) of optical lithography systems. Most of current SO approaches modify the source intensity distribution, but fix the polarization state thus limiting the degrees of optimization freedom. In addition, these SO methods simultaneously optimize the imaging performance on focal and defocal planes to extend the depth of focus (DOF) at the cost of increasing the computational complexity. To overcome these above limitations, this paper develops a pixelated gradient-based polarization optimization (PO) method to effectively extend the PW by seeking for the optimal polarization angle for each point source. In order to accelerate the optimization process, the proposed method tries to optimize a compact cost function incorporating the integral imaging performance over a certain defocus range, rather than taking into account the separate performance metrics on different imaging planes. A gradientbased algorithm is exploited to iteratively modulate the polarization angles to keep reducing the cost function. Finally, a post-processing method is applied to reduce the complexity of the optimized polarization angle pattern for improving its manufacturability. Simulations show that the proposed PO algorithm will achieve approximate two-fold speedup compared to the method using a traditional cost function. The proposed PO algorithm is potential to be applied independently or associated with source and mask optimizations to further improve the lithographic performance. Publisher’s Note: This paper, originally published on 3/31/14, was replaced with a corrected/revised version on 6/3/14. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Negative tone development (NTD) process with positive resist and organic solvent-based developer enhances image contrast and uses a light-field mask to make same feature in opposition to positive tone development (PTD). Due to extremely high transmission rate of a light-field mask, absorption of exposure energy on a mask becomes imperceptible. However, the exposure energy transmitted through the mask influences not only lens heating but also wafer heating. Overlay budget by wafer heating becomes a considerable amount in NTD process. In this paper, to clarify overlay change induced by wafer heating in NTD process, four different levels of exposure energy are applied and the overlay errors are deteriorated by increasing energy. Due to wafer heating, the remarkable correlation between Y-overlay errors and scanning direction are observed. Especially, Ty, RK8, and RK12 have mostly considerable correlation with scanning direction. In NTD process, to avoid this phenomenon, exposure energy has to be minimized. In case scanning direction dependency in overlay is not prevented by minimization of exposure energy, fingerprint correction in wafer field is able to reduce this overlay error.

Hybrid OPC modeling is investigated using both CDs from 1D and simple 2D structures and contours extracted from complex 2D structures, which are obtained by a Critical Dimension-Scanning Electron Microscope (CD-SEM). Recent studies have addressed some of key issues needed for the implementation of contour extraction, including an edge detection algorithm consistent with conventional CD measurements, contour averaging and contour alignment. Firstly, pattern contours obtained from CD-SEM images were used to complement traditional site driven CD metrology for the calibration of OPC models for both metal and contact layers of 10 nm-node logic device, developed in Albany Nano-Tech. The accuracy of hybrid OPC model was compared with that of conventional OPC model, which was created with only CD data. Accuracy of the model, defined as total error root-mean-square (RMS), was improved by 23% with the use of hybrid OPC modeling for contact layer and 18% for metal layer, respectively. Pattern specific benefit of hybrid modeling was also examined. Resist shrink correction was applied to contours extracted from CD-SEM images in order to improve accuracy of the contours, and shrink corrected contours were used for OPC modeling. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total error RMS was decreased by 0.2nm (12%) with shrink correction technique. Variation of model accuracy among 8 modeling runs with different model calibration patterns was reduced by applying shrink correction. The shrink correction of contours can improve accuracy and stability of OPC model.

3D Resist profile aware OPC has becoming increasingly important to address hot spots generated at etch processes due to the mass occurrence of non-ideal resist profile in 28nm technology node and beyond. It is therefore critical to build compact models capable of 3D simulation for OPC applications. A straightforward and simple approach is to build individual 2D models at different image depths either based on actual wafer measurement data or virtual simulation data from rigorous lithography simulators. Individual models at interested heights can be used by downstream OPC/LRC tools to account for 3D resist profile effects. However, the relevant image depths need be predetermined due to the discontinuous nature of the methodology itself. Furthermore, the physical commonality among the individual 2D models may deviate from each other as well during the separate calibration processes. To overcome the drawbacks, efforts are made in this paper to compute the whole bulk image using Hopkins equation in one shot. The bulk image is then used to build 3D resist models. This approach also opens the feasibility of including resist interface effects (for example, top or bottom out-diffusion), which are important to resist profile formation, into a compact 3D resist model. The interface effects calculations are merged into the bulk image Hopkins equation. Simulation experiments are conducted to demonstrate that resist profile heavily rely on interface conditions. Our experimental results show that those interface effects can be accurately simulated with reference to rigorous simulation results. In modeling reality, such a 3D resist model can be calibrated with data from discrete image planes but can be used at arbitrary interpolated planes. One obvious advantage of this 3D resist model approach is that the 3D model is more physically represented by a common set of resist parameters (in contrast to the individual model approach) for 3D resist profile simulation. A full model calibration test is conducted on a virtual lithography process. It is demonstrated that 3D resist profile of the process can be precisely captured by this method. It is shown that the resist model can be carried to a different lithography process with same resist setup but a different illumination source without model any accuracy degradation. In an additional test, the model is used to demonstrate the capability of resist 3D profile correction by ILT.

A traditional approach to construct a fast lithographic model is to match wafer top-down SEM images, contours and/or gauge CDs with a TCC model plus some simple resist representation. This modeling method has been proven and is extensively used for OPC modeling. As the technology moves forward, this traditional approach has become insufficient in regard to lithography weak point detection, etching bias prediction, etc. The drawback of this approach is from metrology and simulation. First, top-down SEM is only good for acquiring planar CD information. Some 3D metrology such as cross-section SEM or AFM is necessary to obtain the true resist profile. Second, the TCC modeling approach is only suitable for planar image simulation. In order to model the resist profile, full 3D image simulation is needed. Even though there are many rigorous simulators capable of catching the resist profile very well, none of them is feasible for full-chip application due to the tremendous consumption of computational resource. The authors have proposed a quasi-3D image simulation method in the previous study [1], which is suitable for full-chip simulation with the consideration of sidewall angles, to improve the model accuracy of planar models. In this paper, the quasi-3D image simulation is extended to directly model the resist profile with AFM and/or cross-section SEM data. Resist weak points detected by the model generated with this 3D approach are verified on the wafer.

With emerging technologies, such as fin-based field-effect transistors (finFETs), the structures, which define the functionality of a device, have added one dimension in the patterning and are now three-dimensional. Lithography for CMOS patterning becomes more complicated for finFETs given the three-dimensional substrate structure, and the resist modeling targeting this issue is yet to be fully investigated. Here, we present lithographic simulations on topography relevant for finFET devices compatible with nodes down to 10 nm. We investigate the influence of different materials and of the additional optical complexity due to the topography and density of the gates and fins.

Assessing pattern printability in new large layouts faces important challenges of runtime and false detection. Lithographic simulation tools and classification techniques do not scale well. We propose a fast pattern detection method that builds jointly a structured overcomplete basis, representing each reference pattern, and a linear predictor of their lithographic difficulty. A pattern from a new design is detected “novel” if its reconstruction error, when coded in the learned basis, is large. This allows a fast detection of unseen clips and a fast prediction of their lithographic difficulty. We show high speedup (1000×) compared to nearest neighbor search, and very high correlation between predicted and calculated lithographic estimate values.

This paper discusses a novel pattern based standalone process verification technique that meets with current and future needs for semiconductor manufacturing of memory and logic devices. The choosing the right process verification technique is essential to bridge the discrepancy between the intended and the printed pattern. As the industry moving to very low k1 patterning solutions at each technology node, the challenges for process verification are becoming nightmare for lithography engineers, such as large number of possible verification defects and defect disposition. In low k1 lithography, demand for full-chip process verification is increasing. Full-chip process verification is applied post to process and optical proximity correction (OPC) step. The current challenges in process verification are large number of defects reported, disposition difficulties, long defect review times, and no feedback provided to OPC. The technique presented here is based on pattern based verification where each reported defects are classified in terms of patterns and these patterns are saved to a database. Later this database is used for screening incoming new design prior to OPC step.

Highly regular gridded designs have been generally accepted¹ as a key component for continued advances in lithographic resolution in an era of limited further progress in lithography hardware. With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs. GDR is necessary for designs with k1 approaching the theoretical Rayleigh limit ~ 0:25. High pattern densities (fine pitch) and good image quality and manufacturability are achieved by very regular designs Fig. 1, which avoid complex corner structures and pattern density variations typical for conventional 2D designs. In particular lines+cuts implementations of GDR are well-suited for pitch splitting and multiple patterning, where the critical cuts patterns can be easily separated into groups with larger pitch for separate patterning. Very advanced technology nodes thus become possible with conventional lithography technology, see² for 11nm results.

In progress of lithography technologies, the importance of Mask3D analysis has been emphasized because the influence of mask topography effects is not avoidable to be increased explosively. An electromagnetic filed simulation method, such as FDTD, RCWA and FEM, is applied to analyze those complicated phenomena. We have investigated Constrained Interpolation Profile (CIP) method, which is one of the Method of Characteristics (MoC), for Mask3D analysis in optical lithography. CIP method can reproduce the phase of propagating waves with less numerical error by using high order polynomial function. The restrictions of grid distance are relaxed with spatial grid. Therefore this method reduces the number of grid points in complex structure. In this paper, we study the feasibility of CIP scheme applying a non-uniform and spatial-interpolated grid to practical mask patterns. The number of grid points might be increased in complex layout and topological structure since these structures require a dense grid to remain the fidelity of each design. We propose a spatial interpolation method based on CIP method same as time-domain interpolation to reduce the number of grid points to be computed. The simulation results of two meshing methods with spatial interpolation are shown.

This paper extends the state of the art by demonstrating performance improvements in the Domain Decomposition Method (DDM) from a physical perturbation of the input mask geometry. Results from four testcases demonstrate that small, direct modifications in the input mask stack slope and edge location can result in model calibration and verification accuracy benefit of up to 30%. All final mask optimization results from this approach are shown to be valid within measurement accuracy of the dimensions expected from manufacture. We highlight the benefits of a more accurate description of the 3D EMF near field with crosstalk in model calibration and impact as a function of mask dimensions. The result is a useful technique to align DDM mask model accuracy with physical mask dimensions and scattering via model calibration.

As the feature sizes printed with optical lithography get smaller, Kirchhoff’s thin mask approximation used in full chip optical proximity corrections (OPC) fails to yield acceptable accuracy due to thick mask diffraction effects. One of the most observed effects of the thick mask diffraction is that it creates different focus shift for different patterns. When Bossung curves (CD plots with respect to defocus) of various patterns are observed from rigorous simulations and from actual wafer data one can notice that each pattern has a different best focus. Depending on the pattern, Bossung curves can be offset in either positive or negative direction. This significantly reduces the common depth of focus (DOF) for which all patterns print with acceptable fidelity. Even though each pattern by itself may have an acceptable DOF, the common DOF may not be acceptable. Several extensions to the thin mask approximation have been developed that model this behavior accurately, such as boundary layer approximations and domain decomposition methods. These methods provide a more accurate approximation than the thin mask model while still being computationally efficient to be useful for full chip OPC. Even though these approximations model and predict the focus shift accurately, to the best knowledge of the authors no method has been published to use these modeling capabilities to automatically fix this focus shift during OPC. In this paper we provide an optimization method to significantly reduce focus shift due to 3D mask effects during OPC. We show that our 3D mask model can predict this focus shift fairly accurately and we also demonstrate how we use this model in OPC to reduce focus shift, which significantly improves the common DOF for the entire layout.

Of keen interest to the IC industry are advanced computational lithography applications such as Optical Proximity Correction of IC layouts (OPC), scanner matching by optical proximity effect matching (OPEM), and Source Optimization (SO) and Source-Mask Optimization (SMO) used as advanced reticle enhancement techniques. The success of these tasks is strongly dependent on the integrity of the lithographic simulators used in computational lithography (CL) optimizers. Lithographic mask models used by these simulators are key drivers impacting the accuracy of the image predications, and as a consequence, determine the validity of these CL solutions. Much of the CL work involves Kirchhoff mask models, a.k.a. thin masks approximation, simplifying the treatment of the mask near-field images. On the other hand, imaging models for hyper-NA scanner require that the interactions of the illumination fields with the mask topography be rigorously accounted for, by numerically solving Maxwell’s Equations. The simulators used to predict the image formation in the hyper-NA scanners must rigorously treat the masks topography and its interaction with the scanner illuminators. Such imaging models come at a high computational cost and pose challenging accuracy vs. compute time tradeoffs. Additional complication comes from the fact that the performance metrics used in computational lithography tasks show highly non-linear response to the optimization parameters. Finally, the number of patterns used for tasks such as OPC, OPEM, SO, or SMO range from tens to hundreds. These requirements determine the complexity and the workload of the lithography optimization tasks. The tools to build rigorous imaging optimizers based on first-principles governing imaging in scanners are available, but the quantifiable benefits they might provide are not very well understood. To quantify the performance of OPE matching solutions, we have compared the results of various imaging optimization trials obtained with Kirchhoff mask models to those obtained with rigorous models involving solutions of Maxwell’s Equations. In both sets of trials, we used sets of large numbers of patterns, with specifications representative of CL tasks commonly encountered in hyper-NA imaging. In this report we present OPEM solutions based on various mask models and discuss the models’ impact on hyper- NA scanner matching accuracy. We draw conclusions on the accuracy of results obtained with thin mask models vs. the topographic OPEM solutions. We present various examples representative of the scanner image matching for patterns representative of the current generation of IC designs.

We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s publication [1]. Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before [2], we implement a 2D phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more predictive than compact model but much faster then the physics-based MC model. However simplifying the model might lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm based lithography process using DSA.

During early stage development of a DSA process, there are many unknown interactions between design, DSA process, RET, and mask synthesis. The computational resolution of these unknowns can guide development towards a common process space whereby manufacturing success can be evaluated. This paper will demonstrate the use of existing Inverse Lithography Technology (ILT) to co-optimize the multitude of parameters. ILT mask synthesis will be applied to a varied hole design space in combination with a range of DSA model parameters under different illumination and RET conditions. The design will range from 40 nm pitch doublet to random DSA designs with larger pitches, while various effective DSA characteristics of shrink bias and corner smoothing will be assumed for the DSA model during optimization. The co-optimization of these design parameters and process characteristics under different SMO solutions and RET conditions (dark/bright field tones and binary/PSM mask types) will also help to provide a complete process mapping of possible manufacturing options. The lithographic performances for masks within the optimized parameter space will be generated to show a common process space with the highest possibility for success.

We propose a framework for the rigorous simulation of the combined lithography/directed self-assembly (DSA) of block copolymers process. As an example, the rectification of a contact hole through grapho-epitaxy DSA is presented. The proposed modeling strategy, using a full-fledged lithography simulation and a coarse-grained polymer model in conjunction with a particle-based Monte-Carlo simulator, provides direct insight into various aspects of the pattern and defect formation. We accordingly characterize and quantify the combined process performance and its determining factors. Appropriate metrics and representations for the common process windows are derived.

Photomasks are expected to have phase effects near edges due to their 3D topography, which can be modeled as imaginary boundary layers in thin mask simulations. We apply a modified transport of intensity (TIE) phase imaging technique to through-focus aerial images of photomasks in order to recover polarization-dependent edge effects. We use AIMS measurements with 193nm light to study the dependence of recovered phase on mask type and geometry. The TIE is an intensity conservation equation that quantitatively relates phase in the wafer plane to intensity through-focus. Here, we develop a modified version of the TIE for strongly absorbing objects, and apply it to recover wafer plane phase of attenuating masks. The projection printer blurs the fields at the wafer plane by its point spread function, hence an effective deconvolution is used to predict the boundary layers at the mask that best approximate the measured thick mask edge effects. Computation required for the inverse problem is fast and independent of mask geometry, unlike FDTD computations.

193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

Nikon’s new immersion scanner “NSR-S630D” has been developed to deliver enhanced product overlay and CD uniformity while improving productivity at 10 nm half pitch node and beyond. The NSR-S630D is equipped with various advanced technologies. Among them are the new reticle stage with encoder servo control and advanced reticle bending mechanism, new optics with enhanced correction knobs for thermal aberration control, and advanced thermally stable wafer stage; all of which are key components to providing the best scanner solution to meet the requirements for 10 nm half pitch node and beyond. In this paper, we describe the NSR-630D development concept and the latest performance data at factory. One of the key factors in improving overlay is shot distortion; in order to improve shot distortion, the NSR-S630D is equipped with a newly developed state-of-the-art projection lens. The overall overlay improvements have been made possible not only by minimizing lens distortion through advancements in lens manufacturing techniques, but also by reducing thermal distortion, which is especially important in actual device production. In addition, we have also added a new function for more effective reticle heating distortion compensation. In order to improve wafer grid performance, we newly designed a wafer table with enhanced thermal stability. We have also further improved the reticle bending system in order to minimize the field curvature induced by projection lens thermal aberration. The new features described above, in addition to the matured Streamlign platform, have enabled the NSR-S630D to deliver highest accuracy and stability.

As chipmakers continue to reduce feature sizes and shrink CDs on the wafer to meet customer needs, Cymer continues developing light sources that enable advanced lithography, and introducing innovations to improve productivity, wafer yield, and cost of ownership. In particular, the architecture provides dose control and improved spectral bandwidth stability, both of which enables superior CD control and wafer yield for the chipmaker. The XLR 660ix incorporates new controller technology called ETC for improvements in spectral bandwidth stability, energy dose stability, and wavelength stability. This translates to improved CD control and higher wafer yields. The authors will discuss the impact that these improvements will have in advanced lithography applications.

The laser impacts on the proximity error are well known in many previous studies and papers. The proximity budget control is more and more important for advanced node design. The goal of this paper is to describe the laser spectral bandwidth and wavelength stability contributions to the proximity budget by considering general line/space and trench pattern design. We performed experiments and modeled the photolithography response using Panoramic Technology HyperLith simulation over a range of laser bandwidth and wavelength stability conditions to quantify the long term and short term stability contributions on wafer-to-wafer and field-to-field proximity variation. Finally, we determine the requirements for current system performance to meet patterning requirements and minimize the laser contribution on proximity error and within 4% of target CD Critical Dimension Uniformity (CDU) budget process requirement [2]. This paper also discusses how the wafer lithography drivers are enabled by ArFi light source technologies.

An in situ aberration measurement method using a phase-shift ring mask is proposed for lithographic projection lenses. Two dimensional (2D) phase-shift rings are designed as the measurement mask. A linear model between the aerial image intensity distribution and the aberrations is built by principal component analysis and multivariate linear regression analyses. Compared with the AMAI-PCA method, in which a binary mask and through-focus aerial images at are used for aberration extraction, the aerial images of the phase-shift ring mask contain more useful information. This provides the possibility to eliminate the crosstalk between different kinds of aberrations. Therefore, the accuracy of aberration measurement is improved. Simulations with the lithography simulator Dr. LiTHO showed that the accuracy is improved by 15% and 5 more Zernike aberrations can be measured compared with AMAI-PCA. Moreover, the speed of aberration measurement is improved because less aerial images are required using the new 2D mask.

An in situ aberration measurement method using a two dimensional (2D) phase-shift ring mask has been proposed for lithographic projection lenses, which is more accurate and faster than AMAI-PCA method. The defocus of the aerial image of the 2D measurement mask is the main source of the measurement error of this method. In this paper, a defocus measurement method for the aberration measurement method is proposed, in which the residual of the principal component analysis process is used as the criterion. After the defocus is accurately measured, the most suitable linear relationship model, which plays a very important role in the aberration measurement method, can be determined. Simulations with the lithography simulator Dr. LiTHO demonstrated that the accuracy of the defocus measurement method is approximately 1nm. The aberration measurement method can detect 12 Zernike aberrations (Z₅~Z₁₆) with maximum systematic error of approximately 1mλ, when the suitable linear relationship model is used.

Historically IC (integrated circuit) device scaling has bridged the gap between technology nodes. Device size reduction is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Exemplifying this trend are aggressive reductions in memory cell sizes that have resulted in systems with diminishing area between bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently difficult to resolve because of their relatively small area and complex aerial image. To accommodate these trends, semiconductor device design has shifted toward the implementation of elliptical contact features. This empowers designers to maximize the use of free device space, preserving contact area and effectively reducing the via dimension just along a single axis. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect ratio vias for implementation in electronic design systems. Vortex masks, characterized by their helically induced propagation of light and consequent dark core, afford great potential for the patterning of such features when coupled with a high resolution negative tone resist system. This study investigates the integration of a vortex mask in a 193nm immersion (193i) lithography system and qualifies its ability to augment aspect ratio through feature density using aerial image vector simulation. It was found that vortex fabricated vias provide a distinct resolution advantage over traditionally patterned contact features employing a 6% attenuated phase shift mask (APM). 1:1 features were resolvable at 110nm pitch with a 38nm critical dimension (CD) and 110nm depth of focus (DOF) at 10% exposure latitude (EL). Furthermore, iterative source-mask optimization was executed as means to augment aspect ratio. By employing mask asymmetries and directionally biased sources aspect ratios ranging between 1:1 and 2:1 were achievable, however, this range is ultimately dictated by pitch employed.

At the 20nm technology node, it is challenging for simple resolution enhancements techniques (RET) to achieve sufficient process margin due to significant coupling effects for dense features. Advanced computational lithography techniques including Source Mask Optimization (SMO), thick mask modeling (M3D), Model Based Sub Resolution Assist Features (MB-SRAF) and Process Window Solver (PW Solver) methods are now required in the mask correction processes to achieve optimal lithographic goals. An OPC solution must not only converge to a nominal condition with high fidelity, but also provide this fidelity over an acceptable process window condition. The solution must also be sufficiently robust to account for potential scanner or OPC model tuning. In many cases, it is observed that with even a small change in OPC parameters, the mask correction could have a big change, therefore making OPC optimization quite challenging. On top of this, different patterns may have significantly different optimum source maps and different optimum OPC solution paths. Consequently, the need for finding a globally optimal OPC solution becomes important. In this work, we introduce a holistic solution including source and mask optimization (SMO), MB-SRAF, conventional OPC and Co-Optimization OPC, in which each technique plays a unique role in process window enhancement: SMO optimizes the source to find the best source solution for all critical patterns; Co-Optimization provides the optimized location and size of scattering bars and guides the optimized OPC solution; MB-SRAF and MB-OPC then utilizes all information from advanced solvers and performs a globally optimized production solution.

The roughness present on the sidewalls of lithographically defined patterns imposes a very important challenge for advanced technology nodes. It can originate from the aerial image or the photoresist chemistry/processing [1]. The latter remains to be the dominant group in ArF and KrF lithography; however, the roughness originating from the mask transferred to the aerial image is gaining more attention [2-9], especially for the imaging conditions with large mask error enhancement factor (MEEF) values. The mask roughness contribution is usually in the low frequency range, which is particularly detrimental to the device performance by causing variations in electrical device parameters on the same chip [10-12]. This paper explains characteristic differences between pupil plane filtering in amplitude and in phase for the purpose of mitigating mask roughness transfer under interference-like lithography imaging conditions, where onedirectional periodic features are to be printed by partially coherent sources. A white noise edge roughness was used to perturbate the mask features for validating the mitigation.

In this paper, we present a thorough investigation of self-aligned octuple patterning (SAOP) process characteristics, cost structure, integration challenges, and layout decomposition. The statistical characteristics of SAOP CD variations such as multi-modality are analyzed and contributions from various features to CDU and MTT (mean-to-target) budgets are estimated. The gap space is found to have the worst CDU+MTT performance and is used to determine the required overlay accuracy to ensure a satisfactory edge-placement yield of a cut process. Moreover, we propose a 5-mask positive-tone SAOP (pSAOP) process for memory FEOL patterning and a 3-mask negative-tone SAOP (nSAOP) process for logic BEOL patterning. The potential challenges of 2-D SAOP layout decomposition for BEOL applications are identified. Possible decomposition approaches are explored and the functionality of several developed algorithm is verified using 2-D layout examples from Open Cell Library.

A generalized edge-placement yield model for the cut-hole patterning process is developed. It incorporates the cut-hole overlay errors, cut-hole and grating line/space CD variations into a unified physical model to investigate the key parameters that affect the edge-placement yield. The yield related features are identified first and probability-of-failure (POF) functions are introduced to construct the yield formula. The variable number in the yield integral is reduced from four to two by a special transformation method. Our calculation results show that the cut-hole overhang and (grating) line/space CD must be optimized in order to achieve the maximum yield. The sensitivity of edge-placement yield to various statistical parameters is investigated and the overlay errors are found to play a dominant role. We also study the scaling trend of the edge-placement yield and show that non-trivial challenges of manufacturing (half-pitch) 7-nm FinFET devices will require significantly improved overlay accuracy and process control.

Dual photoresist complimentary lithography technique consisting of inorganic oxide photoresist and organic photoresist is applied to produce the sub-micro pit patterns on a sapphire surface. The oxide photoresist is patterned by the direct laser writing and the developed mark size decreases to a smaller value than the laser spot size due to the thermal lithography. The small developed pit diameter is one of the advantages using oxide photoresist. The oxide photoresist possesses strong etching resistance against the oxygen plasma but shows no resistance against the chlorine plasma. The chlorine plasma is a necessary component to etch the sapphire during the ion-coupled-plasma reactive-ion-etching process because of sapphire’s mechanical hardness and chemical stability. However, the characteristics of organic resist SU8 are opposite to that of oxide photoresist and possess moderate resistance against chlorine plasma but show no resistance to oxygen plasma. The thermal and developing characteristics of oxide photoresist are reported here. The dependence of the laser power on the developed mark sizes and morphologies is illustrated by atomic force microscopy. The temperature distribution on the photoresist structure during the laser writing is simulated. Images of patterned pits on the large commercial sapphire substrates are also shown.

Typical Dye-sensitized solar cells (DSSC) are composed of mesoporous TiO₂ nanocrystals electrode on transparent fluorine-doped tin oxide (FTO) substrate, sensitizers on the TiO₂ nanocrystals, platinum (Pt) on the FTO substrate as a counter-electrode, and iodine/iodide electrolytes between the two transparent conducting oxide (TCO) substrate. But two transparent conductive oxide(TCO) substrates are estimated to be about 60[%] of the total cost of the DSSCs. Currently novel TCO-less structures have been investigated in order to reduce the cost. We suggested a TCO-less DSSCs which has titanium layer electrodes. Titanium layer electrodes are formed by electron-beam evaporation method. And we proposed the formation of hole for injecting the electrolyte of DSSC by using lithographic method. The sizes of holes are 4um and the intervals of holes are 2um. Finally, we prepared the 0.45 cm² DSSC device and analytical instruments such as electrochemical impedance spectroscopy, scanning electron microscope were used to evaluate the TCO-less DSSCs.

This paper reports the development of a low-cost, portable, light-emitting diode (LED)-based UV exposure system for photolithography. The major system components include UV-LEDs, microcontroller, digital-to-analog (D/A) converter and LED control circuitry. The UV-LED lithography system is also equipped with a digital user interface (LCD and keypad) and permits accurate electronic control on the exposure time and power. Hence the exposure dose can be varied depending on process requirements. Compared to traditional contact lithography, the UV-LED lithography system is significantly cheaper, simple to construct using off-the shelf components and does not require complex infrastructure to operate. Such reduction in system cost and complexity renders UV-LED lithography as a perfect candidate for micro lithography with large process windows typically suitable for MEMS, microfluidics applications.

Optical lithography has been the engine that has empowered semiconductor industry to continually reduce the half-pitch for over 50 years. In early mask aligners a simple movie lamp was enough to illuminate the photomask. Illumination started to play a more decisive role when proximity mask aligners appeared in the mid-1970s. Off-axis illumination was introduced to reduce diffraction effects. For early projection lithography systems (wafer steppers), the only challenge was to collect the light efficiently to ensure short exposure time. When projection optics reached highest level of perfection, further improvement was achieved by optimizing illumination. Shaping the illumination light, also referred as pupil shaping, allows the optical path from reticle to wafer to be optimized and thus has a major impact on aberrations and diffraction effects. Highly-efficient micro-optical components are perfectly suited for this task. Micro-optics for illumination evolved from simple flat-top (fly’s-eye) to annular, dipole, quadrupole, multipole and freeform illumination. Today, programmable micro-mirror arrays allow illumination to be changed on the fly. The impact of refractive, diffractive and reflective microoptics for photolithography will be discussed.

The insertion of SRAF(Sub-Resolution Assist Feature) is one of the most frequently used method to enlarge the process window area. In most cases, the size of SRAF is proportional to the focus margin of drawn patterns. However, there is a trade-off between the SRAF size and SRAF printing, because SRAF is not supposed to be patterned on a wafer. For this reason, a lot of OPC engineers have been tried to put bigger and more SRAFs within the limits of the possible. The fact that many papers about predicting SRAF printability have been published recent years reflects this circumstance. Pattern dummy is inserted to enhance the lithographic process margin and CD uniformity unlike CMP dummy for uniform metal line height. It is ordinary to put pattern dummy at the designated location under consideration of the pitch of real patterns at design step. However, it is not always desirable to generate pattern dummies based on rules at the lithographic point of view. In this paper, we introduce the model based pattern dummy insertion method, which is putting pattern dummies at the location that model based SRAF is located. We applied the model based pattern dummy to the layers in logic devices, and studied which layer is more efficient for the insertion of dummies.

OPC (Optical Proximity Correction) has been employed for over decade to address local lithographic printing effects. With the intensive scaling down of the designs as well as the increasing complexity of layout routing, lithographic process is being pushed to its theoretical limit and it has led to continuously shrinking DoF (Depth of Focus). Complex OPC model components are hence included into optical lithography simulation to ensure tolerable CD (Critical Dimension) variation and sustainable DOF of concerned layouts. For example, very complicated segmentation needs to be applied in mask correction, which comes at the cost of long runtime and requires an effective approach to consolidate the adequacy of model components during the flow of correction parameter tuning. In this paper, an approach is demonstrated to improve the accuracy and efficiency of OPC parameter tuning for mask correction. The approach starts with analyzing the target points in post-OPC database to identify those intolerable variations, followed by a pattern similarity grouping for the above intolerable layouts. Then, a concern index is established based on the CD out-of-tolerance ratio, dissection and pattern type for prioritizing the problematic variations. Then the corrective parameters are accordingly optimized to reduce the variation on highly prioritized patterns. During the iteration flow of OPC parameter optimization, the combination of pattern grouping and concern index greatly reduces required optimization iterations for OPC recipe tuning and enhances OPC convergence.

It’s critical to address the yield issues caused by process specific layout patterns with limited process window. RETs such as PWOPC are introduced to guarantee high lithographic margin, but these techniques cost high run-time when applied to full-chips. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process. In this paper, we study a pattern aware OPC flow that applies PWOPC or specific corrections locally to layouts with critical and yield limiting patterns. Although the full chip PWOPC provides an effective way, it causes great amount of run time penalty and does not achieve optimal process window. Overall, PAOPC achieves the better margins over the hotspots, without sacrificing turnaround time. The study demonstrates the benefit of the new flow with fine grained process window controls over different patterns. This flow get good improvement on defect counts when evaluated on 50 nm node logic devices.

As design rule of devices are getting smaller, it is hard to obtain enough process window like DOF, EL. In aspect of device integration, lithography processes which are included in etching process became more and more important. It has been claimed that photo resist profile is closely related with etch bias and vertical profile. Resist top-loss and bottom slope seriously affect after-etching profile. In order to address these problems, new model based verification method is necessary for preventing hot spots. In this paper, we propose more practical method of model based verification using rigorous simulation and wafer verification results. Highly accurate model is obtained by physical model fitting with minimal experimental data set. After that, virtual data are extracted from rigorous simulation model for applying full chip model based verification modeling. Basically, 2 data sets will be needed for verification of 2-level model, for detecting resist top-loss and bottom-slope. Finally this article shows comparison results of model based verification and real wafer inspection. And also, we try to prove that the newly proposed method is another good candidate to address existing problems such as pinching and bridging after post etching and CMP process.

A robust optical proximity correction (OPC) model must include process variation to be effective in volume manufacturing. Often, calibration of an OPC model is based on data from a single scanner. However, scanner and mask three dimension (3D) effects have been found to affect printing performance and OPC model effectiveness [1]. OPC model robustness is improved if the fingerprints of different scanners are matched as closely as possible. Scanner source map or boundary condition variations can cause isolated and dense feature focus differences between different scanners. The scanner used to build a robust OPC model should have a minimum focus difference between isolated and dense features. Mask 3D effects must be included in OPC model building. Even if the design data is the same, mask 3D effects will vary by different advanced blank film stacks and model fitting will lead to different results. In this work, the effects of focus differences between nested and isolated features for OPC model building are quantified. In addition, mask 3D effect contributions to OPC models will also be illustrated. OPC model tolerance to variation is shown using data from multiple scanners and mask topographies and methodologies to optimize OPC models are presented. The data confirms that different absorber thickness, and n and k values, for advanced binary masks will influence the boundary conditions and effect lithographic performance. A thinner absorber demonstrated better CD prediction than thicker blanks in semi-dense and isolated patterns for both CDTP and inverse CDTP. It also shows that the thinner absorber has better inverse linearity in small isolated features, and has much better prediction for large isolated patterns. The generation of OPC models must include variations due to mask material properties and scanner optical variations to provide robust performance in manufacturing.

With constant shrinking of device critical dimensions (CD), the quality of pattern transfer in IC fabrication depends on the etch process and the exposure process fidelities, and the interaction of lithographic and etching processes is no longer negligible. Etch effect correction with accurate models has become an important component in optical proximity correction (OPC) modeling and related applications. It is now commonly accepted that the lithographic and etch effects should be modeled and corrected in a sequential and staged way: a resist (or lithographic) model should be created and used for lithographic effect compensation, and an etch model should be created and used for etch effect compensation. However, there can be various degrees of separation of these two modeling stages. In order to optimally capture the significant variation in the post-development resist patterns and post-etching patterns, it is helpful to integrate these two processes together for the OPC model calibration practice. In this paper, we analyze the integrated simulation approach in OPC modeling where the entire resist model information is made fully accessible in the etch modeling stage to allow the possibility of resist and etch co-optimization, e.g. through adjusting the resist model to optimally fit the etch data. Furthermore, the integrated simulation technique is integrated into a verification flow to simplify the conventional staged flow.

Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell’s equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

Calibrating an accurate OPC model usually requires a lot of one-dimensional CD-SEM measurements. A promising alternative is to use a SEM image contour approach but many challenges remain to implement this technique for production. In this work a specific flow is presented to get good and reliable contours well matched with traditional CDSEM measurements. Furthermore this work investigates the importance of site selection (number, type, image space coverage) for a successful contour-based OPC model. Finally the comparison of conventional and contour based models takes into account the calibration and verification performances of both models with a possible cross verification between model data sets. Specific advantages of contour based model are also discussed.

In this paper we discuss a statistic approach to SRAF printing detection. This method considers and is generically based on the opportunistic essence of the resist image formation due to various stochastic uncertainties in the state-of-the-art advanced node lithographic process. The method is based on the direct measurement of the probability of SRAF printing at considered-to-be-nominal conditions and extrapolation of the results based on the process conditions/assumptions to the probability ranges where direct probability measurements are practically impossible. The method described here provides a controllable and quantitative framework for setting up SRAF printing detection and facilitates the significant reduction of the efforts and costs needed to setup SRAF printing checks. The argumentation and the way of looking at the verification setup in the environments with considerable variability can be directly reused to design and calibrate other checks in OPC verification flows.

As Critical Dimension (CD) sizes decrease for 32 nm node and beyond, resist loss increases and resist patterns become more vulnerable to etching failures. Traditional OPC models only consider 2D contours and neglect height variations. Rigorous resist simulators can simulate a 3D resist profile but they are not fast enough for correction or verification on a full chip. However, resist loss for positive tone resists is mainly driven by optical intensity variations which are accurately modeled by the optical portion of an OPC model. In this article, we show that a Calibre^TM CM1 resist model can be used to determine resist loss by properly selecting the optical image plane for calibration. The model can then be used to identify toploss hotspots on a full chip and in some cases to correction of these patterns. In addition, the article will show how the model can be made more accurate by accounting for some 3D effects like diffusion through height.

With the implementation of multi-patterning ArF-immersion for sub 20nm integrated circuits (IC), advances in equipment monitoring and control are needed to support on-wafer yield performance. These in-situ equipment monitoring improvements, along with advanced litho-cell corrections based on on-wafer measurements, enable meeting stringent overlay and CD control requirements for advanced lithography patterning. The importance of light-source performance on lithography pattering (CD and overlay) has been discussed in previous publications.^[1-3] Recent developments of Cymer ArF light-source metrology and on-board monitoring enable end-users to detect, for each exposed wafer, changes in the near-field and far-field spatial profiles and polarization performance, ^[4-6] in addition to the key ‘optical’ scalar parameters, such as bandwidth, wavelength and energy. The major advantage of this capability is that the key performance metrics are sampled at rates matched to wafer performance, e.g. every exposure field across the wafer, which is critical for direct correlation with on-wafer performance for process control and excursion detection.

Critical dimension uniformity (CDU) of hole layer is becoming more and more crucial and tightened alongside with the technology node being driven into 28 nm and beyond, since the critical dimension (CD) variation of 2-dimensional (2D) hole pattern is intrinsically harder to control than that of 1D pattern (line/space). As the process window becomes more marginal with the more advanced technology node, although at the cost of contrast loss, EFESE tilt (focus drilling method) is one handy trick for its DOF enhancement capability (1-3). We observed an abnormal up to 6 nm ADI CD trend-down in Y-direction (exposure scan direction) in the strictly repeated via-hole patterns within an about 8 mm x 6 mm chip in condition 1 wafer with pre-layer patterns (short as C1 wafer) where EFESE tilt is applied. No CD trend-down or trend up in X-direction. This C1 hole layer uses EFESE tilt to improve DOF. This CD trend-down phenomenon is thoroughly investigated and a model of “effective EFESE tilt” is proposed and verified. Based on the model, we made a further step into the assessment of another focus drilling method, i.e. EFESE High Range (HR) and evaluate its performance under the same complex leveling scheme. Through all this analysis, we give an insight of the safety zone for applying EFESE tilt for future reference.

In the High NA process, pattern environment will become very aggressive because of scattering effect. Especially on metal layers, maybe it will cause pattern bridge when the pattern density is varied. We need to find out the root cause and have a good solution to minimize the wafer CD difference that comes from environmental effect (pattern density). In this paper, we analyze the root cause by checking the pattern density influence on mask CD and wafer printing CD. We design different pattern density layout to measure the mask CD error, use AIMS (Aerial Image Measurement System) to measure the aerial image CD and print wafer to check the real result. Then, we try to add some assistant feature (pattern density balance) and use simulation tool to simulate whether this method can have improvement.

As critical dimension shrinks, pattern density of integrated circuits gets much denser and lithographic process variations become more pronounced. In order to synthesize masks that are robust to process variations, the average wafer performance with respect to process fluctuations is optimized. This approach takes into account process variations explicitly. However, it needs to calculate a large number of optical images under different process variations during its optimizing process and thus significantly increases the computational burden. Most recently, we proposed a convolutionvariation separation (CVS) method for modeling of optical lithography, which separates process variables from the coordinate system and hence enables fast computation of optical images through a wide range of process variations. In this work, we detail the formulation of robust inverse lithography making use of the CVS method, and further investigate the impacts of arbitrary statistical distribution of process variations on the synthesized mask patterns.

Traditional segment-based model-based OPC methods have been the mainstream mask layout optimization techniques in volume production for memory and embedded memory devices for many device generations. These techniques have been continually optimized over time to meet the ever increasing difficulties of memory and memory periphery patterning. There are a range of difficult issues for patterning embedded memories successfully. These difficulties include the need for a very high level of symmetry and consistency (both within memory cells themselves and between cells) due to circuit effects such as noise margin requirements in SRAMs. Memory cells and access structures consume a large percentage of area in embedded devices so there is a very high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements. Additionally, the range of interactions between mask synthesis corrections of neighboring areas can extend well beyond the size of the memory cell, making it difficult to fully take advantage of the inherent designed cell hierarchy in mask pattern optimization. This is especially true for non-traditional (i.e., less dependent on geometric rule) OPC/RET methods such as inverse lithography techniques (ILT) which inherently have more model-based decisions in their optimizations. New inverse methods such as model-based SRAF placement and ILT are, however, well known to have considerable benefits in finding flexible mask pattern solutions to improve process window, improve 2D CD control, and improve resolution in ultra-dense memory patterns. They also are known to reduce recipe complexity and provide native MRC compliant mask pattern solutions. Unfortunately, ILT is also known to be several times slower than traditional OPC methods due to the increased computational lithographic optimizations it performs. In this paper, we describe and present results for a methodology to greatly improve the ability of ILT to optimize advanced embedded memory designs while retaining significant hierarchy and cell design symmetry, therefore, have good turnaround time and CD uniformity. This paper will explain the enhancements which have been developed in order to overcome the traditional difficulties listed above. These enhancements are in the categories of local CD control, global chip processing options, process window benefit, turn-around time and hierarchy retention.

Gigaphoton has developed a new monitoring system that provides shot-level light source performance data to FDC systems during exposure time. The system provides basic monitoring data (e.g. Energy, Wavelength, Bandwidth, etc.) and beam performance data, such as Beam Profile, Pointing, Divergence, Polarization can also be monitored using a new metrology tool called the Beam Performance Monitor (BPM) module. During exposure time the system automatically identifies the start and end timing of the wafer and each shot based on the burst of firing signals from the scanner, and stores the measured data in sequence. The stored data is sorted by wafer or by shot, and sent to REDeeM Piece which in turn converts the data to the user's protocol and send it to the FDC system. The user also has the option to directly view or download the stored data using a GUI. Through this monitoring system, users can manage light sources data at the shot or reticle level to facilitate optimization of performance and running cost of the light source for each process. This monitoring system can be easily retrofitted to Gigaphoton's current ArF laser light sources. The beam splitter of the BPM was specially designed to bend only a small fraction of the source beam, so we are able to simply install the BPM without the need for special optical alignment.

Immersion lithography is one of the main technologies used to manufacture integrated circuits with the shortest feature size. In immersion lithography, temperature of immersion liquid is strictly constrained and its allowable range is less than ±0.01°C at 22°C. To meet this requirement, a temperature control algorithm adopted by the test rig which controls the temperature of the immersion liquid with process cooling water (PCW) via heat exchangers is proposed. By adjusting the flow rate of PCW through the heat exchangers, the control system varies the amount of heat exchanged, and the temperature of the immersion liquid can be properly controlled. The temperature control rig is a multi-disturbed, timevariant, non-linear and time-delayed system and its transfer function varies with the inlet temperature and flow rates of the streams through the heat exchangers. Considering the characteristics of the system, a cascade-connected fuzzy PID feedback algorithm is designed.

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

The step-and-scan lithographic illumination system has a scanning slit which could not only control the exposure field size but also assist the wafer to complete scanning process with high uniformity. The scanning slit is comprised by four blades which are drive by four electric actuators. This paper presents a 193nm lithographic illumination system without utilizing scanning slit. A microlens array, a micromirror array and a collimating lens are used to generated a certain intensity distribution on the surface of the aperture array. A fast scanning mirror is used in to change the position of the formed intensity distribution to change the illuniated area on the mask. That can realize lithographic scanning process without slit.

The IC Lithography roadmap foresees manufacturing of devices with critical dimension of < 20 nm. Overlay specification of single digit nanometer asking for nanometer positioning accuracy requiring sub nanometer position measurement accuracy. The glass ceramic ZERODUR^® is a well-established material in critical components of microlithography wafer stepper and offered with an extremely low coefficient of thermal expansion (CTE), the tightest tolerance available on market. SCHOTT is continuously improving manufacturing processes and it’s method to measure and characterize the CTE behavior of ZERODUR^® to full fill the ever tighter CTE specification for wafer stepper components. In this paper we present the ZERODUR^® Lithography Roadmap on the CTE metrology and tolerance. Additionally, simulation calculations based on a physical model are presented predicting the long term CTE behavior of ZERODUR^® components to optimize dimensional stability of precision positioning devices. CTE data of several low thermal expansion materials are compared regarding their temperature dependence between - 50°C and + 100°C. ZERODUR^® TAILORED 22°C is full filling the tight CTE tolerance of +/- 10 ppb / K within the broadest temperature interval compared to all other materials of this investigation. The data presented in this paper explicitly demonstrates the capability of ZERODUR^® to enable the nanometer precision required for future generation of lithography equipment and processes.

"Green" has fast become an important and pervasive topic throughout many industries worldwide. Many companies, especially in the manufacturing industries, have taken steps to integrate green initiatives into their high-level corporate strategies. Governments have also been active in implementing various initiatives designed to increase corporate responsibility and accountability towards environmental issues. In the semiconductor manufacturing industry, there are growing concerns over future environmental impact as enormous fabs expand and new generation of equipments become larger and more powerful. To address these concerns, Gigaphoton has implemented various green initiatives for many years under the EcoPhoton™ program. The objective of this program is to drive innovations in technology and services that enable manufacturers to significantly reduce both the financial and environmental “green cost” of laser operations in high-volume manufacturing environment (HVM) – primarily focusing on electricity, gas and heat management costs. One example of such innovation is Gigaphoton’s Injection-Lock system, which reduces electricity and gas utilization costs of the laser by up to 50%. Furthermore, to support the industry’s transition from 300mm to the next generation 450mm wafers, technologies are being developed to create lasers that offer double the output power from 60W to 120W, but reducing electricity and gas consumption by another 50%. This means that the efficiency of lasers can be improve by up to 4 times in 450mm wafer production environments. Other future innovations include the introduction of totally Heliumfree Excimer lasers that utilize Nitrogen gas as its replacement for optical module purging. This paper discusses these and other innovations by Gigaphoton to enable green manufacturing.

Semiconductor market demand for improved performance at lower cost continues to drive enhancements in excimer light source technologies. Increased output power, reduced variability in key light source parameters, and improved beam stability are required of the light source to support immersion lithography, multi-patterning, and 450mm wafer applications in high volume semiconductor manufacturing. To support future scanner needs, Cymer conducted a technology demonstration program to evaluate the design elements for a 120W ArFi light source. The program was based on the 90W XLR 600ix platform, and included rapid power switching between 90W and 120W modes to potentially support lot-to-lot changes in desired power. The 120W requirements also included improved beam stability in an exposure window conditionally reduced by 20%. The 120W output power is achieved by efficiency gains in system design, keeping system input power at the same level as the 90W XLR 600ix. To assess system to system variability, detailed system testing was conducted from 90W – 120W with reproducible results.