2.1

Warped wafers

Wafers often go through high temperature processes, resulting in warping caused by thermo induced stress. The features on the wafer follow the warped surface. When the wafer is flattened by the wafer chuck, these features move laterally as a function of warpage. Figure 1 shows the correlation of wafer warpage with overlay errors from a wafer with a TiN layer and another wafer without TiN. The overlay error induced by the warpage caused by the TiN deposition is 2.8 nm.

Fig. 1.

Wafer #2 has a TiN layer which was skipped for wafer #3. The warpage was measured with a Zygo interferometer showing a range of 11.6 um and 2.96 um respectively. The overlay errors are 8 and 5.2 nm.

2.2

Backside contaminated wafers

Wafers can easily be contaminated at the backside from non-lithographic processes such as etching or chemical mechanical polishing. When chucked down, the top surface is bent, causing defocus and overlay error. Figure 2 shows the overlay error induced this way. The wafer was made to pass through the same contaminating tool ten times for correlating the increase of contamination to the increase in overlay error. Figure 2(a) shows the overlay vector map after the 1^st pass and (b) after the 10^th pass. Figure 2(c) is a view of the contamination from an optical microscope.

Fig. 2.

(a) and (b) are overlay maps after the 1^st and the 10^th pass through the contaminating tool. Figure 2(c) is the contamination map from an optical microscope.

2.3

Front reference chuck to improve overlay accuracy

Wafer warpage and contamination are perennial problems with past nodes. It is quite difficult to keep the wafer absolutely clean and undistorted. We propose a front referenced wafer chuck with dynamically adjustable surface topography to yield to the particles at the wafer backside. Figure 3 shows three situations (a) Wafer-bottom referenced rigid chuck holding a clean and flat wafer (b) Same chuck but the wafer front surface is bent due to backside contamination. (c) Dynamic front-surface referenced chuck mitigating the effects of backside contamination.

Fig. 3.

(top to bottom) rigid wafer back referenced chuck; Sane chuck distorting a contaminating wafer; Dynamic front-referenced chuck.

2.4

High-order overlay corrections

Irregular wafer conditions above produce high-order nonlinear distortion requiring many high-order correction terms to reduce the overlay error. Figure 4 shows the overlay vector map of a nonlinearly distorted wafer. Using only 6 linear terms results an overlay residue of ±3 nm, which can be improved to ±1 nm using additional 12 high-order terms. The out-of-spec percentage improved from 1.5%~2.7% to 0~0.15% in 9 wafers. This type of overlay error is difficult to correct with rigid mask and lenses. Multiple e-beam maskless lithography enables high-order dynamic overlay corrections to deal with such situation.

Fig. 4.

Overlay accuracies with and without high-order corrections.

2.5

Mask contributions

In addition to controlling the placement errors on the mask, the flatness and bending of the mask also have to be controlled. For optical lithography, the lack of flatness from pellicle mounting can contribute to overlay errors but it is much smaller than the effects from lack of flatness on a EUV mask. EUV using a reflective mask, oblique illumination, an extremely short wavelength is ultrasensitive to lack of flatness. The flatness irregularity can be broken down into a map of longitudinal displacements of the mask pattern that translate to lateral displacement of the image, leading to overlay errors. The equation describing the relationship of the lateral displacement and the lack of flatness has been reported in an earlier article².

where m is the reduction ratio of the imaging optics; θ, chief ray angle; δZ_long, mask translation in the longitudinal direction. From Table 1, the single machine overlay tolerance is 1.5 nm. Allowing of the total overlay tolerance for mask flatness variation, then δx’_lat =1.06 nm. Substituting m = 4 and θ = 6° sets δZ_long to 20.2 nm. Hence, the flatness of EUV mask has to be within 20 nm for the 7-nm node. For the 5-nm node, with SMO=1 nm, the EUV mask flatness has to be better than 13.5 nm. In comparison, a very good mask for immersion lithography is specified for 500-nm flatness.

Mask flatness irregularity may be induced by substrate flatness, chucking errors, contamination of the mask, and stress. Naturally, maskless lithography systems are free from mask contributions to overlay error. In addition, the mask overlay budget can be waived to enlarge the wafer budget.

2.6

Elimination of overlay budget for mask

Maskless lithography systems can allocate the entire CDU and overlay budget to the wafer, instead of having to share the budget with the mask. This is a significant advantage in improving the overlay accuracy.

2.7

Contribution from multiple patterning

Because the NA and wavelength of immersion tools are fixed, multiple patterning is used to reduce pitch after the 28-nm node. The extra masking inevitably leads to indirect alignment. When many multiple patterning layers are aligned to each other, there can be higher-order indirect alignment. Figure 5 shows the situation of aligning a 2P2E layer to 3P3E which is aligned to another 2P2E layer. As high as 3^rd order alignment is produced, worsening the overlay accuracy by 2X. The most straightforward remedy is to use 1P1E. However, mixing 1P1E with multiple patterning layers cannot alleviate the problem. Figure 6 shows the situation of aligning a 1P1E layer to the stack in Fig. 5. Even though a 1P1E layer is used, 3^rd order alignment is still present. To take advantage of 1P1E, all critical alignment layers have to be 1P1E. Therefore, all critical alignment layers have to use EUV, MEB DW, or a mixture of them.

Fig. 5.

Overlay tree of 2P2E aligned to 3P3E on 2P2E. Indirect alignments up to the 3^rd order are present.

Fig. 6.

Overlaying a 1P1E layer on multiply patterned layers cannot eliminate high-order alignments.

2.8

Self-aligned processes

To overcome the mechanical limitation in overlay, self-aligned processes have to be developed. A well-known self-align process³ is shown in Fig. 7. After the poly-Si gate, shallow trench isolation, source and drain are formed. The self-aligned silicide is produced by depositing a layer of the desired metal, such as Ti or Ni, to react with Si at elevated temperature. After the silicide is formed, the unreacted metal is removed selectively with an etch solution. No masking is needed to form the self-aligned silicide in the source and drain.

Fig. 7

Self-aligned silicide process

The spacer technique is also a self-aligned process. It is shown in Fig. 8. The sidewall spacers are self-aligned to the mandrels to form higher-resolution patterns. Removal of the mandrel and cutting of the loops are often necessary.

Fig. 8.

The spacer technique to double resolution.

We need to develop many new self-aligned processes to meet the need of the ever tightening overlay accuracy.

2.9

Overlay-immune designs

There is no reason that overlay friendly circuit designs cannot be made. Designers should realize the mechanical limit of overlay accuracy and help to reduce the dependency on it. An example of overlay-immune design is to split the via layer according to the split of the metal layer that is to be aligned upon. Cross alignment between the split patterns⁴ is removed.

3.1

Immersion lithography

The resolution of ArF water immersion lithography peaks at NA=1.35 at the 193-nm ArF wavelength. The resolution of photon-based imaging systems is governed by the scaling equation,

Where W is the half pitch of the feature to be printed; k₁, the resolution scaling coefficient; NA, the numerical aperture of the imaging lens; λ, the imaging wavelength. With NA and λ fixed, the only possibility to increase resolution is by reduction of k₁. With much work and accumulated experience, the industry can reduce k₁ to <0.3. Even though the absolute limit of k₁ is 0.25, it is quite impossible to reduce it further from 0.28, i.e. 40 nm half pitch. Similarly, the ultimate limit of the NA in the ArF water immersion system is 1.44 but it is not wise to increase it beyond 1.35. The lens will be very difficult to design and extremely expensive to build, not to mention the possibility of losing depth of focus (DOF) and field size, thus decreasing the productivity of the immersion scanner. The industry has manufactured circuits with immersion scanners at resolutions exceeding the capability of these scanners, by resorting to pitch splitting using the multiple patterning technique, the spacer technique, or a combination of them. The tradeoff is throughput and process complexity. There are unexpected advantages with the pitch splitting technique.

3.2

EUV lithography

EUV lithography uses λ=13.5 nm at NA=0.33. It is impossible to reduce the wavelength further with limited time, resource, and positive experience to draw upon. Because of higher level of stray light, less accurate optical precision, oblique chief ray, limited resolution enhancement techniques, and 3D masks, the difficulty of imaging at k₁<0.4 is no less than k₁=0.28 in ArF immersion imaging, leading to 16.2 nm half pitch, slightly larger than the required 15 nm for the 7-nm node shown in Table 1. EUV lenses with NA>0.33 have been discussed⁵ but it is not wise to use higher NA EUV lenses. Similar to immersion lithography, the DOF and field size will suffer, losing process window and productivity, and necessitating new tools for the next generation. It is better to depend on multiple patterning, the spacer technique, or a combination of them to improve resolution just as in the case of immersion lithography. The tradeoff is throughput and process complexity just as multiple patterning in immersion lithography

3.3

MEB DW lithography

E-beam imaging has the potential of extremely high resolution and large processing window. Figure 9 shows simulated imaging results from a 100 keV, 80X reduction e-beam column design for use in the REBL system⁶. The imaging current per column is 1.5 μA, sufficient to support more than 85 wph for holes, using 3x36 columns. The processing window is 1.3 μm DOF at 15% exposure latitude for holes and 1 μm DOF at 10% exposure latitude for lines and spaces. These windows are common window of dense and isolated patterns at the edge and the center of the e-beam column ⁷, ⁸ . With immersion lithography and EUVL struggling with DOF in the sub-hundred nm regime, having micrometer level DOF is a luxury.

Fig. 9

Simulated processing window of L/S and hole patterns for the 7-nm node. These are the common window of isolated and dense patterns at the edge and the center of the e-beam column.

3.4

Resolution limit post by resists

Resist blur has become a key limiting factor on resolution for the 7- and the 5-nm nodes. Even though Fig. 9 shows that a 10-nm resist blur can support the 7-nm node in MEB, it is more difficult for EUVL. Figure 10 shows the image intensity distribution⁹ from a 0.33 NA lens at λ=13.5 nm. The image contrast rapidly drops when the resist blur is 7 or 9 nm. For the most critical layers in the 7-nm node, we may have to use EUV double patterning unless the resist blur can be kept below 5 nm. For the 5-nm node, MEB DW also requires resist blur smaller than 10 nm to facilitate single patterning. The situation is summarized in Table 2.

Fig. 10.

Simulated EUV image intensity of 30-nm pitch gratings at resist blurs=0, 7, and 9 nm. The pitch of the image is 30 nm.

Table 2.

Impact from resist blur.

The resist thickness is also a limiting factor. The height-to-width ratio in the resist image is generally capped at 3:1 to prevent resist collapse from the drying process¹⁰ during development. For a 10-nm feature, a mere 30 nm of resist thickness has to serve as an etch mask. The etching resistance has to be managed or the adhesion of the resist has to be increased to use a higher aspect ratio to support etching.

Line width roughness (LWR) is also of great concern. Using the same image under the same processing condition, there is a tradeoff between LWR and the EUV exposure dosage as seen in Fig. 11. A higher dosage reduces the LWR at the expense of throughput, thus, cost. The curve can be moved to the left for better LWR only by increasing the image contrast, using the spacer technique, or directed self-assembly.

Fig. 11.

Tradeoff between LWR and resist sensitivity

In summary, the resist blur, thickness, sensitivity, and LWR have to be suitable for the 7- and the 5-nm nodes.

4.1

Defects on Mask

4.1.1

Defects in mask blank

It is extremely rare to find defects on mask blanks for optical lithography. The spec is zero. EUV lithography is a different story. Because of the extremely short wavelength and the reflective mode, a longitudinal surface irregularity of 13.5/4=3.4 nm can cause a π shift. This irregularity can be in the EUV mask substrate as well in the multi-layer for reflection. As of 2014Q4 the average count for defect size 23 nm and larger is 34 per blank¹⁰. There is still room for improvement. Many of these defects can be mitigated by globally shifting the mask patterns to maximize their coverage. Figure 12 shows mitigation of EUV mask blank defects using this scheme. The effectiveness of this scheme is dependent on the mask pattern density. There is a higher chance of success with contact and via layers.

Fig. 12.

Global mask pattern shift to mitigate EUV mask blank defects.

4.1.2

Defect repair

Similar to mask writing, repair of patterned absorber is not much different between optical and EUV lithography systems. Figure 13 shows some sample opaque and clear defects on EUV masks¹¹. The mask images before and after repair are shown, as well as the wafer image from the repaired mask. Defects from patterned absorbers are manageable.

Fig. 13.

Sample EUV opaque and clear defects, before and after repair.

4.1.3

Defect build up

During mask loading and unloading from the EUV scanner, the mask carrier, or any other equipment, during exposure or other processes, the mask can be contaminated. Figure 14 shows¹² a 1-μm size particle attached to the mask during step-and-scan exposure. The 1^st 16 fields had clean wafer images. At the 17^th field, a particle appeared and its image repeated through the rest of the fields. This type of defect build up occurred many times. The material has been found to be Sn or Ru. Hence, EUV pellicle is necessary. Pellicle life under intense EUV radiation and pellicle mounting stress causing overlay errors are challenges.

Fig. 14.

A micrometer-size particle deposited on the EUV mask during scan-and-repeat exposure.

Another type of mask defect is contamination at the back side of the mask substrate¹¹, as shown in Fig. 15. If this defect is not removed before chucking, there is a higher probability of removal failure. The particle removal efficiency drops from 89% to 72% after chucking. Backside contamination on masks can cause overlay error and loss of DOF.

Fig. 15.

Particle removal efficiency of chucked and unchucked masks with backside particle.

4.1.4

Defects on maskless masks

The REBL MEB maskless system also has a mask contamination problem. Even though it does not replicate a mask image, it demagnifies the dynamic image on the dynamic pattern generator (DPG) just the same. Any particle falling on it can potentially produce a repeating defect. The REBL team was aware of this defect potential and had incorporated the time delay and integration (TDI) mode ¹³, as shown in Fig. 16. The sensitivity to contamination on the DPG is reduced with redundancy. First, 5 levels of grey is used to define the position of each graphic element on wafer. Each bit is determined by a pixel on the DPG As the pixel is turned on and off dynamically while the wafer is being scanned in the horizontal direction, the exposure accumulates to define the position of the graphic element on wafer. An additional level of grey is used to even out the differences between DPG pixels at different positions in the DPG and at different columns. This 2⁶ array is repeated four times to further increase the redundancy. Hence, there is a total of 2⁸ bits in the array to define the position of a pixel. When one bit is missed, only 1/256 exposure is affected. To make the exposure of one data point exceed 10% exposure latitude, there has to be 26 bad pixels lined up in the scan direction. Therefore, the 2⁸ redundancy makes the REBL system much less sensitive to contamination. The 80X reduction ratio of the REBL column also helps to screen out small defects.

Fig. 16.

TDI scheme makes the DPG much less to contaminations.

4.2

Defects on Wafer

Defects on wafer can be classified by their cause. They can be already on the wafer before lithography just as defects imbedded in the mask blank. They can be process induced, tool induced, or material induced. Unfortunately, defects on wafer cannot be repaired as those on mask, due to complexity and cost.

Defects generated by non-lithographic processes such as etch, CMP, etc. can cause overlay error and reduce DOF as discussed in Sections 2.1 and 2.2. They may cause electrical problems in addition to just lithography problems.

For defects deposited on wafer during exposure on immersion tools, improper wetting and bubble generation from the immersion fluid may be defect sources but they have long been taken care of, except for tightening of defect size specification in each node advance or for increasing the scan speed. For EUVL and MEB DW, the electrostatic chuck may be a defect getter. In the former, there may be presence of tin in the exposure chamber to be trapped electrostatically. Because the defect generation mechanisms are different, it is incorrect to assume that nPnE in immersion lithography produces more defects than 1P1E in EUVL or MEB DW.

Defects generated from other lithographic processes such as coating, baking, and drying, have equal opportunity of occurrence for immersion lithography, EUVL, or MEB DW. They are becoming more and more difficult to mitigate.

Defects in incoming materials are also of concern. The materials suppliers have to upgrade their factory on defect level in their materials for each node.

5.1

Cost of optical lithography

The cost of optical lithography and that of immersion lithography in particular, can escalate in several ways. Obviously, it is directly related to the number of masking layers required of the next generation. Starting from the 20-nm node, the number of masking layers increases faster than the historical trend, due to multiple patterning. The number of mask splits for each circuit layer can increase beyond two, for a particular geometry. This increase is alarming not only for cost but also for process complexity and overlay accuracy. One of the important tasks for lithography engineers is to innovatively reduce the number of masking layers without trading off density and electrical performance.

Another cost contributor is the exposure tool. Even though the NA of tools does not increase any further, the overlay performance of the exposure tool has to improve, making the tool price increase substantially. Also, the increase of wafer throughput is slowing down. The historically effective cost reduction scheme is becoming less effective.

Due to the requirement of better CD uniformity and low defect level, the wafer processing tracks as well as the processing materials such as resists, under layers, etc. also become more costly.

5.2

Cost of EUVL

The most significant cost factor in EUVL is wafer throughput. The EUV exposure tools are inevitably more expensive than optical tools, immersion scanners included. The wafer throughput is also lower than that of optical tools. One saving grace is that single patterning in EUV can replace multiple patterning, which has a turnover point at about 3P3E with EUV tool delivering 250 W to produce 100 wph. Of course, when EUV 2P2E has to be used, as discussed in Sec. 3.4, the turnover point moves to 6P6E of optical tools. To be precise on the turnover point, we have to consider tool maintenance and utility costs, EUV mask blank cost, mitigation of blank defects, reparability, contamination, mask cleaning life time, cost and lifetime of pellicles, as well as the cost of mask inspection and repair verification tools.

A yet undetermined cost component is wafer throughput gated by resist sensitivity and shot noise. Delineating small 2-D features with acceptable CDU requires exposure dosages in the order of 60 mJ/cm², which was predicted theoretically¹⁴ and experienced in the lab. This dosage is 3 times higher than the rated dosage and can severely impact EUV productivity, thus cost. Reference 14 concluded that 1000 W of EUV power is necessary to make EUVL cost effective.

5.3

Cost of MEB DW lithography

For MEB DW the cost differentiator is number of columns and the corresponding data path for each column, because of the sheer number of columns required. It is desirable to make 108-column MEB exposure cost for L/S per move similar to that of EUVL at 125 W source power. For holes, because of a lower pattern density, the MEB exposure cost should be made roughly half of that of EUVL at 250 W source power. Under these conditions, the exposure cost of MEB DW is approximately equivalent to that of 2P2E in immersion lithography.

For less critical layers, the space-charge limit of the MEB column is relaxed, enabling higher current for imaging. Also, shot noise is less severe, allowing resist of higher sensitivity. Wafer throughput is increased. It is economically feasible to use MEB DW for all circuit layers, critical and non-critical¹. In addition to economy, the overlay accuracy, mask cost and cycle time savings are also advantageous.

5.4

Mixing immersion, EUV, and MEB layers

Mixing nPnE immersion L/S exposure with MEB cutting and MEB hole imaging is the most cost-effective way to pattern wafers. When n becomes unbearably costly, an economical EUV L/S exposure can be mixed with MEB cutting and hole imaging. This plays into the high-throughput potential in MEB DW on low pattern density layers and the relatively higher resist sensitivity that can be used for EUV L/S patterning. As discussed in Sec. 5.2, delineating holes and cutting layers can significantly reduce EUV exposure productivity. There is one concern. It is more difficult to mitigate mask blank defects for the L/S layers. The EUV/MEB mix requires mask blanks to reach a usable defect level.

Overlay accuracy is also of concern with mixing of these tools. A more than economical desired number of EUV layers may have to be incorporated to attain the required overlay accuracy. It is less of a concern with the Immersion/MEB mix because high-order overlay matching is feasible for MEB DW as shown in Sec. 2.4.

5.5

Cost comparison

Following the considerations above, three case studies were performed to compare ArF water immersion, EUVL mixed with ArF immersion at two different EUV source power levels, and MEB mixed with ArF immersion, as shown in Table 3. Costs are compared to that of the 10-nm node. The most expensive situation can be 2.4 times the cost of the 10-nm node and is unacceptable for the Moore’s law of economy. Case 3 is more cost effective, even though still costly in terms of economy of node advancement. Only MEB-ArFi approaches an acceptable cost target according to Table 1. EUV-ArF_i at 250 W has the opportunity of being slightly less expensive than pure ArF_i, if the exposure dosage can be kept at the rated 20 mJ/cm².

Table 3.

Cost comparison for the 7-nm node.