This PDF file contains the front matter associated with SPIE Proceedings Volume 9777 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

Optical lithography resolution scaling has stalled, giving innovative alternatives a window of opportunity. One important factor that impacts these lithographic approaches is the transition in design style from 2D to 1D for advanced CMOS logic. Just as the transition from 3D circuits to 2D fabrication 50 years ago created an opportunity for a new breed of electronics companies, the transition today presents exciting and challenging time for lithographers. Today, we are looking at a range of non-optical lithography processes. Those considered here can be broadly categorized: self-aligned lithography, self-assembled lithography, deposition lithography, nano-imprint lithography, pixelated e-beam lithography, shot-based e-beam lithography .Do any of these alternatives benefit from or take advantage of 1D layout? Yes, for example SAPD + CL (Self Aligned Pitch Division combined with Complementary Lithography). This is a widely adopted process for CMOS nodes at 22nm and below. Can there be additional design / process co-optimization? In spite of the simple-looking nature of 1D layout, the placement of “cut” in the lines and “holes” for interlayer connections can be tuned for a given process capability. Examples of such optimization have been presented at this conference, typically showing a reduction of at least one in the number of cut or hole patterns needed.[1,2] Can any of the alternatives complement each other or optical lithography? Yes.[3] For example, DSA (Directed Self Assembly) combines optical lithography with self-assembly. CEBL (Complementary e-Beam Lithography) combines optical lithography with SAPD for lines with shot-based e-beam lithography for cuts and holes. Does one (shrinking) size fit all? No, that’s why we have many alternatives. For example NIL (Nano-imprint Lithography) has been introduced for NAND Flash patterning where the (trending lower) defectivity is acceptable for the product. Deposition lithography has been introduced in 3D NAND Flash to set the channel length of select and memory transistors.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made overlay, throughput and defectivity and to introduce the FPA-1200NZ2C cluster system designed for high volume manufacturing of semiconductor devices. in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm. Overlay results better than 5nm 3sigma have been demonstrated. To further enhance overlay, wafer chucks with improved flatness have been implemented to reduce distortion at the wafer edge. To address higher order corrections, a two part solution is discussed. An array of piezo actuators can be applied to enable linear corrections. Additional reductions in distortion can then be addressed by the local heating of a wafer field. The NZ2C cluster platform for high volume manufacturing is also discussed. System development continues this year with a target for introduction later in 2016. The first application is likely to be NAND Flash memory, and eventual use for DRAM and logic devices as both overlay and defectivity improve.

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are two critical components to meeting throughput requirements for imprint lithography. Using a similar approach to what is already done for many deposition and etch processes, imprint stations can be clustered to enhance throughput. The FPA-1200NZ2C is a four station cluster system designed for high volume manufacturing. For a single station, throughput includes overhead, resist dispense, resist fill time (or spread time), exposure and separation. Resist exposure time and mask/wafer separation are well understood processing steps with typical durations on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 15 wafers per hour (wph) for a single station, it is necessary to complete the fluid fill step in 1.5 seconds. For a throughput of 20 wph, fill time must be reduced to only one second. There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which address drop spreading after jetting), Design for Imprint or DFI (to accelerate drop spreading) and material engineering (to promote wetting between the resist and underlying adhesion layer). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. In this paper, we address the improvements made in all of these parameters to enable a 1.50 second filling process for a sub-20nm device like pattern and have demonstrated this capability for both full fields and edge fields.

A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm. Hard particles on a wafer or mask create the possibility of creating a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, test stand results demonstrate the potential for extending mask life to better than 1000 wafers. Additionally, a new replication tool, the FPA-1100 NR2 is introduced. Mask chuck flatness simulation results were also performed and demonstrate that residual image placement errors can be reduced to as little as 1nm.

Roll-to-Roll-UV-nanoimprint lithography (R2R-UV-NIL) enables high resolution large area patterning of flexible substrates and is therefore of increasing industrial interest. We have set up a custom-made R2R-UV-NIL pilot machine which is able to convert 10 inch wide web with velocities of up to 30 m/min. In addition, we have developed self-replicable UV-curable resins with tunable surface energy and Young’s modulus for UV-imprint material as well as for polymer working stamp/shim manufacturing. Now we have designed test patterns for the evaluation of the impact of structure shape, critical dimension, pitch, depth, side wall angle and orientation relative to the web movement onto the imprint fidelity and working shim life time. We have used female (recessed structures) silicon masters of that design with critical dimensions between CD = 200 nm and 1600 nm, and structure depths of d = 500 nm and 1000 nm - all with vertical as well as inclined side walls. These entire master patterns have been transferred onto single male (protruding structures) R2R polymer working shims. The polymer working shims have been used for R2R-UV-NIL runs of several hundred meters and the imprint fidelity and process stability of the various test patterns have been compared. This study is intended as a first step towards establishing of design rules and developing of nanoimprint proximity correction strategies for industrial R2R-UV-NIL processes using polymer working shims.

Full-field, physically-based simulation of nanoimprint lithography (NIL) is needed to address the throughput-versus-yield challenges that are currently faced by NIL. We demonstrate a simulation framework that can track the spreading and coalescence of tens of thousands of picoliter-volume resin droplets beneath a nanoimprint template, predicting evolution of feature filling and residual layer thickness (RLT) uniformity during the imprinting of geometrically complex designs such as found in solid-state memory. We have used the framework to explore directionality of droplet spreading beneath patterned templates, the role of template curvature in mitigating gas entrapment, and detrimental elastic deflections at wafer-edge partial imprint fields.

Directed self-assembly (DSA) is one of the candidates for next generation lithography. Over the past few years, cylindrical and lamellar structures dictated by the block co-polymer (BCP) composition have been investigated for use in patterning contact holes or lines, and, Tokyo Electron Limited (TEL is a registered trademark or a trademark of Tokyo Electron Limited in Japan and /or other countries.) has presented the evaluation results and the advantages of each-^1-5. In this report, we will present the latest results regarding the defect reduction work on a model line/space system. Especially it is suggested that the defectivity of the neutral layer has a large impact on the defectivity of the DSA patterns. Also, LER/LWR reduction results will be presented with a focus on the improvements made during the etch transferring the DSA patterns into the underlayer.

This manuscript shows the relationship between defectivity of a typical chemo-epitaxy sequence and the DSA-specific materials, namely the mat, the brush and the block co-polymer. We demonstrate that the density of assembly defects in a line-space DSA flow, namely the dislocations and 1-period bridges have a direct correlation to certain parameters in the synthesis sequence of these materials. The primary focus of this manuscript is on identifying, controlling and reproducing the defects-critical parameters in the block co-polymer synthesis process for a stable and low defect performance of DSA flows.

In next generation lithography to make sub-15nm pattern, Directed self-assembly (DSA) and Nano-imprint lithography (NIL) are proposed. The current DSA process is complicated and it is difficult to decrease width and line edge roughness of a guide pattern for sub-15nm patterning. In the case of NIL, it is difficult to make the master template having sub- 15nm pattern. This paper describes cost-effective lithography process for making sub-15nm pattern using DSA on a guide pattern replicated by Nano-imprinting (NIL + DSA). Simple process for making sub-15nm pattern is proposed. The quartz templates are made and line/space patterns of half pitch (hp) 12nm and hp9.5nm are obtained by NIL + DSA.

Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.

Recent industrial results around directed self-assembly (DSA) of block copolymers (BCP) have demonstrated the high potential of such technique. One of the main advantages of this method is the reduction of lithographic steps thus leading to cost reduction. At the same time, the associated correction for mask creation must account for the introduction of this new technique maintaining a high level of accuracy and reliability. In order to create a Vertical Interconnect Layer (VIA) layer, graphoepitaxy DSA is the main candidate. The technique relies on the creation of a confinement guide where the BCP can separate into distinct regions and the resulting patterns are etched in order to obtain an ordered contact layer. The printing of the guiding pattern requires a classical lithography and optical proximity correction (OPC) to obtain the best suited guiding pattern for a specific target. Thus it is necessary to perform simulations of the BCP behavior in order to correctly determine contact hole placement. However, most existing models which simulates the BCP phase segregation have a computational cost that is too high and cannot be used to efficiently correct a full layout. In this study, we propose an original compact model that resolves this issue. The model is based on the calculation of the density probability of PMMA (Polymethyl Methacrylate) domain centers (figure 1). It is compared with both rigorous simulations (based on the Otha-Kawasaki model) and experiments as shown in figure 2. For this analysis, test cases are contact shrink and contact multiplication. The number of PMMA domains inside a structure is also discussed and an analytic formula is derived and compared to experiments (figure 3). The overall consistency of the compact model is presented.

In this paper, we present a DSA compliant flow for contact/via layers with immersion lithography assuming the grapho-epitaxy process for cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use Template Error Enhancement Factor (TEEF) to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data shows that it is promising to achieve 2-mask solution with DSA for the contact/via layer using 193i at 5nm node.

Directed Self-Assembly (DSA) is a well-known candidate for next generation sub-15nm half-pitch lithography. ^[1-2] DSA processes on 300mm wafers have been demonstrated for several years, and have given a strong impression due to finer pattern results. ^[3-4] On t he other hand, specific issues with DSA processes have begun to be clear as a result of these recent challenges. ^[5-6] Pattern placement error, which means the pattern shift after DSA fabrication, is recognized as one of these typical issues. Coat-Develop Track systems contribute to the DSA pattern fabrication and also influence the DSA pattern performance.^[4] In this study, the placement error was investigated using a simple contact-hole pattern and subsequent contact-hole shrink process implemented on the SOKUDO DUO track. Thus, we will show the placement error of contact-hole shrink using a DSA process and discuss the difference between DSA and other shrink methods.

Directed self-assembly (DSA) of block copolymers (BCP) has attracted significant interest as a patterning technique over the past few years. We have previously reported the development of a new process flow, the CHIPS flow (Chemo-epitaxy Induced by Pillar Structures), where we use ArFi lithography and plasma etch to print guiding pillar patterns for the DSA of cylindrical phase BCPs into dense hexagonal hole arrays of 22.5 nm half-pitch and 15 nm half-pitch [1]. The ability of this DSA process to generate dense regular patterns makes it an excellent candidate for patterning memory devices. Thus, in this paper we study the applicability of the CHIPS flow to patterning for DRAM storage layers. We report the impact of various process conditions on defect density, defect types and pattern variability. We also perform detailed analysis of the DSA patterns, quantify pattern placement accuracy and demonstrate a route towards excellent LCDU after pattern transfer into a hard mask layer.

Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.

In this paper, we focus on the directed-self-assembly (DSA) application for contact hole (CH) patterning using polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymers (BCPs). By employing the DSA planarization process, we highlight the DSA advantages for CH shrink, repair and multiplication which are extremely needed to push forward the limits of currently used lithography. Meanwhile, we overcome the issue of pattern densityrelated- defects that are encountered with the commonly-used graphoepitaxy process flow. Our study also aims to evaluate DSA performances as function of material properties and process conditions by monitoring main key manufacturing process parameters: CD uniformity (CDU), placement error (PE) and defectivity (Hole Open Yield = HOY). Concerning process, it is shown that the control of surface affinity and the optimization of self-assembly annealing conditions enable to significantly enhance CDU and PE. Regarding materials properties, we show that the best BCP composition for CH patterning should be set at 70/30 of PS/PMMA total weight ratio. Moreover, it is found that increasing the PS homopolymer content from 0.2% to 1% has no impact on DSA performances. Using a C35 BCP (cylinder-forming BCP of natural period L₀ = 35nm), high DSA performances are achieved: CDU-3σ = 1.2nm, PE-3σ = 1.2nm and HOY = 100%. The stability of DSA process is also demonstrated through the process follow-up on both patterned and unpatterned surfaces over several weeks. Finally, simulation results, using a phase field model based on Ohta-Kawasaki energy functional are presented and discussed with regards to experiments.

Directed self-assembly using block copolymers for positioning vertical interconnect access in integrated circuits relies on the proper shape of a confined domain in which polymers will self-assemble into the targeted design. Finding that shape, i.e., solving the inverse problem, is currently mainly based on trial and error approaches. We introduce a level-set based algorithm that makes use of a shape optimization strategy coupled with self-consistent field theory to solve the inverse problem in an automated way. It is shown that optimal shapes are found for different targeted topologies with accurate placement and distances between the different components.

In this paper, we study the impact of topographic guide or template properties on pattern formation in a directed self-assembly (DSA) process. In particular, we investigate the relationship between free energy and defect generation or process robustness, and analyze the influence of guide affinity. The good correlation between experimental and simulation results confirms the role of certain setup parameters and process conditions on the DSA patterning.

For Directed Self-Assembly (DSA) to be deployed in advanced semiconductor technologies, it must reliably integrate into a full process flow. We present a methodology for using virtual fabrication software, including predictive DSA process models, to develop and analyze the replacement of SAQP patterning with LiNe chemoepitaxy on a 14nm DRAM process. To quantify the impact of this module replacement, we investigate a key process yield metric for DRAM: interface area between the capacitor contacts and transistor source/drain. Additionally, we demonstrate virtual fabrication of the DRAM cell’s hexagonally-packed capacitors patterned with an array of diblock copolymer cylinders in place of LE4 patterning.

Developments of a Micro Electro-Mechanical System (MEMS) electrostatic Condenser Lens Array (CLA) for a Massively Parallel Electron Beam Direct Write (MPEBDW) lithography system are described. The CLA converges parallel electron beams for fine patterning. The structure of the CLA was designed on a basis of analysis by a finite element method (FEM) simulation. The lens was fabricated with precise machining and assembled with a nanocrystalline silicon (nc-Si) electron emitter array as an electron source of MPEBDW. The nc-Si electron emitter has the advantage that a vertical-emitted surface electron beam can be obtained without any extractor electrodes. FEM simulation of electron optics characteristics showed that the size of the electron beam emitted from the electron emitter was reduced to 15% by a radial direction, and the divergence angle is reduced to 1/18.

The emerging Massively Parallel-Electron Beam Direct Write (MP-EBDW) is an attractive high resolution high throughput lithography technology. As previously shown, Chemically Amplified Resists (CARs) meet process/integration specifications in terms of dose-to-size, resolution, contrast, and energy latitude. However, they are still limited by their line width roughness. To overcome this issue, we tested an alternative advanced non-CAR and showed it brings a substantial gain in sensitivity compared to CAR. We also implemented and assessed in-line post-lithographic treatments for roughness mitigation. For outgassing-reduction purpose, a top-coat layer is added to the total process stack. A new generation top-coat was tested and showed improved printing performances compared to the previous product, especially avoiding dark erosion: SEM cross-section showed a straight pattern profile. A spin-coatable charge dissipation layer based on conductive polyaniline has also been tested for conductivity and lithographic performances, and compatibility experiments revealed that the underlying resist type has to be carefully chosen when using this product. Finally, the Process Of Reference (POR) trilayer stack defined for 5 kV multi-e-beam lithography was successfully etched with well opened and straight patterns, and no lithography-etch bias.

Massively parallel mask-less electron beam lithography (MP-EBL) offers a large intrinsic flexibility at a low cost of ownership in comparison to conventional optical lithography tools. This attractive direct-write technique needs a dedicated data preparation flow to correct both electronic and resist processes. Moreover, Data Prep has to be completed in a short enough time to preserve the flexibility advantage of MP-EBL. While the MP-EBL tools have currently entered an advanced stage of development, this paper will focus on the data preparation side of the work for specifically the MAPPER Lithography FLX-1200 tool [1]-[4], using the ASELTA Nanographics Inscale software. The complete flow as well as the methodology used to achieve a full-field layout data preparation, within an acceptable cycle time, will be presented. Layout used for Data Prep evaluation was one of a 28 nm technology node Metal1 chip with a field size of 26x33mm², compatible with typical stepper/scanner field sizes and wafer stepping plans. Proximity Effect Correction (PEC) was applied to the entire field, which was then exported as a single file to MAPPER Lithography’s machine format, containing fractured shapes and dose assignments. The Soft Edge beam to beam stitching method was employed in the specific overlap regions defined by the machine format as well. In addition to PEC, verification of the correction was included as part of the overall data preparation cycle time. This verification step was executed on the machine file format to ensure pattern fidelity and accuracy as late in the flow as possible. Verification over the full chip, involving billions of evaluation points, is performed both at nominal conditions and at Process Window corners in order to ensure proper exposure and process latitude. The complete MP-EBL data preparation flow was demonstrated for a 28 nm node Metal1 layout in 37 hours. The final verification step shows that the Edge Placement Error (EPE) is kept below 2.25 nm over an exposure dose variation of 8%.

As the integration node becomes smaller in 193nm ArF immersion optical lithography, the complexity of optical proximity correction (OPC) has been increased continuously. Moreover, pattern design should be changed by more aggressive transformation technique such as inverse lithography technique (ILT). The greater fidelity to the target design on wafers is achieved by the application of these OPC techniques and results in the greater complexity level of the mask patterns. Complicated mask pattern consists of many corners and assist features, which raises the fraction of small shots in e-beam data. To get more accurate mask pattern, the dose stability of small shots becomes more important in a complicated mask pattern. In this paper, we present the evaluation results of the small shot handling capabilities of e-beam machines. According to the results, the information of small shots generated during data fracturing should be considered as a factor that defines the complexity of patterns in e-beam writing. It shows that the small shot printing in e-beam machines need to be improved in order to guarantee mask pattern quality.

This paper is about positioning error of photomask by resist charge up effect in the EB lithography. We postulated that charges created by incident electron beam in the photomask form electric dipoles perpendicular to its surface by the electron image effect from metal film. The formed electric dipole distributions depending on writing patterns deflect the orbit of the electron beam . We have simulated the deflection of the electron beam by the dipole produced at the surface and obtained the dipole distribution that led to the experimentally measured position error for a test writing pattern. Our model will be useful to predict the positioning error in EB lithography.

Overlay errors, cut/block and line/space critical-dimension (CD) variations are the major sources of the edge-placement errors (EPE) in the cut/block patterning processes of complementary lithography when IC technology is scaled down to sub-10nm half pitch (HP). In this paper, we propose and discuss a modular technology to reduce the EPE effect by combining selective etching and alternating-material (dual-material) self-aligned multiple patterning (altSAMP) processes. Preliminary results of altSAMP process development and material screening experiment are reported and possible material candidates are suggested. A geometrical cut-process yield model considering the joint effect of overlay errors, cut-hole and line CD variations is developed to analyze its patterning performance. In addition to the contributions from the above three process variations, the impacts of key control parameters (such as cut-hole overhang and etching selectivity) on the patterning yield are examined. It is shown that the optimized altSAMP patterning process significantly improves the patterning yield compared with conventional SAMP processes, especially when the half pitch of device patterns is driven down to 7 nm and below.

In this paper, we experimentally demonstrated a new technique of electric-field assisted assembly of core-shell particles to create uniform contact hole array with complex geometries. A spatially varying dielectrophoretic (DEP) force created by lithographically defined guiding features is used to control the particle position. The influence of the predefined guiding features on contact hole pattern displacement is systematically studied. The results show that the center-to-center spacing rather than the size and shape of the guiding features determines the particle placement, which indicates the self-healing potential of this technique.

Tilted ion implantation (TII) is proposed as a lower-cost alternative to self-aligned double patterning (SADP) for pitch halving. This new approach is based on an enhancement in etch rate of a hard-mask layer by implant-induced damage. Ar⁺ implantation into a thin layer of silicon dioxide (SiO₂) is shown to enhance its etch rate in dilute hydrofluoric acid (HF) solution, by up to 9× for an implant dose of 3×10¹⁴ cm^-2. The formation of sub-lithographic features defined by masked tilted Ar⁺ implantation into a SiO₂ hard-mask layer is experimentally demonstrated. Features with sizes as small as ~21 nm, self-aligned to the lithographically patterned mask, are achieved. As compared with SADP, enhanced patterning by TII requires far fewer and lower-cost process steps and hence is expected to be much more cost-effective.

In this work, direct-write, high-resolution multiphoton photolithography using doped random methacrylic co-polymer thin films is demonstrated, using a continuous wave ultraviolet (UV) 375 nm diode laser source. The random copolymers are specifically designed for enhancing resolution and addressing issues arising from laser ablation processes, such as the berm-formation around the created holes in the film, which can be accessed by tuning the polymeric material properties including Tg, surface adhesion etc. The methacrylic copolymer is composed of monomers, each of them especially selected to improve individual properties. The material formulations comprise perylene molecules absorbing at the exposure wavelength where the polymeric matrix is transparent. It was found that if the radiation intensity exceeds a certain threshold, the perylene molecules transfer the absorbed light energy to the acrylate polymer matrix leading to polymer degradation and ablation of the exposed areas. The non-linear nature of the light absorption and energy transfer processes resulted in the creation of holes with critical dimensions well below the used wavelength reaching the sub 50 nm domain. Arrays of holes having various dimensions were fabricated in the laser ablation experiments using a directwrite laser system developed specifically for the purposes of this project.

Microcolumns are widely used for parallel electron-beam lithography because of their compactness and the ability to achieve high spatial resolution. A design of an electrostatic microcolumn for our recent nanoscale photoemission sources is presented. We proposed a compact column structure (as short as several microns in length) for the ease of microcolumn fabrication and lithography operation. We numerically studied the influence of several design parameters on the optical performance such as microcolumn diameter, electrode thickness, beam current, working voltages, and working distance. We also examined the effect of fringing field between adjacent microcolumns during parallel lithography operations. The microcolumns were also fabricated to show the possibility.

We demonstrate a novel approach for electron-beam lithography (EBL) of periodic nanostructures. This technique can rapidly produce arrays of various metallic and etched nanostructures with line and pitch dimensions approaching the beam spot size. Our approach is based on often neglected functionality which is inherent in most modern EBL systems. The raster/vector beam exposure system of the EBL software is exploited to produce arrays of pixel-like spots without the need to define coordinates for each spot in the array. Producing large arrays with traditional EBL techniques is cumbersome during pattern design, usually leads to large data files and easily results in system memory overload during patterning. In Dots-on-the-fly (DOTF) patterning, instead of specifying the locations of individual spots, a boundary for the array is given and the spacing between spots within the boundary is specified by the beam step size. A designed pattern element thus becomes a container object, with beam spacing acting as a parameterized location list for an array of spots confined by that container. With the DOTF method, a single pattern element, such as a square, rectangle or circle, can be used to produce a large array containing thousands of spots. In addition to simple arrays of nano-dots, we expand the technique to produce more complex, highly tunable arrays and structures on substrates of silicon, ITO/ FTO coated glass, as well as uncoated fused silica, quartz and sapphire.

A novel nanoimprint lithography process using disposable biomass template having gas permeability was investigated. It was found that a disposable biomass template derived from cellulose materials shows an excellent gas permeability and decreases transcriptional defects in conventional templates such as quartz, PMDS, DLC that have no gas permeability. We believe that outgasses from imprinted materials are easily removed through the template. The approach to use a cellulose for template material is suitable as the next generation of clean separation technology. It is expected to be one of the defect-less thermal nanoimprint lithographic technologies. It is also expected that volatile materials and solvent including materials become available that often create defects and peelings in conventional temples that have no gas permeability.

Nano-imprinting lithography (NIL) technology, as one of the most promising fabrication technologies, has been demonstrated to be a powerful tool for large-area replication up to wafer-level, with features down to nanometer scale. The cost of resists used for NIL is important for wafer-level large-area replication. This study aims to develop capabilities in patterning larger area structure using thermal NIL. The commercial available Poly (Methyl Methacrylate) (PMMA) and Polystyrene (PS) polymers possess a variety of characteristics desirable for NIL, such as low material cost, low bulkvolumetric shrinkage, high spin coating thickness uniformity, high process stability, and acceptable dry-etch resistance. PMMA materials have been utilized for positive electron beam lithography for many years, offering high resolution capability and wide process latitude. In addition, it is preferable to have a negative resist like PMMA, which is a simple polymer with low cost and practically unlimited shelf life, and can be dissolved easily using commercial available Propylene glycol methyl ether acetate (PGMEA) safer solvent to give the preferred film thickness. PS is such a resist, as it undergoes crosslinking when exposed to deep UV light or an electron beam and can be used for NIL. The result is a cost effective patterning larger area structure using thermal nano-imprint lithography (NIL) by using commercial available PMMA and PS ploymers as NIL resists.

Nanoimprint lithography (NIL) technology is in the spotlight as a next-generation semiconductor manufacturing technique for integrated circuits at 22 nm and beyond. NIL is the unmagnified lithography technique using template which is replicated from master templates. On the other hand, master templates are currently fabricated by electron-beam (EB) lithography[1]. In near future, finer patterns less than 15nm will be required on master template and EB data volume increases exponentially. So, we confront with a difficult challenge. A higher resolution EB mask writer and a high performance fabrication process will be required. In our previous study, we investigated a potential of photomask fabrication process for finer patterning and achieved 15.5nm line and space (L/S) pattern on template by using VSB (Variable Shaped Beam) type EB mask writer and chemically amplified resist. In contrast, we found that a contrast loss by backscattering decreases the performance of finer patterning. For semiconductor devices manufacturing, we must fabricate complicated patterns which includes high and low density simultaneously except for consecutive L/S pattern. Then it’s quite important to develop a technique to make various size or coverage patterns all at once. In this study, a small feature pattern was experimentally formed on master template with dose modulation technique. This technique makes it possible to apply the appropriate exposure dose for each pattern size. As a result, we succeed to improve the performance of finer patterning in bright field area. These results show that the performance of current EB lithography process have a potential to fabricate NIL template.

In this paper, we will discuss the improvement of resist pattern roughness on NTD (Negative Tone Development) resist by chemical shrink process. Chemical shrink process is one of the most practical approaches to achieve small feature size CH (Contact Hole) or trench with ArF immersion lithography. We found that this shrink material has not only general benefits of shrink process like DOF (Depth of Focus) margin improvement, but also demonstrates a pattern smoothing effect through observation of the surface of shrink layer using SPM (Scanning Probe Microscope). Additionally, an improvement of LWR (Line Width Roughness) over 16% and an improvement of LCDU (Local Critical Dimension Uniformity) around 60% were observed.

Electric field can induce long range flow in liquid materials. This phenomenon is known as liquid electromigration. In particular case of Cr thin film deposited on an insulating substrate, application of high electric-field between two point electrodes results in liquefaction and subsequent flow of the liquefied material in a radially symmetric fashion away from the cathode. This electric field driven material transport phenomenon has been used for a new patterning technique, named electrolithography. A negatively biased scanning probe is used to etch a thin Cr film according to a desired pattern. Then the pattern is transferred to new materials using a polymer layer below the metal film. Electrolithography does not need any UV or e-beam source, and can be performed in ambient condition. We have achieved pattern resolutions of 9 nm on the polymer and 40 nm on transferring the pattern to other materials. In this work, with the help of electrolithography, we have patterned large areas using vector scan technique. This improves throughput of the process by a significant order.

Pixelated wiregrids are of great interest in polarimetric imagers, but there are no straightforward methods available for combining the uniform exposures of laser interference with a masking system to achieve pixels at different rotational angles. In this work we demonstrate a 266nm deep-UV interference lithography combined with a traditional i-line contact lithography to create such pixels. Aluminum wiregrids are first made, following by etching to create the pixels, and then a planarizing molybdenum film is used before patterning subsequent pixel arrays. The etch contrast between the molybdenum and the aluminum enables the release of the planarizing layer.

In this study, we investigated a directed self-assembly (DSA) flow that could include a non-periodic pattern (i.e., wide line) lying in between the periodic line/space patterns, in a relatively simple and inexpensive way. A symmetric poly(styrene-block-methyl methacrylate) (PS-b-PMMA) with the natural periodicity (L₀) of 30 nm was employed here. Our DSA flow has two key features. First, we used a hybrid approach that combined chemoepitaxy and graphoepitaxy methods to generate PMMA-attractive pinning guide patterns directly from ArF resist. Second, we attempted to utilize both the perpendicular lamellae in the periodic regions and the horizontal lamellae on the non-periodic pattern as an etch template. The advantage of this process will be a reduction of the number of lithographic processes, whereas the challenge is how to control the mixed morphologies at the boundary between the periodic and non-periodic regions. Our preliminary results from simulations and experiments showed that, in order to generate the horizontal lamellae on the non-periodic pattern, the PS-b-PMMA thickness on top of the non-periodic guide pattern should roughly match to ~1 L₀, and the width of the non-periodic pattern should be larger than ~3-4 L0. In addition, the space between the periodic and non-periodic regions was found to be critical and it should be basically equal to the space between the guiding pins in the periodic regions (~75 nm) to minimize the formation of fingerprint morphology at the boundaries.

Directed self-assembly (DSA) of block copolymers (BCPs) with conventional lithography is being thought as one of the potential patterning solution for future generation devices manufacturing. New BCP platform is required to obtain resolution below 10nm half pitch (HP), better roughness, and defect characteristics than PS-b-PMMA. In this study, we will introduce the newly developed Si-containing high chi BCP which can apply perpendicular lamellar orientation with topcoat free, mild thermal annealing under nitrogen process conditions. It will be also shown in experimental results of graphoepitaxy demonstration for L/S multiplication using new high chi BCP.

Placement of cylinders in hole multiplication patterns for directed self-assembly is the topic of this computational study. A hole doublet process applying a corner rounded rectangle guide is the focus of this work. Placements including morphology fluctuation can be analyzed by dissipative particle dynamics simulation. When the surface of guides and underlayers are modified from strong polymethyl methacrylate (PMMA) attractive to weak PMMA attractive, two PMMA cylinders can be contacted at the underlayer. Even when the PMMA domain had a separated morphology, hole placement errors (HPE) were similar to those with connected domains which occurred in the strong PMMA affine case. In general, HPE in longitudinal guide direction was larger than in the shorter direction. It is interesting to note that HPE in the longer direction was decreased by increasing the guide size in shorter direction. Cylinder tops likely fluctuate; cylinder middles may fluctuate as well in some cases. Means for HPE reduction were also tested computationally: reducing the guide thickness and employing dimpled structures. Decreasing guide thickness was effective for reducing HPE; however, guide thicknesses that were too thin prevented PMMA domains from forming vertical cylinders. Dimpled structures also reduced HPE. The depth of the dimple had a little influence on the distance of two holes when the guide structure was fitted with hexagonal packing for the block co-polymers.

Si-rich poly((polyhedral oligomeric silsesquioxane) methacrylate)-b-poly(trifluoroethyl methacrylate) (PMAPOSS-b- PTFEMA) was used to form 8-nm half-pitch line and space (L/S) pattern via grapho-epitaxy. Vertical alignment of the lamellae was achieved without using either a neutral layer or top-coating material. Because PMAPOSS-b-PTFEMA forms vertical lamellae on a variety of substrates, we used two types of physical guide structures for grapho-epitaxy; one was a substrate guide and the other was a guide with an embedded under layer. On the substrate guide structure, a fine L/S pattern was obtained with trench widths equal to 3–7 periods of the lamella spacing of the block copolymer, L_o. However, on the embedded under layer guide structure, L/S pattern was observed only with 3 L_o and 4 L_o in trench width. Cross-sectional transmission electron microscope images revealed that a thick PMAPOSS layer was formed under the PMAPOSS-b-PTFEMA L/S pattern. Pattern transfer of the PMAPOSS-b-PTFEMA L/S pattern was prevented by a thick PMAPOSS layer. To achieve pattern transfer to the under layer, optimization of the surface properties is necessary.

Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)^{1– 3}. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm ⁴. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.

In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). DSA is now widely regarded as a leading complementary patterning technique for future node integrated circuit (IC) device manufacturing and is considered for the 7 nm node. One of the most straightforward approaches for implementation of DSA is via patterning by graphoepitaxy. In this approach, the guiding pattern dictates the location and pitch of the resulting hole structures while the material properties of the BCP control the feature size and uniformity. Tight pitches need to be available for a successful implementation of DSA for future node via patterning which requires DSA in small guiding pattern CDs. Here, we show strategies how to enable the desired CD shrink in these small guiding pattern vias by utilizing high χ block copolymers and/or controlling the surface properties of the template, i.e. sidewall and bottom affinity to the blocks.

Block copolymers, polymers composed of two or more homopolymers covalently bonded together, are currently being investigated as a method to extend optical lithography due to their ability to microphase separate on small size scales. In order to drive down the size that these BCPs phase separate, the BCPs with larger Flory-Huggin's χparameter needs to be found. Typically these BCPs are composed of more dissimilar homopolymers. However, changing these interactions also changes how BCPs interact with their guiding underlayers. In this paper, several block copolymers are simulated annealing on chemoepitaxial guiding underlayers using a coarse-grained molecular dynamics model in order to explore the effect that either energetic asymmetry or density asymmetry in the BCP have on the pattern registration. It is found that energetic asymmetry in BCPs causes one of the blocks to desire to skin, which shifts the composition of the background region that leads to well aligned vertical lamellae formation. It is hypothesized that moderate footing and undercutting at the underlayer or slight skinning at the free surface can increase the kinetics of defect annihilation by decreasing the distance that bridges must form. The density asymmetric BCPs simulated in this paper have different mechanical properties which lead to straighter sidewalls in the BCP film and potentially lead to better pattern registration. It is hypothesized that altering the compressibility of the blocks can alter equilibrium defectivity.

In this work, we present completely industry adapted processes for high-chi PS-PDMS block copolymers. DSA was performed on trenches fabricated within standard photolithography stacks and pattern transfer was made by using etching processes similar to those used for gate etching in industry. We propose the alignment of two different PS-PDMS (45.5kg/mol, 16kg/mol) solely by thermal annealing. By adding plasticizer molecules in the high molecular weight BCP (45.5k), we have not only avoided solvent vapor annealing but also reduced significantly the processing time. The properties of the guiding lines and the quality of the final BCP hard mask (CD uniformity, LWR, LER) were investigated.

This manuscript first presents a cost model to compare the cost of ownership of DSA and SAQP for a typical front end of line (FEoL) line patterning exercise. Then, we proceed to a feasibility study of using a vertical furnace to batch anneal the block co-polymer for DSA applications. We show that the defect performance of such a batch anneal process is comparable to the process of record anneal methods. This helps in increasing the cost benefit for DSA compared to the conventional multiple patterning approaches.

The methodology suggested in this research provides the great possibility of creating nanostructures composed of various materials, such as soft polymer, hard polymer, and metal, as well as Si. Such nanostructures are required for a vast range of optical and display devices, photonic components, physical devices, energy devices including electrodes of secondary batteries, fuel cells, solar cells, and energy harvesters, biological devices including biochips, biomimetic or biosimilar structured devices, and mechanical devices including micro- or nano-scale sensors and actuators.