3D additive fabrication for CMOS-compatible integration of scalable neural networks

Adria Grabulosa; Johnny Moughames; Xavier Porte; Daniel Brunner

doi:10.1117/12.2650043

17 March 2023 3D additive fabrication for CMOS-compatible integration of scalable neural networks

Adria Grabulosa, Johnny Moughames, Xavier Porte, Daniel Brunner

Proceedings Volume PC12433, Advanced Fabrication Technologies for Micro/Nano Optics and Photonics XVI; PC124330E (2023) https://doi.org/10.1117/12.2650043
Event: SPIE OPTO, 2023, San Francisco, California, United States

Abstract

The topology of neural networks fundamentally differs from classical computing concepts. They feature a colocation of memory and transformation of information, which makes them ill-suited for implementation in von Neumann architectures. In substrates pursuing in-memory computing, the connection topology of a neural network is encoded in the wiring of a chip, regardless of photonic or electronic, and this approach promises to revolutionize the efficiency of neural network computing. Equally general is that such in memory architectures cannot be implemented in 2D substrates, where their chip real-estate as well as energy consumption increase with an exponent larger unity with the number of neurons. I will discuss our recent work on using additive one and two photon polymerization in order to create 3D integrated photonic chips, that will allow to overcome this scaling bottleneck. Our process is CMOS compatible and hence maps a direct path to a technological implementation.

Conference Presentation

Citation Download Citation

Adria Grabulosa, Johnny Moughames, Xavier Porte, and Daniel Brunner "3D additive fabrication for CMOS-compatible integration of scalable neural networks", Proc. SPIE PC12433, Advanced Fabrication Technologies for Micro/Nano Optics and Photonics XVI, PC124330E (17 March 2023); https://doi.org/10.1117/12.2650043

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