This PDF file contains the editorial “How to Write a Good Scientific Paper: Structure and Organization” for JM3 Vol. 13 Issue 04

This PDF file contains the editorial “Special Section Guest Editorial: Holistic/Hybrid Metrology” for JM3 Vol. 13 Issue 04

A study performed to evaluate the benefits of combining techniques to improve the overall metrology of thin silicon germanium (SiGe) epitaxial layers doped with boron is presented. A specifically designed set of wafers was processed and measured by different in-line metrology tools and characterization techniques. This study describes the best strategy for combining metrology techniques in order to reliably determine dopant concentration and Ge composition measurement of the layers. It demonstrates that combined metrology enables key improvements in manufacturing and engineering environments.

Scatterometry-based critical dimension (CD), also known as optical CD (OCD), significantly matches CD scanning electron microscopy in accuracy and precision, in addition to offering superior full-profile reconstruction. OCD, however, is computationally intensive. We construct an extremely fast screening tool that determines whether a sample should or should not proceed to subsequent manufacturing steps. To this end, we examine the diffraction signals of the grating in order to determine whether a sample is in or out of its specification limits. This allows us to allocate traditional metrology resources only for samples that show unusual behavior. Support vector machines (SVMs) are trained to classify each incoming sample as in-spec or out-of-spec. The constructed classifier is applied to gratings exposed with a focus-exposure matrix for a rectangular silicon-bottom anti-reflective coating-photoresist stack, which include erroneous samples with under–over exposure, necking, and bridging problems. The misclassification rates as well as false and missed alarm rates are analyzed. Results show that our prototype screening system has misclassification errors on the order of 5% to 10%, while the computation time is on the order of one vector dot product.

One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.

For robustness improvement of inline metrology tools, we propose an inline reference metrology system, named verification metrology system (VMS). This system combines inline metrology and nondestructive reference metrology tools. VMS can detect the false alarm error and the nondetectable error caused by measurement robustness decay of inline metrology tools. Grazing-incidence small-angle x-ray scattering (GI-SAXS) was selected as the inline reference metrology tool. GI-SAXS has high robustness capability for under-layer structural changes. VMS with scatterometry and GI-SAXS was evaluated for measurement robustness. The potential to detect metrology system errors was confirmed using VMS. Cost reduction effect of VMS was estimated for the false alarm case. Total cost is obtained as a sum of the false alarm losses and the metrology costs. VMS is effective for total cost reduction with low sampling. Also, it is important that the sampling frequency of reference metrology is optimized based on process qualities.

Scatterometry performance enhancement is demonstrated through a holistic approach by utilizing comprehensive information from various sources, including data from different process steps, different toolsets, multiple structures, and multiple optical channels using samples from magnetic hard disk drive manufacturing. Parameter and spectrum feed-forward are performed across multiple targets at the photo step and the photo results are fed forward to the post-reactive ion etch (RIE) step. For an isolated structure with critical dimensions (CD) much smaller than the incident light wavelengths, feed-forward methods improve CD correlation with a general improvement of 20 to 60% in precision and fleet measurement precision (FMP). A second technique examined is hybrid metrology, where inputs from source tools, such as CD-SEM and CD-AFM, are used to determine critical parameters. Hybridization of line edge roughness results in CD and sidewall angle (SWA) FMP improvement of ∼60%. We also demonstrate improved CD accuracy using azimuthal scatterometry at 0, 45, and 90 deg azimuth angles measuring resist lines with CD larger than the incident light wavelengths. FMP reductions of ∼60 and 30% are obtained for CD and SWA. SWA hybridization after RIE results in CD and SWA FMP improvements by > 50 and 30%, respectively.

At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R² equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R² being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.

We have used synchrotron-based critical dimension small-angle x-ray scattering (CD-SAXS) to monitor the impact of hydrogen annealing on the structural characteristics of silicon FinFET structures fabricated using self-aligned double patterning on both bulk silicon and silicon-on-insulator (SOI) substrates. H₂ annealing under different conditions of temperature and gas pressure allowed us to vary the sidewall roughness and observe the response in the two metrology approaches. In the case of the simpler bulk Si FinFET structures, the CD-SAXS measurements of the critical dimensions are in substantive agreement with the top–down critical dimension scanning electron microscopy metrology. Corresponding characterizations on SOI-based FinFET structures showed less agreement, which is attributed to the more complex structural model required for SOI FinFET CD-SAXS modeling. Because sidewall roughness is an important factor in the performance characteristics of Si FinFETs, we have compared the results of roughness measurements using both critical dimension atomic force microscopy (CD-AFM) and CD-SAXS. The measurements yield similar estimates of sidewall roughness, although the CD-AFM values were typically larger than those generated by CD-SAXS. The reasons for these differences will be discussed.

As semiconductor processing becomes more complicated and pattern sizes shrink, the overlay metrology has become one of the most important issues in the semiconductor industry. Therefore, in order to obtain correct, reliable overlay values in semiconductor fabrication facilities (fab), quantization methods for the efficient management and implementation of a measurement algorithm are required, as well as an understanding of the target structures in the semiconductor device. We implemented correct, reliable overlay values in the pattern using the image processing method. The quantization method, through correlation analysis and a new algorithm for target structures, were able to improve the sensitivity to misalignment in the pattern and enable more stable and credible in-line measurement by decreasing the distribution of the residuals in overlay values. Since overlay values of the pattern in the fab were measured and managed more reliably and quickly, it is expected that our study will be able to contribute to the yield enhancement of semiconductor companies.

The accelerated pace of the semiconductor industry in recent years is putting a strain on existing dimensional metrology equipment (such as critical dimension-secondary electron microscopy, atomic force microscopy, scatterometry) to keep up with ever-increasing metrology challenges. However, a revolution appears to be forming with the recent advent of hybrid metrology (HM). We highlight some of the challenges and lessons learned when setting up a standard HM solution and describe the first-in-industry implementation of HM within a high-volume manufacturing environment.

Integrated circuits from 22-nm node and beyond utilize many innovative techniques to achieve features that are well beyond the resolution limit of 193-nm immersion lithography. The introduction of complex three-dimensional structures in device design presents additional challenges that require more sophisticated metrology with high accuracy and precision. One such example is pitch walking induced by multiple-patterning techniques. Quantification of pitch walking has traditionally been a challenge. We present two ways of detecting pitch walking using optical and x-ray techniques. In scatterometry, this work investigates the feasibility of nonorthogonal azimuth angle spectroscopic reflectometry setups for fin pitch walking measurements, which is useful for in-line monitoring in 14-nm node microelectronics manufacturing. Simulations show a significant improvement in pitch walking sensitivity using 45-deg azimuth scan. Other relevant considerations for pitch walking modeling in scatterometry, such as parameter correlations, are also discussed. Another approach is using high-resolution x-ray diffraction (HRXRD) to measure the diffraction peaks from crystalline fins. The onset of pitch walking is determined by the appearance of a shifted subset of peaks in the diffraction spectrum. Information about the fin profiles, e.g., sidewall angle, critical dimension, height, and pitch walking, can be obtained from the resultant diffraction pattern. Note that in HRXRD measurements, each critical parameter is a unique element in the Reciprocal Space Map (RSM) and no correlations between parameters exist. We will discuss the results from measurements using the two techniques and how the combination of the two techniques can give complete information about the fins needed for in-line monitoring.

The performance of overlay metrology as total measurement uncertainty, design rule compatibility, device correlation, and measurement accuracy has been challenged at the 2× nm node and below. The process impact on overlay metrology is becoming critical, and techniques to improve measurement accuracy become increasingly important. We present a methodology for improving the overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with the least process impacts and reliable accuracies. Using the quality metric, a calibration method, Archer self-calibration, is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as critical dimension–scanning electron microscopy data collected on a device correlated metrology hybrid target or by electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. We provide an example of such a case.

Work using the concept of a co-optimization-based metrology hybridization is presented. Hybrid co-optimization involves the combination of data from two or more metrology tools such that the output of each tool is improved by the output of the other tool. Here, the image analysis parameters from a critical dimension scanning electron microscope (CD-SEM) are modulated by the profile information from optical critical dimension (OCD, or scatterometry), while the OCD-extracted profile is concurrently optimized through addition of the CD-SEM CD results. The test vehicle utilized is the 14-nm technology node-based FinFET high-k/interfacial layer (HK/IL) structure. When compared with the nonhybrid approach, the correlation to reference measurements of the HK layer thickness measurement using hybrid co-optimization resulted in an improvement in relative accuracy of about 40% and in R² from 0.81 to 0.91. The measurement of the IL thickness also shows an improvement with hybrid co-optimization: better matching to the expected conditions as well as data that contain less noise.

Until now, metrologists had no statistics-based method to determine the sampling needed for an experiment before the start that accuracy experiment. We show a solution to this problem called inverse total measurement uncertainty (TMU) analysis, by presenting statistically based equations that allow the user to estimate the needed sampling after providing appropriate inputs, allowing him to make important “risk versus reward” sampling, cost, and equipment decisions. Application examples using experimental data from scatterometry and critical dimension scanning electron microscope tools are used first to demonstrate how the inverse TMU analysis methodology can be used to make intelligent sampling decisions and then to reveal why low sampling can lead to unstable and misleading results. One model is developed that can help experimenters minimize sampling costs. A second cost model reveals the inadequacy of some current sampling practices—and the enormous costs associated with sampling that provides reasonable levels of certainty in the result. We introduce the strategies on how to manage and mitigate these costs and begin the discussion on how fabs are able to manufacture devices using minimal reference sampling when qualifying metrology steps. Finally, the relationship between inverse TMU analysis and hybrid metrology is explored.

Integrated circuit (IC) technology is changing in multiple ways: 193i to extreme ultraviolet exposure, planar to nonplanar device architecture, from single exposure lithography to multiple exposure and directed self-assembly (DSA) patterning, and so on. Critical dimension (CD) control requirement is becoming stringent and more exhaustive: CD and process windows are shrinking, three-sigma CD control of <2  nm is required in complex geometries, and a metrology uncertainty of <0.2  nm is required to achieve the target CD control for advanced IC nodes (e.g., 14, 10, and 7 nm nodes). There are fundamental capability and accuracy limits in all the metrology techniques that are detrimental to the success of advanced IC nodes. Reference or physical CD metrology is provided by atomic force microscopy (CD-AFM) and TEM while workhorse metrology is provided by CD-SEM, scatterometry, and model-based infrared reflectrometry (MBIR). Precision alone is not sufficient for moving forward. No single technique is sufficient to ensure the required accuracy of patterning. The accuracy of CD-AFM is ∼1  nm and the precision in TEM is poor due to limited statistics. CD scanning electron microscopy (CD-SEM), scatterometry, and MBIR need to be calibrated by reference measurements for ensuring the accuracy of patterned CDs and patterning models. There is a dire need for a measurement with <0.5  nm accuracy and the industry currently does not have that capability with inline measurements. Being aware of the capability gaps for various metrology techniques, we have employed data processing techniques and predictive data analytics, along with patterning simulation and metrology models and data integration techniques to selected applications demonstrating the potential solution and practicality of such an approach to enhance CD metrology accuracy. Data from multiple metrology techniques have been analyzed in multiple ways to extract information with associated uncertainties and integrated to extract the useful and more accurate CD and profile information of the structures. This paper presents the optimization of scatterometry and MBIR model calibration and the feasibility to extrapolate not only in design and process space but also from one process step to a previous process step. A well-calibrated scatterometry model or patterning simulation model can be used to accurately extrapolate and interpolate in the design and process space for lithography patterning where AFM is not capable of accurately measuring sub-40 nm trenches. The uncertainty associated with extrapolation can be large and needs to be minimized. We have made use of measurements from CD-SEM and CD-AFM, along with the patterning and scatterometry simulation models to estimate the uncertainty associated with extrapolation and the methods to reduce it. For the first time, we have reported the application of machine learning (artificial neural networks) to the resist shrinkage systematic phenomenon to accurately predict the preshrink CD based on supervised learning using the CD-AFM data. The study lays out various basic concepts, approaches, and protocols of multiple source data processing and integration for a hybrid metrology approach. Impacts of this study include more accurate metrology, patterning models, and better process controls for advanced IC nodes.

Source mask optimization (SMO) is one of the required techniques for lithography below 32 nm. Source representation is one important factor that affects both the imaging simulation and optimization processes of SMO, especially the global SMOs such as the SMO using genetic algorithm (GA-SMO). We propose a source representation which accelerates the GA-SMO. The proposed representation uses a group of circular poles to describe the freeform illumination source whose pupil filling ratio (PFR) is small. Compared with conventional Cartesian-grid and polar-grid pixelated representations, the proposed multipole source representation can represent the low-PFR freeform illumination source with fewer variables, which speeds up both the GA convergence and lithography imaging simulation. Numerical experiments show that the GA-SMO using the proposed multipole source representation method is about seven times faster than that using polar-grid pixelated source representation on the premise that other simulation conditions are the same and optimization qualities are comparable.

Although extreme ultraviolet (EUV) lithography is being considered as one of the most promising next-generation lithography techniques for patterning sub-20 nm features, the development of suitable EUV resists remains one of the main challenges confronting the semiconductor industry. The goal is to achieve sub-20 nm line patterns having low line edge roughness (LER) of <1.8  nm and a sensitivity of 5 to 20  mJ/cm². The present work demonstrates the lithographic performance of two nonchemically amplified (n-CARs) negative photoresists, MAPDST homopolymer and MAPDST-MMA copolymer, prepared from suitable monomers containing the radiation sensitive sulfonium functionality. Investigations into the effect of several process parameters are reported. These include spinning conditions to obtain film thicknesses <50  nm, baking regimes, exposure conditions, and the resulting surface topographies. The effect of these protocols on sensitivity, contrast, and resolution has been assessed for the optimization of 20 nm features and the corresponding LER/line width roughness. These n-CARs have also been found to possess high etch resistance. The etch durability of MAPDST homopolymer and MAPDST-MMA copolymer (under SF₆ plasma chemistry) with respect to the silicon substrate are 7.2∶1 and 8.3∶1, respectively. This methodical investigation will provide guidance in designing new resist materials with improved efficiency for EUVL through polymer microstructure engineering.

We report on our development strategy of photo-curable resists for nanoimprint lithography (NIL) based on modularity. Starting with a basic formulation, we address two topics: the integration of fluorinated additives and the enhancement of the dry etching stability. We prove both concepts by the introduction of two different resists derived from the same basic formulation. The viscosity of the novel resist materials was optimized for inkjet dispensing at room temperature (RT). The novel resist materials can be applied either in NIL batch processes or in high-throughput roller processes. Batch-wise imprints were performed on various substrates such as Si or plastics, demonstrating the distinctive application versatility of the novel materials. Dry etching of spin-coated thin films on Si wafers was performed, demonstrating an etch stability versus Si of 3.5:1 by using the resist formulation with improved etching stability. Roll-to-roll NIL at high throughput on large areas was performed with web speeds of up to 30  m min⁻¹ with different stamp materials. We conclude that all resists reported herein can be deposited via inkjet dispensing at RT, are suitable for continuous high-throughput imprinting on flexible substrates, and are applicable in step-wise NIL processes with good etch resistance in dry etch processes.

This paper reports the development of a low-cost, portable, light-emitting diode (LED)-based ultraviolet (UV) exposure system. The major system components include UV-LEDs, a microcontroller, a digital-to-analog converter, and LED control circuitry. Through its front panel with a liquid crystal display and keypad, the UV-LED lithography system is able to receive user-defined values for exposure time and power, which allows the exposure dose to be tunable on demand. Compared to standard mask aligners, the UV-LED lithography system is a fraction of the cost, is simpler to construct using off-the shelf components, and does not require a complex infrastructure to operate. Such a reduction in system cost and complexity renders UV-LED lithography a perfect candidate for microlithography with large process windows typically suitable for MEMS, microfluidics applications.

Defect avoidance methods are likely to play a key role in overcoming the challenge of mask blank defectivity in extreme ultraviolet (EUV) lithography. In this work, we propose an innovative EUV mask defect avoidance method. It is the first approach that allows exploring all the degrees of freedom available for defect avoidance (pattern shift, rotation and mask floorplanning). We model the defect avoidance problem as a global, nonconvex optimization problem and then solve it using a combination of random walk and gradient descent. For a 8-nm polysilicon layer of an ARM Cortex M0 layout, our method achieves a 60% point better mask yield compared to prior art in defect avoidance for a 40-defect mask. We show that pattern shift is the most significant degree of freedom for improving mask yield. Rotation and mask floorplanning can also help improve mask yield to a certain extent.

The introduction of extreme ultraviolet (EUV) lithography into manufacturing requires changes in all aspects of the infrastructure, including the photomask. EUV reflective masks consist of a sophisticated multilayer (ML) mirror, capping layer, absorber layer, and anti-reflective coating thereby dramatically increasing the complexity of the photomask. In addition to absorber type defects similar to those the industry was forced to contend with for deep ultraviolet lithography, the complexity of the mask leads to new classes of ML defects. Furthermore, these approaches are complicated not only by the mask itself but also by unique aspects associated with the exposure of the photomask by the EUV scanner. This paper focuses on the challenges for handling defects associated with inspection, review, and repair for EUV photomasks. Blank inspection and pattern shifting, two completely new steps within the mask manufacturing process that arise from these considerations, and their relationship to mask review and repair are discussed. The impact of shadowing effects on absorber defect repair height is taken into account. The effect of mask biasing and the chief ray angle rotation due to the scanner slit arc shape will be discussed along with the implications of obtaining die-to-die references for inspection and repair. The success criteria for compensational repair of ML defects will be reviewed.

Optical proximity correction (OPC) is a resolution enhancement technique extensively used in the semiconductor industry to improve the resolution and pattern fidelity of optical lithography. In pixel-based OPC (PBOPC), the layout is divided into small pixels, which are then iteratively modified until the simulated print image on the wafer matches the desired pattern. However, the increasing complexity and size of modern integrated circuits make PBOPC techniques quite computationally intensive. This paper focuses on developing a practical and efficient PBOPC algorithm based on a nonparametric kernel regression, a well-known technique in machine learning. Specifically, we estimate the OPC patterns based on the geometric characteristics of the original layout corresponding to the same region and a series of training examples. Experimental results on metal layers show that our proposed approach significantly improves the speed of a current professional PBOPC software by a factor of 2 to 3, and may further reduce the mask complexity.

An optical fiber strain sensor based on sandwiched long-period fiber gratings (OFSS-SLPFG) with a surface bonding layer is proposed. The proposed OFSS-SLPFG is an etched optical fiber that is sandwiched between two thick photoresists with a periodic structure. To prevent the glue effect in the surface bonding process, where glue flows into the SLPFG structure, reducing the coupling strength, a surface bonding layer (thickness: 16  μm) is used as the base layer on the bottom of the OFSS-SLPFG. The OFSS-SLPFG is, therefore, more effective for use as a strain sensor. When external strain loading is applied, the resonant dip loss of the OFSS-SLPFG is reflected linearly. A bending strain calibration experiment is demonstrated by the four-point bending test. The results show an average linearity (R²) of 0.980, with a sensitivity of 0.00788  dB/με. This phenomenon suggests that the OFSS-SLPFG can be utilized as a sensitive strain transducer.

This paper proposes a low-cost SU-8 pressure sensor fabricated using a piezoresistive material, SU-8/silver composite (SU-8/Ag), and a substrate material, overhead projector (OHP) transparency. SU-8/Ag has higher gauge factor (26.3) but shows a lower stiffness (2 GPa) compared with doped silicon. The OHP transparency substrate is cheap, easily forms the desired shape, is transparent to light (allows backside exposure), and allows for the dry release method through OHP transparency. Fabrication and characterization in this study were carried out using a typical semiconductor lab setup. The fabricated sensor showed high sensitivity (21.5  μV/Pa), low linearity error (Pearson’s correlation coefficient=0.994937), and no apparent hysteresis response. The fabricated sensor with SU-8/Ag as the piezoresistive material exhibited 41 times higher sensitivity compared to that found in a previous study based on SU-8 and doped polysilicon.

As critical dimensions decrease for 32-nm node and beyond, the resist loss increases and resist patterns become more vulnerable to etching failures. Traditional optical proximity correction (OPC) models only consider two-dimensional (XY) contours and neglect height (Z) variations. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip. However, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. We show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration. The model can then be used to identify toploss hotspots on a full chip and, in some cases, for correction of these patterns. In addition, the article will show how the model can be made more accurate by accounting for some 3-D effects like diffusion through height.

We present fabrication, characterization, and experimental results describing electrical actuation and readout of the mechanical vibratory response of electrospun ZnO nanofibers. For a fiber with an approximate radius of 200 nm and a length of 70  μm, a resonance frequency around 3.62 MHz with a quality factor (Q) of about 235 in air at ambient conditions is observed. It is shown that the measured frequency of the resonance is consistent with results from finite element simulations. Also, the measurements were performed in an enclosed chamber with controlled levels of ethanol vapor. The adsorption of ethanol causes a shift in the resonance frequency of the fibers, which can be related to the concentration of ethanol vapor for sensing purposes.

This report shows different fabrication procedures followed to obtain piezoelectric microcantilevers. The proposed microcantilever is a sandwich structure composed of chromium (Cr) electrodes (from 50 to 300-nm thick) and a reactive sputtered piezoelectric aluminum nitride (AlN) thin film (from 350 nm to 600-nm thick). The microcantilevers top-view dimensions ranged from 50 to 300  μm in width and from to 250 to 700  μm in length. Several materials such as nickel silicide and nickel, as well as a photoresist, and finally the silicon substrate surface have been investigated to discern their possibilities and limitations when used as sacrificial layers. These materials have been studied to determine the optimal processing steps and chemistries required for each of them. The easiest and the only successful microcantilevers release was finally obtained using the top silicon substrate surface as a sacrificial layer. The structural and morphological characteristics of the microcantilevers are presented as well as their piezoelectric character. The main difference of this work resides in the Si surface-based microcantilever release technique. This, along with the synthesis of AlN at room temperature by reactive sputtering, establishes a manufacturing procedure for piezoelectric microbeams, which makes possible the integration of such MEMS devices into postCMOS technology.

Source mask optimization (SMO) is a leading resolution enhancement technique in immersion lithography at the 45-nm node and beyond. Current SMO approaches, however, fix the numerical aperture (NA), which has a strong impact on the depth of focus (DOF). A higher NA could realize a higher resolution but reduce the DOF; it is very important to balance the requirements of NA between resolution and the DOF. In addition, current SMO methods usually result in complicated source and mask patterns that are expensive or difficult to fabricate. This paper proposes a parametric source-mask-NA co-optimization (SMNO) method to improve the pattern fidelity, extend the DOF, and reduce the complexity of the source and mask. An analytic cost function is first composed based on an integrative vector imaging model, in which a differentiable function is applied to formulate the source and mask patterns. Then, the derivative of the cost function is deduced and a gradient-based algorithm is used to solve the SMNO problem. Simulation results show that the proposed SMNO can achieve the optimum combination of parametric source, mask, and NA to maintain high pattern fidelity within a large DOF. In addition, the complexities of the source and mask are effectively reduced after optimization.

We have demonstrated a fiber-based template process for fabricating site-specific and highly aligned platinum (Pt) microwires (MWs) with a polymeric core utilizing near-filed electrospinning (NFES) and soft transferring technology. Eliminating the indispensably expensive submicron lithographic and metal catalyst/lift-off as well as the extensive etching processes, the proposed method is direct-write, lithography-free, and low cost. As a demonstration, Pt sputtering deposition on top of a 500-μm length of microfibers for 5/10/15  min is sufficient to produce highly conductible Pt MWs with a sheet resistance measured to be 1.46/1.09/0.83  kΩ/sq, with good adhesion between the sputtered MWs and the underlying layers. The measured total resistances were found to increase almost linearly with the length of the MWs and are comparatively more conductive than polypyrrole films. Furthermore, the reliable and repeatable nanofiber arrays can be speedily fabricated, while various patterns and dimensions are predominantly controllable by NFES in a direct-write, addressable manner.

The inspection sensitivity of a patterned extreme ultraviolet mask with B₄C-capped multilayer (ML) was investigated using a simulated projection electron microscope (PEM) image. Extrusion and intrusion defects with 16-nm size were detected with their intensity of >10 times the standard deviation of the background level on a half-pitch 64-nm line-and-space pattern. The defect detection sensitivity in this case was higher than that of a Ru-capped ML sample and has a potential to meet the requirement for beyond 16-nm node generation from the standpoint of patterned mask inspection using the PEM technique. These results indicate that the B₄C capping layer, besides its good durability, has an advantage for high sensitivity of patterned mask inspection. The optimal condition of the incident beam energy was found to be 500 and 1,000 eV for the samples of B₄C-capped ML and B₄C-buffered Ru-capped ML, respectively. The sensitivity of defect detection was strongly affected by the difference of secondary electron emission coefficients (SEECs) between the absorber layer and capping layer. However, the small incident beam energy was found to be preferable when the SEEC difference was relatively high.

A digital micromirror device (DMD) acts as a spatial light modulator in a maskless photolithography system. Illuminated by coherent light, DMD performs as a two-dimensional diffraction grating because of its periodical internal structure. Diffraction efficiency is an important factor for evaluating the exposure doses. A diffraction model of DMD based on Fourier analysis demonstrates that errors of the DMD’s manufacture and the precision of the machining of the optical mechanical structure affect the diffraction efficiency. Additionally, analysis of exposure results by the diffraction model of DMD in Tracepro explains the degradation of the exposure quality and is helpful for calibrating the direction of optical focusing.

The acid-catalyzed deprotection of glassy poly(4-hydroxystyrene-co-tertbutyl acrylate) films was studied with infrared absorbance spectroscopy and stochastic simulations. Experimental data were interpreted with a simple description of subdiffusive acid transport coupled to second-order acid loss. This model predicts key attributes of observed deprotection rates, such as fast reaction at short times, slow reaction at long times, and a nonlinear dependence on acid loading. Fickian diffusion is approached by increasing the postexposure bake temperature or adding plasticizing agents to the polymer resin. These findings demonstrate that acid mobility and overall deprotection kinetics are coupled to glassy matrix dynamics. To complement the analysis of bulk kinetics, acid diffusion lengths were calculated from the anomalous transport model and compared with nanopattern line widths. The consistent scaling between experiments and simulations suggests that the anomalous diffusion model could be further developed into a predictive lithography tool.

With the use of subwavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden. These are the ones with a high yield impact or low routability impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the postroute stage in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability impact. Hence, an evaluation method is required early in the process to assess the impact of forbidding layout patterns on routability. We propose pattern-driven design rule evaluation (pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies [e.g., litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned octuple patterning (SAOP)]. Given a set of design rules and a set of forbidden patterns, pattern-DRE generates a set of virtual standard cells; then it finds the possible routing options for each cell without using any of the forbidden patterns. Finally, it reports the routability metrics. We present a few studies that illustrate the use cases of the framework. The first study compares LELE to SADP by using a set of forbidden patterns that are allowed by LELE but not by SADP. Another study compares LELE to extreme ultraviolet lithography from the routability aspect by prohibiting patterns that have LELE native conflicts. In addition, we present a study that investigates the effect of placing the active area of the transistors close to the P/N interface instead of close to the power rails.

This work reports on mechanical tests and irradiations made on silicon bulk-acoustic wave resonators. The resonators were based on a tuning fork geometry and actuated by a piezoelectric aluminum nitride layer. They had a resonance frequency of 150 kHz and a quality factor of about 20,000 under vacuum. The susceptibility of the devices to radiation-induced degradation was investigated using ⁶⁰Co γ-rays and 50 MeV protons with space-relevant doses of up to 170 krad. The performance of the devices after irradiation indicated a high tolerance to both ionizing damage and displacement damage effects. In addition, the device characteristics were evaluated after mechanical shock and vibration tests and only small effects on the devices were observed. In all experiments, no significant changes of the resonance characteristics were observed within the experimental uncertainty, which was below 100 ppm for the resonance frequency. The results support the efforts toward design and fabrication of highly reliable MEMS devices for space applications.

In plasmonic lithography, when using a scanning probe in contact mode, degradation of the line pattern quality occasionally occurs due to variations of probe tip velocity or a stick/slip motion. To avoid poor pattern quality caused by such variations in probe tip motion, we analyzed the motion of the probe tip by using a frictional model based on conventional contact mechanics. The motion of the probe tip was numerically analyzed in terms of adhesion force and probe velocity, which are the dominant factors in micro/nanoscale motion. It was found that stick/slip spacing has a roughly positive relationship with the maximum adhesion force between the substrate and probe tip, and a negative relationship with the probe velocity. Combining the probe tip motion with the exposure model of a near-field wave, we analyzed the quality of line patterns that resulted from various stick/slip spacing in terms of line-edge roughness.