3 September 2015 Hardware architecture for full analytical Fraunhofer computer-generated holograms
Zhi-Yong Pang, Zong-Xi Xu, Yi Xiong, Biao Chen, Hui-Min Dai, Shao-Ji Jiang, Jian-Wen Dong
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Abstract
Hardware architecture of parallel computation is proposed for generating Fraunhofer computer-generated holograms (CGHs). A pipeline-based integrated circuit architecture is realized by employing the modified Fraunhofer analytical formulism, which is large scale and enables all components to be concurrently operated. The architecture of the CGH contains five modules to calculate initial parameters of amplitude, amplitude compensation, phases, and phase compensation, respectively. The precalculator of amplitude is fully adopted considering the “reusable design” concept. Each complex operation type (such as square arithmetic) is reused only once by means of a multichannel selector. The implemented hardware calculates an 800×600  pixels hologram in parallel using 39,319 logic elements, 21,074 registers, and 12,651 memory bits in an Altera field-programmable gate array environment with stable operation at 50 MHz. Experimental results demonstrate that the quality of the images reconstructed from the hardware-generated hologram can be comparable to that of a software implementation. Moreover, the calculation speed is approximately 100 times faster than that of a personal computer with an Intel i5-3230M 2.6 GHz CPU for a triangular object.
© 2015 Society of Photo-Optical Instrumentation Engineers (SPIE) 0091-3286/2015/$25.00 © 2015 SPIE
Zhi-Yong Pang, Zong-Xi Xu, Yi Xiong, Biao Chen, Hui-Min Dai, Shao-Ji Jiang, and Jian-Wen Dong "Hardware architecture for full analytical Fraunhofer computer-generated holograms," Optical Engineering 54(9), 095101 (3 September 2015). https://doi.org/10.1117/1.OE.54.9.095101
Published: 3 September 2015
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Cited by 8 scholarly publications.
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KEYWORDS
Computer generated holography

Computer architecture

Field programmable gate arrays

Holograms

Diffraction

Amplifiers

Fourier transforms

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