This paper aims at developing a novel defect detection algorithm for the semiconductor assembly process by image analysis of a single captured image, without reference to another image during inspection. The integrated circuit (IC) pattern is usually periodic and regular. Therefore, we can implement a classification scheme whereby the regular pattern in the die image is classified as the acceptable circuit pattern and the die defect can be modeled as irregularity on the image. The detection of irregularity in image is thus equivalent to the detection of die defect. We propose a method where the defect detection algorithm first segments the die image into different
regions according to the circuit pattern by a set of morphological segmentations with different structuring element sizes. Then, a feature vector, which consists of many image attributes, is calculated for each segmented region. Lastly, the defective region is extracted by the feature vector classification.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.