With each new process technology node chip designs increase in complexity and size, and mask data prep flows require
more compute resources to maintain the desired turn around time (TAT). In addition, to maintaining TAT, mask data
prep centers are trying to lower costs. Securing highly scalable processing for each element of the flow - geometry
processing, resolution enhancements and optical process correction, verification and fracture - has been the focal point
so far towards the goal of lowering TAT. Processing utilization for different flow elements is dependent on the
operation, the data hierarchy and device type. In this paper we pursue the introduction of a dynamic utilization driven
compute resource control system applied to large scale parallel computation environment. The paper will explain the
performance challenges in optimizing a mask data prep flow for TAT and cost while designing a compute resource
system and its framework. In addition, the paper will analyze performance metrics TAT and throughput of a production
system and discuss trade-offs of different parallelization approaches in data processing in interaction with dynamic
resource control. The study focuses on 65nm and 45nm process node.
With each new process technology node chip designs increase in complexity and size, and mask data prep flows require
more compute resources to maintain the desired turn around time (TAT) at a low cost. Securing highly scalable
processing for each element of the flow - geometry processing, resolution enhancements and optical process correction,
verification and fracture - has been the focal point so far. The utilization for different flow elements depends on the
operation, the data hierarchy and the device type. This paper introduces a dynamic utilization driven compute resource
control system applied to large scale parallel computation environment. The paper will analyze performance metrics
TAT and throughput for a production system and discuss trade-offs of different parallelization approaches in data
processing regarding interaction with dynamic resource control. The study focuses on 65nm and 45nm designs.
In this work, test-patterns, test-cases and layout-patterns generations are widely investigated in the sense of turnaround
time for creation and/or modification. STPRL, a novel behavioral modeling language for test-pattern creation, is
being proposed. The turn-around time for both creation and modification is hugely reduced at no degradation in either
accuracy or performance. Furthermore, STPRL provides considerable performance improvements in custom test-patterns
creation over available automatic layout creation tools. Our method has been verified with real data at different
node-technologies and for migration from and between different technology nodes.
In this work, test-patterns, test-cases and layout-patterns generations are widely investigated in the sense of turnaround
time for creation and/or modification. STPRL, a novel behavioral modeling language for test-pattern creation, is
being proposed. The turn-around time for both creation and modification is hugely reduced at no degradation in either
accuracy or performance. Furthermore, STPRL provides considerable performance improvements in custom testpatterns
creation over available automatic layout creation tools. Our method has been verified with real data at different
node-technologies and for migration from and between different technology nodes.
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