Shift happens due to electron beam tilt in scanning electron microscopy. To measure this aberration effect with submilliradian uncertainty, and to calibrate scale factor and correct scanfield distortion, we introduce conical frustum arrays as multifunctional reference structures. Our concept shows promise for new accuracy in scanning electron microscopy.
KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL), targeted as a production worthy multiple electron beam tool for next generation high volume lithography. The Digital Pattern Generator (DPG) integrated with CMOS and MEMS lenslets is a critical part of REBL. Previously, KLA-Tencor reported on progress towards a REBL tool for maskless lithography below the 10 nm technology node. However, the MEMS lenslet structure suffered from charging up during writing, requiring the usage of a charge drain coating. Since then, the TSMC multiple e-beam team and the KLA-Tencor REBL team have worked together to further develop the DPG for direct write lithography. In this paper, we introduce a hollow-structure MEMS lenslet array that inherently prevents charging during writing, and preliminary verification results are also presented.
The digital pattern generator (DPG) is a complex electron-optical MEMS that pixelates the electron beam in the reflective electron beam lithography (REBL) e-beam column. It potentially enables massively parallel printing, which could make REBL competitive with optical lithography. The development of the REBL DPG, from the CMOS architecture, through the lenslet modeling and design, to the fabrication of the MEMS device, is described in detail. The imaging and printing results are also shown, which validate the pentode lenslet concept and the fabrication process.
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half
pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL)
technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing
system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL
system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable
of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons
are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The
DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed.
Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below
the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the
REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled
DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of
over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron
beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern
scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in
both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying
the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design
improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current
chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be
presented.
KEYWORDS: Electron beam lithography, Monte Carlo methods, Lithography, Line width roughness, Photomasks, Electron beams, Logic, Photoresist processing, Nanoimprint lithography, Semiconductor manufacturing
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm
logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam
Lithography (REBL) technology targeting high-volume 10 nm logic performance.
There are several potential applications for E-Beam Direct Write Lithography in high volume
manufacturing (HVM) Lithography. They range from writing full critical layers to the use as complementary
lithography in order to write cut masks for multiple patterning optical lithography. Two of the potential applications
for REBL with specific requirements on the writing strategy are contact layer and cut mask lithography. For these
two applications the number of electrons writing a single feature can be a concern if the resist sensitivity is high and
the process latitude is small. This paper will share calculations with respect to the needed and expected shot noise,
dose and focus latitude performance of a proposed REBL lithography system. The simulated results will be
compared to data taken on test structures. Predicted performance based on the simulations and test results of a
potential REBL system for contact layers and cut mask applications will be discussed.
Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam
direct write lithography has been used for mask writing rather than wafer processing since the maximum blur
requirements limit column beam current - which drives e-beam throughput. To print small features and a fine
pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total
number of beams on a single writing tool. Because of the uncertainty with regards to the optical lithography
roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of
designing and testing e-beam lithography tools with the potential for high volume wafer processing. For this
work, we report on the development and current status of a new maskless, direct write e-beam lithography
tool which has the potential for high volume lithography at and below the 22 nm technology node.
A Reflective Electron Beam Lithography (REBL) tool is being developed for high throughput electron beam
direct write maskless lithography. The system is targeting critical patterning steps at the 22 nm node and
beyond at a capital cost equivalent to conventional lithography. Reflective Electron Beam Lithography
incorporates a number of novel technologies to generate and expose lithographic patterns with a throughput
and footprint comparable to current 193 nm immersion lithography systems. A patented, reflective electron
optic or Digital Pattern Generator (DPG) enables the unique approach. The Digital Pattern Generator is a
CMOS ASIC chip with an array of small, independently controllable lens elements (lenslets), which act as an
array of electron mirrors. In this way, the REBL system is capable of generating the pattern to be written
using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage
concept using a rotating platen carrying multiple wafers optimizes the writing strategy of the DPG to achieve
the capability of high throughput for sparse pattern wafer levels. The lens elements on the DPG are fabricated
at IMEC (Leuven, Belgium) under IMEC's CMORE program. The CMOS fabricated DPG contains ~
1,000,000 lens elements, allowing for 1,000,000 individually controllable beamlets. A single lens element
consists of 5 electrodes, each of which can be set at controlled voltage levels to either absorb or reflect the
electron beam. A system using a linear movable stage and the DPG integrated into the electron optics module
was used to expose patterns on device representative wafers. Results of these exposure tests are discussed.
REBL (Reflective Electron Beam Lithography) is a program for the development of a novel approach for highthroughput
maskless lithography. The program at KLA-Tencor is funded under the DARPA Maskless Nanowriter
Program. A DPG (digital pattern generator) chip containing over 1 million reflective pixels that can be individually
turned on or off is used to project an electron beam pattern onto the wafer. The DARPA program is targeting 5 to 7
wafers per hour at the 45 nm node, and this paper will describe improvements to both increase the throughput as
well as extend the system to the 2x nm node and beyond.
This paper focuses on three specific areas of REBL technology. First, a new column design has been developed
based on a Wien filter to separate the illumination and projection beams. The new column design is much smaller,
and has better performance both in resolution and throughput than the first column which used a magnetic prism for
separation. This new column design is the first step leading to a multiple column system. Second, the rotary stage
latest results of a fully integrated DPG CMOS chip with lenslets will be reviewed. An array of over 1 million micro
lenses which is fabricated on top of the CMOS DPG chip has been developed. The microlens array eliminates
crosstalk between adjacent pixels, maximizes contrast between on and off states, and provides matching of the NA
between the DPG reflector and the projection optics.
REBL (Reflective Electron Beam Lithography) is being developed for high throughput electron beam direct write
maskless lithography. The system is specifically targeting 5 to 7 wafer levels per hour throughput on average at the
45 nm node, with extendibility to the 32 nm node and beyond. REBL incorporates a number of novel technologies
to generate and expose lithographic patterns at estimated throughputs considerably higher than electron beam
lithography has been able to achieve as yet. A patented reflective electron optic concept enables the unique
approach utilized for the Digital Pattern Generator (DPG). The DPG is a CMOS ASIC chip with an array of small,
independently controllable cells or pixels, which act as an array of electron mirrors. In this way, the system is
capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely
high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the
writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The
exposure method utilized by the DPG was emulated on a Vistec VB-6 in order to validate the gray level exposure
method used in REBL. Results of these exposure tests are discussed.
A hydrogen silisesquioxane (HSQ) bilayer process and a top surface imaging (TSI) process are investigated for application as low-voltage electron beam resist systems. Namatsu, van Delft, and others have reported printing exceptionally small features using high-voltage electron beam exposure of HSQ at high-exposure doses (~2000 µC/cm2 at 100 kV). The shallow penetration depth of low-voltage electrons results in greatly reduced dose requirements, and smooth, high-resolution images are generated at 1 kV with an exposure dose of less than 60 µC/cm2. HSQ's high silicon content enable it to be used in a bilayer form utilizing reactive ion etching with an oxygen plasma, thus generating high aspect ratio images. TSI has been studied in the past by numerous researchers at low voltages using various TSI schemes. We investigate the use of a chemically amplified TSI resist process based on poly (t-BOC-hydroxystyrene). The effect of base quencher loading in the resist formulation on line edge roughness and resolution is investigated, and is found to have a dramatic influence. High-resolution, high aspect ratio images are printed down to 40 nm, and exhibit only moderate levels of line edge roughness. Furthermore, proximity effects at 1, 2, and 3 kV are examined and compared to simulation.
KEYWORDS: Etching, Electron beams, Monte Carlo methods, Photoresist processing, Hydrogen, Imaging systems, Electron beam lithography, Photomasks, Oxygen, Reactive ion etching
Namatsu, van Delft, and others have reported printing exceptionally small features using high voltage (>50kV) electron beam exposure of hydrogen silsesquioxane (HSQ). They also reported that HSQ has very high exposure dose requirements (~2000(mu) C/cm2 at 100kV). We have explored the utility of HSQ as a resist for low-voltage electron beam lithography. Because low energy electrons have a very limited penetration depth, a thin film imaging technique must be employed in conjunction with anisotropic oxygen reactive ion etching to generate the high aspect-ratio features required to provide adequate etch resistance for subsequent image transfer steps. HSQ's exceptionally low oxygen plasma etch rate makes it an excellent top layer for a bilayer process of this sort. High resolution, high aspect ratio images were printed with this system using 1kV electrons with an imaging dose of less than 60 (mu) C/cm2. The resulting features have very smooth sidewalls. Monte Carlo simulations have been performed for the exposure process and compared to experimental results.
Electron beam lithography systems have historically had low throughput. The only practical solution to this limitation is an approach using many beams writing simultaneously. For single-column multi-beam systems, including projection optics (SCALPELR and PREVAIL) and blanked aperture arrays, throughput and resolution are limited by space-charge effects. Multibeam micro-column (one beam per column) systems are limited by the need for low voltage operation, electrical connection density and fabrication complexities. In this paper, we discuss a new multi-beam concept employing multiple columns each with multiple beams to generate a very large total number of parallel writing beams. This overcomes the limitations of space-charge interactions and low voltage operation. We also discuss a rationale leading to the optimum number of columns and beams per column. Using this approach we show how production throughputs >= 60 wafers per hour can be achieved at CDs <EQ 100 nm, independent of both wafer diameter and die size. The Cost-of-Ownership (CoO) advantages of direct-write (maskless) lithography are significant especially for small-volume semiconductor fabrication, for example ASICs, SOCs and MPUs.
An inspection system has been developed that uses high-speed electron- beam imaging combined with digital image processing to automatically locate defects on semiconductor wafers. The system inspects wafers using a low beam energy of 0.8 KeV and a scan speed that is as much as 1000 times faster than traditional SEMs. This paper describes the system and presents characterization testing results of the system's ability to find defects on advanced integrated circuits. Three unique applications for the new automated scanning electron microscope inspection system (SEMSpec) have been found. First, the high resolution of the electron imaging microscope allows the tool to find much smaller defects than optical inspection systems can find. The SEMSpec system found defects smaller than 0.1 micrometers in size, even on densely packed, sub-quarter micron, high aspect ratio, multilayer geometries. Second, wafers that are late in the fabrication process are much easier to inspect at high sensitivity by SEMSpec than by optical means. This is because SEMSpec images are much cleaner than optical images when viewing grainy poly, metal, or other interconnect layers. Third, the SEMSpec system can sometimes find electrical problems by observing charge-induced voltage contrast differences. Voltage contrast occurs when some of the IC features are electrically defective and they charge up differently under the electron beam than they normally would. The SEMSpec system can then identify them as defective even though they might otherwise appear to be perfectly formed.
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