Dr. Alessio Spessot Profile

Dr. Alessio Spessot

at imec

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Publications (12)

Proceedings Article | 12 October 2021 Presentation + Paper

Analysis of advanced technology nodes and h-NA EUV introduction: a cost perspective

Gioele Mirabelli, Jane Wang, Darko Trivkovic, Pieter Weckx, Alessio Spessot, Kurt Ronse, Ryoung Han Kim, Geert Hellings, Julien Ryckaert

Proceedings Volume 11854, 118540D (2021) https://doi.org/10.1117/12.2600804

KEYWORDS: Extreme ultraviolet, Optical lithography, Metals, Lithography, Extreme ultraviolet lithography, Back end of line, Semiconducting wafers, Standards development, Front end of line, Very large scale integration

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Proceedings Article | 22 April 2021 Presentation + Paper

Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm

Bilal Chehab, Julien Ryckaert, Pieter Schuddinck, Pieter Weckx, Naoto Horiguchi, Gioele Mirabelli, Alessio Spessot, Myunghee Na

Proceedings Volume 11614, 116140D (2021) https://doi.org/10.1117/12.2583395

KEYWORDS: Back end of line, Standards development, Metals, Field effect transistors, Multiplexers, Logic, Fin field effect transistors, Dielectrics, Control systems, Clocks

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Proceedings Article | 25 March 2020 Presentation

Progression of Logic Device and DTCO to enable advance scaling (Conference Presentation)

Satadru Sarkar, Bilal Chehab, Julien Ryckaert, Myung Hee Na, Alessio Spessot

Proceedings Volume 11328, 113280P (2020) https://doi.org/10.1117/12.2551690

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Proceedings Article | 23 March 2020 Presentation + Paper

Sequential 3D standard cell 4T architecture using design crenellation and self-aligned MOL for N2 technology and beyond

Pieter Weckx, Bilal Chehab, Julien Ryckaert, Diederik Verkest, Alessio Spessot

Proceedings Volume 11328, 113280A (2020) https://doi.org/10.1117/12.2552032

KEYWORDS: Standards development, Metals, 3D imaging standards, Logic, System on a chip, Back end of line, Semiconducting wafers, Optical lithography, Wafer bonding, Fin field effect transistors

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Proceedings Article | 23 March 2020 Presentation + Paper

Standard cell architectures for N2 node: transition from FinFET to nanosheet and to forksheet device

Bilal Chehab, P. Weckx, J. Ryckaert, D. Jang, D. Verkest, A. Spessot

Proceedings Volume 11328, 1132807 (2020) https://doi.org/10.1117/12.2548573

KEYWORDS: Fin field effect transistors, Field effect transistors, Optical lithography, Metals, Extreme ultraviolet, Etching, Multiplexers, Dielectrics, Logic devices, Logic

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Proceedings Article | 27 March 2019 Presentation + Paper

Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

S. M. Yasser Sherazi, Miroslav Cupak, P. Weckx, O. Zografos, D. Jang, P. Debacker, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, J. Ryckaert

Proceedings Volume 10962, 1096202 (2019) https://doi.org/10.1117/12.2514569

KEYWORDS: Metals, Optical lithography, Fin field effect transistors, Extreme ultraviolet, Standards development, Silicon, Line edge roughness, Computer architecture, Process control

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Proceedings Article | 20 March 2019 Presentation + Paper

Optimization of read and write performance of SRAMs for node 5nm and beyond

Khaja Ahmad Shaik, Mohit Gupta, Pieter Weckx, Alessio Spessot

Proceedings Volume 10962, 1096203 (2019) https://doi.org/10.1117/12.2515162

KEYWORDS: Resistance, Extreme ultraviolet, System on a chip, Optical lithography, Capacitance, Logic, Laser induced breakdown spectroscopy, Transistors, Fabrication

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Proceedings Article | 20 March 2019 Presentation + Paper

CFET standard-cell design down to 3Track height for node 3nm and below

S. M. Y. Sherazi, J. K. Chae, P. Debacker, L. Matti, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, A. Dounde, J. Ryckaert

Proceedings Volume 10962, 1096206 (2019) https://doi.org/10.1117/12.2514571

KEYWORDS: Transistors, Metals, Logic, Standards development, Nanowires, Silicon, Field effect transistors, Fin field effect transistors, Semiconducting wafers, Electronic components

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Proceedings Article | 20 March 2019 Presentation + Paper

Backside power delivery as a scaling knob for future systems

Bharani Chava, Khaja Ahmad Shaik, Anne Jourdain, Sofiane Guissi, Pieter Weckx, Julien Ryckaert, Geert Van Der Plaas, Alessio Spessot, Eric Beyne, Anda Mocuta

Proceedings Volume 10962, 1096205 (2019) https://doi.org/10.1117/12.2514942

KEYWORDS: Metals, Logic, Standards development, Semiconducting wafers, Resistance, Clocks, Switches, Silicon, Chemical mechanical planarization, Device simulation

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Proceedings Article | 20 March 2018 Presentation + Paper

Track height reduction for standard-cell in below 5nm node: how low can you go?

S.M. Yasser Sherazi, Jung Kyu Chae, P. Debacker, L. Matti, P. Raghavan, V. Gerousis, D. Verkest, A. Mocuta, R.H. Kim, A. Spessot, J. Ryckaert

Proceedings Volume 10588, 1058809 (2018) https://doi.org/10.1117/12.2297191

KEYWORDS: Metals, Dielectrics, Standards development, Optical lithography, Logic, Photomasks, Transistors, Extreme ultraviolet, Silicon

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Proceedings Article | 20 March 2018 Presentation + Paper

DTCO exploration for efficient standard cell power rails

Bharani Chava, Julien Ryckaert, Luca Mattii, Syed Muhammad Yasser Sherazi, Peter Debacker, Alessio Spessot, Diederik Verkest

Proceedings Volume 10588, 105880B (2018) https://doi.org/10.1117/12.2293500

KEYWORDS: Resistance, Ruthenium, Standards development, Metals, Optical lithography, Transistors, Copper, Capacitance, Resistors

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Proceedings Article | 4 April 2017 Paper

Low track height standard cell design in iN7 using scaling boosters

S. M. Sherazi, C. Jha, D. Rodopoulos, P. Debacker, B. Chava, L. Matti, M. Bardon, P. Schuddinck, P. Raghavan, V. Gerousis, A. Spessot, D. Verkest, A. Mocuta, R. Kim, J. Ryckaert

Proceedings Volume 10148, 101480Y (2017) https://doi.org/10.1117/12.2257658

KEYWORDS: Front end of line, Metals, Back end of line, Standards development, CMOS technology, Capacitance, Logic, Semiconductors, Transistors

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Showing 5 of 12 publications

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