3D heterogeneous integration is an evolving segment of the world semiconductor industry roadmap to enable improvements in device performance beyond Moore’s law expectations. These “More than Moore” (MtM) performance enhancements have the potential for realizing dramatic improvements in communication bandwidth, design flexibility that enables new system architectures on-chip or at the wafer level, and overall cost reduction. 3D heterogeneous integration strives to increase electrical connectivity through pitch and contact dimensional scaling to enable <10μm pitch solder bump scaling, and sub-micrometer hybrid Cu/dielectric fusion bond connectivity. Integration options include wafer to wafer (W2W), pick-and-place (P&P), and die to wafer (D2W) assembly strategies. Enhanced process capability and systems architecture imposes new overlay (OVL) metrology challenges to address variable silicon substrate thickness, stressinduced wafer or die distortions, and tight OVL error specifications. In this work, we will cover the OVL trends and challenges surrounding this evolving segment. We will cover different OVL aspects such as accuracy, measurability, reproducibility, and throughput and discuss their impact on pre and post-bonding error budgets.
In recent years, lithographic printability of overlay metrology targets for memory applications has emerged as a significant issue. Lithographic illumination conditions such as extreme dipole, required to achieve the tightest possible pitches in DRAM pose a significant process window challenge to the metrology target design. Furthermore, the design is also required to track scanner aberration induced pattern placement errors of the device structure. Previous workiii, has shown that the above requirements have driven a design optimization methodology which needs to be tailored for every lithographic and integration scheme, in particular self-aligned double and quadruple patterning methods. In this publication we will report on the results of a new target design technique and show some example target structures which, while achieving the requirements specified above, address a further critical design criterion – that of process resilience.
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