We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and
stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a
number of questions that arise in such simulations. These questions include identification of stress effects causing
context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due
to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of
corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin
determination.
The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI
65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours.
Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and
active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated
changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools
were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells
with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation
from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability
analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on
timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a
real design.
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