We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High
Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s
publication [1]. Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are
demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic
requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either
random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the
guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast
DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed
different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the
Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before [2], we implement a 2D
phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more
predictive than compact model but much faster then the physics-based MC model. However simplifying the model might
lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro
full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with
pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip
runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm
based lithography process using DSA.
In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography
has been explored and documented in the literature.1-5 It has been shown that intensive optimization of the fundamental
degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the
source, which leads to improved lithographic performance. These efforts have driven the need for improved controllability
in illumination5-7 and have pushed the required optimization performance of mask design.8, 9 This paper will present recent
experimental evidence of the performance advantage gained by intensive optimization, and enabling technologies like pixelated
illumination. Controllable pixelated illumination opens up new regimes in control of proximity effects,1, 6, 7 and we
will show corresponding examples of improved through-pitch performance in 22nm Resolution Enhancement Technique
(RET). Simulation results will back-up the experimental results and detail the ability of SMO to drive exposure-count reduction,
as well as a reduction in process variation due to critical factors such as Line Edge Roughness (LER), Mask Error
Enhancement Factor (MEEF), and the Electromagnetic Field (EMF) effect. The benefits of running intensive optimization
with both source and mask variables jointly has been previously discussed.1-3 This paper will build on these results by
demonstrating large-scale jointly-optimized source/mask solutions and their impact on design-rule enumerated designs.
The process of preparing a sample plan for optical and resist model calibration has always been tedious. Not only
because it is required to accurately represent full chip designs with countless combinations of widths, spaces and
environments, but also because of the constraints imposed by metrology which may result in limiting the number of
structures to be measured. Also, there are other limits on the types of these structures, and this is mainly due to the
accuracy variation across different types of geometries. For instance, pitch measurements are normally more accurate
than corner rounding. Thus, only certain geometrical shapes are mostly considered to create a sample plan. In addition,
the time factor is becoming very crucial as we migrate from a technology node to another due to the increase in the
number of development and production nodes, and the process is getting more complicated if process window aware
models are to be developed in a reasonable time frame, thus there is a need for reliable methods to choose sample plans
which also help reduce cycle time.
In this context, an automated flow is proposed for sample plan creation. Once the illumination and film stack are defined,
all the errors in the input data are fixed and sites are centered. Then, bad sites are excluded. Afterwards, the clean data
are reduced based on geometrical resemblance. Also, an editable database of measurement-reliable and critical structures
are provided, and their percentage in the final sample plan as well as the total number of 1D/2D samples can be
predefined. It has the advantage of eliminating manual selection or filtering techniques, and it provides powerful tools
for customizing the final plan, and the time needed to generate these plans is greatly reduced.
Source optimization in optical lithography has been the subject of increased exploration in recent years [1-4], resulting in
the development of multiple techniques including global optimization of process window [4]. The performance
advantages of source optimization have been demonstrated through theory, simulation, and experiment. This paper will
emphasize global optimization of sources over multiple patterns, e.g. co-optimization of critical SRAM cells and the
critical pitches of random logic, and implement global source optimization into current resolution enhancement
techniques (RETs). The effect on optimal source due to considering multiple patterns is investigated. We demonstrate
that optimal source for limited patterns does work for a large clip of layout. Through theoretical analysis and
simulations, we explain that only critical patterns and/or critical combinations of patterns determine the final optimal
source; for example those patterns that contain constraints which are active in the solution. Furthermore, we illustrate,
through theory and simulation, that pixelated sources have better performance than generic sources and that in general it
is impossible for generic sources to construct a truly optimal solution. Sensitivity, tool matching, and lens heating issues
for pixelated sources are also discussed in this paper. Finally, we use a RETs example with wafer data to demonstrate the
benefits of global source optimization.
As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process
windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC
verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust
solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively
impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and
verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process
robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable
first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by
identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not
catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable
of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while
maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented
for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC.
Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen
the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process
variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.
Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently,
the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry
is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh
diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that
enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through
innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful
lithography-design optimization.
KEYWORDS: Optical proximity correction, Data modeling, Photomasks, Critical dimension metrology, Calibration, Process modeling, Semiconducting wafers, Model-based design, Reticles, Control systems
The impact of mask CD non-uniformity on the accuracy of optical proximity correction (OPC) models has been
observed on several critical levels. In the current OPC model calibration flow, the mask effect is not explicitly separated
from the optical and resist models. Instead, the resist model is compensating for the mask errors. In this paper, we report
a detailed study of the effect of mask CD non-uniformity on OPC model accuracy using the established OPC model
calibration flow. The influence of mask CD non-uniformity on the through process behavior of an OPC model is also
discussed. A possible OPC flow to take the systematic mask CD error into consideration is proposed and a detailed
study of mask modeling is present.
As the industry moves toward 45nm technology node and beyond, further reduction of lithographic process window is anticipated. The consequence of this is twofold: first, the manufactured chip will have pattern sizes that are different from the designed pattern sizes and those variations may become more dominated by systematic components as the process windows shrink; second, smaller process windows will lead to yield loss as, at small dimensions, lithographic process windows are often constrained by catastrophic fails such as resist collapse or trench scumming, rather than by gradual pattern size variation. With this notion, Optical Proximity Correction (OPC) for future technology generations must evolve from the current single process point OPC to algorithms that provide an OPC solution optimized for process variability and yield. In this paper, a Process Window OPC (PWOPC) concept is discussed, along with its place in the design-to-manufacturing flow. Use of additional models for process corners, integration of process fails and algorithm optimization for a production-worthy flow are described. Results are presented for 65nm metal levels.
The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.
This paper discusses the resolution capabilities of proximity x-ray lithography (PXRL) system. Exposure characteristics of features designed at 150 nm pitch size: 75 nm dense lines with 1:1 duty ratio, 2D features at 1:1 and 1:2 duty ratios and isolated lines have been studied. Aerial image simulations were compared to the experimental data. Verification of the aerial image model has been accomplished by measurements of exposure windows of 100 nm and 125 nm nested lines. The PXRL aerial image parameter, equivalent penumbra blur, has been determined from the experimental data. Contributions from the synchrotron radiation x-ray source, stepper and the chemically amplified resist to the degradation of the aerial image have been evaluated. Patterning capability of PXRL at 75 nm feature size is compared to projection optics using the optical k1 factor as a common figure of merit. To facilitate the comparison, optical imagin was at pattern sizes currently manufacturable by the mainstream optical tools while the PXRL imaging was at 75 nm pattern size. Requirements for a PXRL system of manufacturing VLSI at 70 nm minimum feature sizes with the critical dimension control better than 10 percent are also discussed.
Defect repair is a key component in fabricating a defect- free mask. Focused ion beam repair has been successfully used for x-ray masks. To repair an opaque defect the ion beam is used to mill away the excess absorber while clear defect repair requires beam assisted deposition of Au. Current x-ray mask repair tools specify edge placement accuracy of +/- 25 mask nm. However, the effects of non- ideal repairs on printed resist have not been investigated, and the tolerance of such errors have not been specified. In this study, reported defect printing was tracked and resists edge placement accuracy was measured to evaluate the non- ideal repair effects. In the opaque defect repair case, we observed inside the 'repair box', repaired mask errors such as sloped walls, remaining absorber and re-deposition outside the box and found that these errors shift the printed resist pattern edge toward the inside of the box. In the clear defect repair case, the deposited gold is typically extended out of the defined box by sloped side- wall and the printed resist pattern edge is shifted toward the outside of the box. These non-ideal repairs systematically affect resist pattern edge placement. An x- ray lithography simulation tool was used to analyze these effects. Preliminary by adjusting the 'repair box' size and etch/deposition time, the effects of non-ideal repair can be eliminated. Programmed defects were created on a mask and repairs were performed, evaluated and optimized with actual x-ray exposures.
Fresnel zone plates (ZP) have gained popularity as the optics of choice for advanced microfocusing applications. The main virtues of ZP are high resolution, high efficieny, low background, coherence preservation, and ample working distance. Zone plates are also unique because they are a normal incidence x-ray optics, which are much easier to align and use compared to other grazing incidence optics. We will report here recent progress that has drastically enhanced the performance of ZPs in 1) higher spatial resolution, 2) higher focusing efficiency, and 3) extension to higher energies. With the new developments, zone plates have proven to be one of the best microfocusing optics for monochromatic x-ray beams.
In this paper, dimensional control of critical features in proximity x-ray lithography is discussed. CD error components attributed to x-ray mask, proximity exposure and resist process are identified. Analysis of linewidth control data at 180 nm and 150 nm ground rules for synchrotron based x-ray proximity lithography is presented. Data have been collected at IBM Advanced Lithography Facility equipped with x-ray stepper built by SVGL and Helios synchrotron radiation x-ray source.
Chet Wasik, G. Murphy, Alek Chen, Azalia Krasnoperova, Alex Flamholz, Daniel DeMay, Jeffrey Leavey, Steve Loh, Sue Chaloux, Alan Thomas, Sang Lee, Kenneth Giewont, Paul Agnello
X-ray lithography has been used in mix and match mode with optical steppers to build test circuits in support of DRAM and Logic development at IBM's Advanced Semiconductor Technology Center, ASTC. Prior to building the test devices, hundreds of wafers were exposed using x-ray lithography to define the etch processes for critical levels and to help separate optical lithography, resist and etching effects. The demand for this type of support required IBM's Advanced Lithography Facility (ALF) to focus on a set of pilot line issues not previously faced by this emerging lithography. The challenges and solutions which resulted are discussed. This paper examines the requirements for the introduction of x-ray into pilot line use based on ALF's most recent experience and performance.
In this paper, experimental formulations of ESCAP photoresist with two different photoacid generators (PAG) are compared for x-ray and DUV (248 nm) exposures. Sensitivities, chemical contrasts and development selectivities have been derived from dissolution rate and FTIR data collected under similar process conditions. X-ray exposed experimental resists are also compared to a commercial UVIIHS photoresist. Linewidth performances of the x-ray exposed resists are presented at 175 nm ground rules. Relationships between the photoresists contrasts (both chemical and development), dissolution rates of fully exposed and unexposed resists, aerial image properties and linewidth exposure budget are discussed. Effect of a dissolution inhibitor on x-ray linewidth performance is shown.
Alek Chen, Alex Flamholz, Azalia Krasnoperova, Robert Rippstein, Ben Vampatella, George Gomba, Robert Fair, William Chu, V. Dimilia, J. Silverman, R. Amodeo, Dave Heald, P. Kochersperger, Carl Stahlhammer
A state-of-the-art proximity x-ray lithography aligner was developed for the Defense Advanced Lithography Program (DALP) and installed in IBM's Advanced Lithography Facility (ALF) in 1995. This aligner was designed to satisfy the manufacturing requirements for 250 and 180 nm groundrule electronic devices, such as 256 Mbit and 1 Gbit DRAMs, while connected to synchrotron beamlines which use scanning beam systems for x- ray flux delivery. The aligner uses an innovative x-ray image sensor (XRIS) to align the mask by detecting its x-ray actinic image, and uses an off-axis alignment system, similar to the alignment system used in Micrascan-II, to align the wafer. As a result, the same wafer alignment marks can be used by either tool. This facilitates the mix and match between the x-ray aligner and Micrascan-II optical steppers. A stabilized helium environment is maintained from the beryllium window of the beamline to the exposure plane, including the gap between mask and wafer. The aligner can accept x-ray masks that conform to NIST standards, and has a maximum exposure field of 50 mm by 50 mm. The important lithography performance parameters, i.e., overlay, linewidth control and throughput, have been evaluated. The test methodologies and their results are presented in detail. Potential improvements of the system's performance will also be discussed.
The use of the X-ray lithography to produce blazed diffractive optical elements (DOEs) is described. The proposed method allows one to make highly efficient blazed DOE with a deep phase profile (ten wavelengths and more) using a single X-ray mask with a binary transmission pattern. Unlike the well-known multilevel DOEs, blazed ones do not involve fabrication and aligning of a set of masks. DOEs with a profile depth of 10 micrometers and more and zone sizes of down to 1 micrometers can be obtained due to the short wavelength and high penetrability of X- rays. The first experimental samples of blazed DOEs with a 10 micrometers -height profile (lenses and gratings) were fabricated by X-ray lithography with synchrotron radiation using the X-ray masks, prepared in accordance with the pulse-width modulation algorithm. Diffraction efficiency for lenses was measured for white light. It is higher than 80 percent for the central part of the lenses (inside a 10 mm diameter) and about 60 percent for an area of 20 mm diameter.
Lithographic techniques for fabrication of hard x-ray Fresnel zone plates are discussed. Practical results achieved at the Center for X-ray Lithography of the University of Wisconsin- Madison are presented. Fabrication technology includes replication of an e-beam written master mask into a thick photoresist by synchrotron radiation x-ray lithography, and subsequent electroplating of a metal zone plate structure using photoresist pattern as a mold.
Deep X-ray lithography is a fabrication process for the production of a broad variety of microstructures with large structural heights. These can reach several hundred micrometers, with minimum lateral dimensions on the order of several microns. The main difference between ULSI and micromachining XRL is in the use of high-contrast masks (HCMs), with contrast in excess of 100. We fabricate these HCMs using a negative-tone resist to yield a coy of an original e-beam-made thin X-ray mask. Thus, we have fabricated HCMs with 6- micrometers -thick gold absorbers on SiN membranes using X-ray lithography replication. In our HCM fabrication process, it is possible to control the absorber sidewall by adjusting the exposure dose and development time. In this way, it is possible to generate absorbers sidewalls with slopes as large as 70 degrees. We have observed that when using HCM with sidewall slopes the exposed resist structures display sloping sidewalls as well. This opens the possibility of generating tapered structures and other complex shapes. This approach becomes even more interesting when combined with multilevel lithography, where different levels may be formed in the same resist layer by multiple exposures. We will present both experimental results and an image formation study that includes in detail the effect absorber topology, and the relation between mask sidewall slopes and resist sidewall slopes.
The actinic spectra of two beamlines of the University of Wisconsin's Center for X-ray Lithography (CXrL) at the Aladdin storage ring were studied in three configurations. Some beamlines optimized for particular bandwidths are presented and their impact on mask making, aerial image quality, printed image quality, and device damage discussed. Resist performance dependence on the actinic spectrum is investigated. The exposure-gap tree response of 0.25 micron features is presented for different spectra. Resist characteristic curve data were collected for these conditions and are compared.
This paper reports the initial results on modeling of a positive chemically amplified photoresist for x-ray lithography. A positive tone chemically amplified photoresist, APEX-M from the IBM Corp., was exposed with synchrotron radiation. A kinetic model for exposure and post- exposure bake has been developed. The FTIR spectroscopy measurement data show that the photoacid loss reaction during post-exposure bake is described as a second order reaction. For the mask patterned photoresist, this leads to a nonlinear diffusion -- reaction equation. It was shown that the second order photoacid loss mechanism results in different values of the photoacid diffusion range for different exposure doses. A simulation method has been developed to take into account simultaneously photoacid diffusion and photoacid loss for the latent image of the photoresist. The x-ray exposure simulation tool XLITH and the photoresist development simulator SAMPLE-3D have been used for verification of the model for 0.25 micrometers patterns. The experimental and simulated profiles have shown good agreement.
In this paper we present the activities at the Center for X-ray Lithography (CXrL) that are dedicated to applying x-ray lithography to 0.25 micrometers processing. We first present the results of optimizing the parameters of the x-ray resist, AZ-PF 514, to achieve 0.25 micron features with variations of less than 10%; second, we discuss the properties of an exposure station (ES3) that feeds the in-house built aligner; third, we present the novel in-house built Two State Aligner (TSA) and its ability to achieve < 32 nm registration error; fourth, we present a developed fabrication process that produces masks with the required membrane stress, optical transparency, and mask flatness; and finally, we present the integration of all the above subprocesses by showing preliminary results from the in-progress 0.25 micrometers NMOS device run. The requirements and results of each sub-process are discussed and judged according to the 0.25 micrometers error budget goals that were initially set for 1997.
This paper presents the results of a simple orthogonal matrix experiment testing photoresist performance as a function of post exposure bake temperature and time. The dose latitude of quarter micron line/space pairs is found under these conditions. These empirical results are compared against those produced under identical process conditions but utilizing simulated images based on resist dissolution rate data. The matrix responses of the empirical and simulated data sets are compared. Also, these linewidth results are compared against resist characteristic data produced under identical process conditions. The matrix responses of the three data sets are compared.
We have performed experiments to study the kinetics of dissolution of the positive chemically amplified resist AZ-PF (Hoechst AG). The resist dissolution in exposed regions was shown to have non-linear time dependence, with a delay time strongly dependent on prebake and post- exposure bake conditions. Effect of the presence of a low-solubility surface layer on patterning of submicron features as well as on roughness of the developed film has been demonstrated.
The establishment of standard resist processes are a primary requirement for the X-ray Lithography National Test Bed at the Center for X-ray Lithography. For this, experimental design is a necessary component of the methodology given the large parameter space associated with chemically amplified resists (CARs). The process development is carried out in three phases. DOX is applied to several steps in the development. The vacuum hot plate pre-bake, post-bake time, temperature and the exposure dose have the greatest effect on controlling the performance of the resist. Constraints are placed on the contrast, develop time and unexposed resist loss. The exposure dose needed to meet these requirements is obtained from the modified response surface of the bulk behavior. The final optimization is based on the CD control and side wall angle for quarter-micron features in resist. The process is run on a sampled basis in order to determine the control issues. Control limits are set from these data, and the process performance is determined.
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