Resist supplier has successfully demonstrated applying negative tone resist into ArF lithography. It is capable of
achieving 50nm dense line and <30nm isolated space pattern by over dose operation in topcoat-free immersion
lithography. Additionally, using ArF dry system with double exposure could also realize 65nm gridded contact hole
patterns. For specific application, negative PR ArF lithography has better benefit of cost and process control capability
than other approaches. In this paper, we have determined process capability of 65nm gridded contact hole by ArF dry
double patterning and compared with LELE process in terms of DOF, EL and CDU and cost. By continuously
optimizing process parameter, >0.21um DOF and 4.6nm global CDU are achieved on DRAM capacitor process. It
revealed strong relation to development parameter setting. Furthermore, specific pattern formation considering optical
items, ex: OPE, NRF (non-resolution feature) and interaction between double exposure have also been analyzed and
difficulties of generating a specific pattern with negative tone resist double exposure have been figured out.
When the feature size keep shrinking to 4Xnm, ArF lithography has already proceed to immersion process and became
mature enough. There is an important factor that will obviously influence photo process window in the initial phase
development is the optical reflection from imperfect substrate design. From previous experience, reflection would be
optimized to fine level by adjusting TARC (Top Anti-Reflection Coating) or BARC (Bottom Anti-Reflection Coating)
thickness through index of reflectivity. However, actual criteria of reflectivity for various ArF lithography process are
unlikely the same, e.g. different system type (wet/dry), node (feature size), illumination type, or even substrate effect,
and also need to be examined to retain a decent process window. In this paper, experimental result of various abovementioned
ArF process have been compared with reflectivity index from prolith simulation engine, and distinctly
clarified criteria of reflectivity for each case. Furthermore, effects of reflection to several optics caused patterning-related
results, e.g. IDB (Iso-Dense Bias), OPC (Optical Proximate Correction) accuracy, will also be discussed. The result also
shows severe criterion of reflection is requested as feature size getting smaller to 4Xnm node, and RET-applied
(Resolution Enhancement Technology) process has opposite result on it. From experimental results, IDB has been
obviously affected by reflection and become one important factor that influences reflection criterion examination.
Immersion technology is definitely the mainstream lithography technology for NAND FLASH in recent years since
hyper-NA immersion technology drives the resolution limit down to the 40-50 nm half pitch region. Immersion
defectivity and overlay issues are key challenges before introducing immersion technology into mass production. In this
work, both long term immersion defectivity and overlay data, as well as good photoresist performance, show the Nikon
S610C immersion scanner plus LITHIUS i+ cluster is capable of 40-50 nm NAND FLASH mass production. Immersion
defects are classified based on their causes, and no tool specific immersion defects, e.g. bubbles and water marks, were
found in the Nikon S610C plus TEL LITHIUS i+ cluster. Materials-induced immersion defects require more attention to
achieve production-worthy results.
As the semiconductor industry continues to drive towards high volume production at the 50nm technology node and
beyond, there are formidable barriers imposed not only from technical challenges but also from economic challenges
related to controlling overlay tightly enough to meet the strict requirements of a increasingly smaller overlay control
window. In this paper, the authors will show potential sources overlay error for a 50nm node process and detail a
methodology to pinpoint the root cause and an application to help reduce these errors to facilitate the ramp of a new
process technology for high volume DRAM/FLASH manufacturing. In short, based on a series of experiments and
analysis, the authors have identified high-order wafer-level residual component to be the main contribution of the high
residuals with the source attributed to the scanner mix-and-match set. In turn, an overlay control approach using high
order correctables generated from the overlay metrology system and fed through the APC system will be able to
effectively reduce the mix-and-match high residual errors.
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