Beyond the 40nm technology node, layout weak points and hotspot types increase dramatically. Many hotspots can be detected by OPC simulation. However, in advanced nodes, OPC simulation suffers from a long turn-around-time (TAT) and is challenged to handle the additional design complexity. Therefore, in order to speed up the process and OPC development, an efficient OPC hotspot detection method is required. This paper presents a flow using Pegasus Computational Pattern Analytics (CPA) technology from Cadence to extract a comprehensive set of patterns to build a pattern bank from a layout source. We can then compare two or more different banks (diffing) to find new patterns which have not been processed before. OPC engineers can analyze these new patterns to check for any OPC issues instead of simulating a full chip. This flow provides a much higher efficiency and better performance while allowing the storage of pattern banks over time to build history and yield experience. Over time, each new layout introduced for OPC can be processed faster because more patterns have been added to the banks and less simulation time is needed.
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