Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in
the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has
penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability
concerns. This requires very accurate models to analyze the manufacturability issues. This also often requires
simultaneous analysis and optimization of both layout and the process. Most advanced layout patterns are extremely
hard to manufacture and consequently run into the risk of re-spins. Therefore, an early pre-tapeout analysis and
troubleshooting of various layout, process, and RET issues has become a very important task. Our paper gives examples
of how these and other related issues can be addressed using a commercially available Design-for-Yield integrated
environment.
As we delve deeper into subwavelength design and manufacturing challenges and solutions, technologies such as Optical Proximity Correction (OPC) and Phase Shifting Masks (PSM) have become essential to reliabily produce advanced integrated circuits. Alternating PSM (altPSM) has demonstrated many recent successses as an effective means to this end. This paper lays the groundwork for defining the IC design components needed to meet altPSM-compliance requirements. The paper addresses the open question regarding whether we can take into account all the manufacturing requirements and come up with highly abstract manufacturing rules that can be applied to all IC design domains. The paper further proposes a solution with specific rules and algorithms needed to apply altPSM to transistor gate regions, and targeted to various domains of IC design such as verification or place and route. Examples include constraints for routers and placement tools, as well as sign-off rules that can be used by designers as well as by production engineres to fine-tune the process and yield for a given design structure. The usability of such a solution is then analyzed to take the practical aspects of IC design into consideration.
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