The ASML extreme ultraviolet lithography (EUV) alpha demo tool is a 0.25NA fully functional lithography
tool with a field size of 26×33 mm2, enabling process development for sub-40-nm technology. Two exposure
tools are installed in two research centers.
The main topic of this paper is the examination of the measured pattern roughness LER contributed by
measurement (SEM), exposure (EUV exposure tool) and the resists itself. The authors also examined
suspected metrology SEM challenges on different EUV resist types exposed by one of the EUV demo tools.
Standard CD SEM tests, such as precision and shrinkage were performed in order to get best working
conditions. As part of the research, special attention was given to expected electron - material interactions,
such as resist's slimming, low contrast and contamination build up on both lines. LER was analyzed in order
to determine separately the contribution effect of the exposure tool and the different resists. Additional
comparison was performed on different CDs with different orientations and densities.
Ilan Englard, Raf Stegen, Peter Vanoppen, Ingrid Minnaert-Janssen, Ted der Kinderen, Erik van Brederode, Frank Duray, Jeroen Linders, Denis Ovchinnikov, Rich Piech, Claudio Masia, Noam Hillel, Erez Ravid, Ofer Rotlevi, Amir Wilde, Saar Shabtay, Zach Telor, Robert Schreutelkamp
Increase of Depth of Focus (DOF) and higher Numerical Aperture (NA), make of immersion lithography a sub-50nm
technology node enabler. At the same time it introduces a range of new defect types, also known as immersion defects.
According to the ITRS roadmap, the Smallest Defect Of Interest (SDOI) for the 45nm node has a size of 30nm [1] which
is the minimal defect size which poses risk to the integrity of the post litho chain processes. A novel approach of
Immersion Defectivity Baseline creation and monitoring has been developed for the 45nm technology node by ASML,
supported by Applied Materials. An Immersion Defectivity Baseline consists of: a qualified stack, a dedicated
defectivity reticle, a Defect Inspection Tool with an optimized inspection recipe, a Defect Review SEM with an
optimized defect review recipe and a defect qualification scheme. The new approach to Immersion Defectivity Baseline
creation is based on the combined capabilities of highest resolution bright-field inspection and SEM (Scanning Electron
Microscopy) review that are available today, with a unique qualification methodology using printed programmed defects
that cover the full printable size range. The inspection tool's SDOI detection sensitivity has been optimized for
engineering, production as well as monitoring modes, with negligible nuisance rate and basic classification capability
followed by highly accurate SEM review and classification. As a result, it enables a stringently controlled, highly
efficient, automated defect classification for baseline monitoring and increased productivity. The SEM material analysis
sub-apparatus complete the control loop for baseline creation and excursion control. This paper presents a protocol for
Immersion Defectivity Baseline creation and control methodologies used for the latest ASML immersion scanner.
Multi patterning lithography (MPL) breaks the k1=0.25 barrier to become the main candidate for 32nm device
fabrication before 2010. When using MPL, overlay (OVL) becomes an essential part of the overall critical dimension
(CD) budget and therefore can no longer be treated as a separate process control measure. Furthermore, the CD measured
at each of the two consecutive lithography steps must be combined into one single 32nm process control measure and
will require further improvements of CD-SEM precision, resolution and accuracy.
The metrology challenges involved in measuring double patterning CD and OVL arise from the fact that across chip
pitch variations (ACPV) are determined by the two separate lithographic processes [1]. This aspect makes the control of
the process significantly more complex and requires careful measurement of the processes, both individually as well as
combined. Meeting the ITRS specifications for CD and localized OVL measurements beyond 32nm half pitch is
challenging and will require innovative CDSEM algorithmic solutions.
This paper is a follow-up from last year's paper that introduced SEM metrology for MPL technology. In this paper, we
report on the actual implementation of combined CD and OVL metrology solutions for the latest immersion scanner
generation. We will describe the latest OVL measurements performed at ASML and demonstrate the robustness of the
novel algorithm for accurate separation and recombination of two individual CD populations related to the consecutive
MPL steps.
KEYWORDS: Overlay metrology, Critical dimension metrology, Etching, Lithography, Monte Carlo methods, Scanning electron microscopy, Metrology, Semiconducting wafers, Reticles, Algorithm development
Traditionally CD SEM has been positioned as a local critical dimension measurement and analysis technique. Emerging
lithography techniques introduce new challenges for CD SEM such as overlay error measurements. For the sub 45 nm
technology nodes, several new lithography approaches are developed that rely on multiple lithography and deposition
and etch process steps. Seamless integration of these lithography and deposition and etch process steps requires specific
CD and/or overlay metrology capability for optimal CD and overlay registration performance. Areas of development are
focused on CD measurement algorithms and correlation after resist develop and subsequent etch steps. These new
lithography processes require unprecedented accuracy and overlay resolution. Fundamental and application specific
metrology challenges and solutions will be highlighted. In addition, this paper will report on unique overlay target design
in combination with innovative CD SEM measurement techniques to meet those challenges.
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