The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at
lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries
along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized
by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to
the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle
time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer
needs but still manage the computational lithography overhead as well as the patterning process performance, this
process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV
vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems,
comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences
in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary
to switch to the new mask process were analyzed.
In our paper we make an analysis of conditions for the haze development on photomask fabricated on Mo-Si
containing substrates. We bring in focus cases of haze formation on masks with intrinsically very low contaminants level
and being exposed in very well controlled atmosphere. There are clear indications that this new type of haze formation
deviates from the generally accepted models not only with respect to the formation mechanisms but also with regard to
the chemical composition of the haze products. In our analysis we speculate that the new haze type formation is closely
related to the earlier reported CD degradation observed on Mo-Si masks. We also analyze the hypothesis that the
ingredients for the haze formation are not only airborne contaminants and/or traces on the mask surface, but are also
provided by the substrate material. Finally we present and discuss experimental data in the view of the advanced models.
Reticle cost and cycle time to deliver new circuit designs to a wafer fab remain key focus areas for advanced
semiconductor manufacturing and new product development. Resolution enhancement techniques like optical proximity
correction as applied to critical layers have increased the burden on mask data preparation and reticle writing steps of the
mask making flow. The growing data volume and complexity of designs must be reduced to a perfect image on a reticle
in the shortest time possible against computer and machine constraints. Continued dependence on 193 nm wavelength
exposure in extremely low k1 lithography exacerbates the underlying trends.
Two important factors come together to drive the economics and performance of the reticle line: the complexity of the
designs and the productivity of e-beam writing tools. The designs, OPC methods, and writing tool capabilities continue
to evolve with each node of technology. The study builds on prior evaluations to look at fundamental pattern complexity
across 90nm, 65nm, and 45nm logic designs using the gate and metal-1 critical layers. The writing tool throughput
testing uses a range of standard patterns to establish shot limited performance as a calibration method for arbitrary
designs.
Node to node design and tool to tool generation comparisons highlight actual step changes in complexity and capability
by introducing new quantitative methods, benchmarking metrics, and testing strategies. The findings are projected into
the future using design complexity and writing tool trends to suggest implications about reticle cost, cycle time, or
possible gaps in technology development.
Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask
relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to
grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask
makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers'
continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while
some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore,
improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent
and compelling.
The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images,
rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The
idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for
traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance,
which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab
mask qualification to validate defect and dimensional performance.
In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and
logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of
SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is
not only feasible, but, in some cases, desirable.
This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an enhancement to mask
characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a
thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and
disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve
to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization
and qualification.
The semiconductor industry will soon be putting >=1.07NA 193nm immersion lithography systems into production for
the 45nm device node and in about three years will be putting >=1.30NA systems into production for the 32nm device
node. For these very high NA systems, the maximum angle of light incident on a 4X reticle will reach ~16 degrees and
~20 degrees for the 45nm and 32nm nodes respectively. These angles can no longer be accurately approximated by an
assumption of normal incidence. The optical diffraction and thin film effects of high incident angles on the wafer and
on the photomask have been studied by many different authors. Extensive previous work has also investigated the
impact of high angles upon hard (e.g., F-doped silica) thick (>700μm) pellicles for 157nm lithography, e.g.,.
However, the interaction of these high incident angles with traditional thin (< 1μm) organic pellicles has not been
widely discussed in the literature.
In this paper we analyze the impact of traditional thin organic pellicles in the imaging plane for hyper-NA
immersion lithography at the 45nm and 32nm nodes. The use of existing pellicles with hyper-NA imaging is shown to
have a definite negative impact upon lithographic CD control and optical proximity correction (OPC) model accuracy.
This is due to the traditional method of setting organic pellicle thickness to optimize normally incident light
transmission intensity. Due to thin film interference effects with hyper-NA angles, this traditional pellicle optimization
method will induce a loss of high spatial frequency (i.e., high transmitted angle) intensity which is similar in negative
impact to a strong lens apodization effect. Therefore, using simulation we investigate different pellicle manufacturing
options (e.g., multi-layer pellicle films) and OPC modeling options to reduce the high spatial frequency loss and its
impact.
AAPSM masks require OPC correction through pitch in order to print a linear dark line response vs the design CDs. The masks also require correction for the clear intensity imbalance caused by the phased etched Qz wall edge. The clear intensity can be balanced by two approaches;(or a combination of the two) data biasing or wet undercut etching of the Qz etched opening. IC manufacturers would like to use one OPC model that will work for any mask fabrication approach. This paper shows that there is no OPC difference observed in either the aerial image or the printed image of several OPC learning patterns. The study includes CD through pitch for dense (1:1) L/S Patterns and Isolated Line CD vs line-space ratio. The images were analyzed for the dark line linearity, the clear CD balance though pitch, and the clear CD balance with focus (phase error effects -PES).
The mask error enhancement factor for contact holes is experimentally determined for 180 nm features under a variety of exposure conditions. Since its magnitude depends, in part, upon the slope of the aerial image, the value is calculated as a function of binary and phase shift masks, mask bias, and conventional and quadrupole illumination. The primary purpose is to compare experimental results to a simulation study and determine which simulation trends are accurately predicted. The results show that isolated contacts have lower MEEF than dense contacts but that dense contacts do not necessarily have the largest error factor. The magnitude of MEEF and the optimal bias that minimizes it are show to be accurately predicted.
For lithography smaller that 180 nm using 248 nm steppers, phase-shifting lithography is becoming more routine. However, when applied to very small dimensions, OPC effects begin to become pronounced. We have design a new phase- shifting test structure for reticles to address these phase shifting distortions, and report on its use.
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