Inverse Lithography Technology (ILT) is becoming the choice for Optical Proximity Correction (OPC) of advanced technology nodes in IC design and production. Multi-beam mask writers promise significant mask writing time reduction for complex ILT style masks. Before multi-beam mask writers become the main stream working tools in mask production, VSB writers will continue to be the tool of choice to write both curvilinear ILT and Manhattanized ILT masks. To enable VSB mask writers for complex ILT style masks, model-based mask process correction (MB-MPC) is required to do the following: 1). Make reasonable corrections for complex edges for those features that exhibit relatively large deviations from both curvilinear ILT and Manhattanized ILT designs. 2). Control and manage both Edge Placement Errors (EPE) and shot count. 3. Assist in easing the migration to future multi-beam mask writer and serve as an effective backup solution during the transition. In this paper, a solution meeting all those requirements, MB-MPC with GPU acceleration, will be presented. One model calibration per process allows accurate correction regardless of the target mask writer.
The 1Xnm technology node lithography is using SMO-ILT, NTD or more complex pattern. Therefore in mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask feature. One key Technology of mask manufacture is defect verification to use aerial image simulator or other printability simulation. AIMS™ Technology is excellent correlation for the wafer and standards tool for defect verification however it is difficult for verification over hundred numbers or more.
We reported capability of defect verification based on lithography simulation with a SEM system that architecture and software is excellent correlation for simple line and space.[1]
In this paper, we use a SEM system for the next generation combined with a lithography simulation tool for SMO-ILT, NTD and other complex pattern lithography. Furthermore we will use three dimension (3D) lithography simulation based on Multi Vision Metrology SEM system. Finally, we will confirm the performance of the 2D and 3D lithography simulation based on SEM system for a photomask verification.
In a Photomask manufacturing process, mask defect inspection is an increasingly important topic for 193nm optical lithography. Further extension of 193nm optical lithography to the next technology nodes, staying at a maximum numerical aperture (NA) of 1.35, pushes lithography to its utmost limits. This extension from technologies like ILT and SMO requires more complex mask patterns. In mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask features. One of the solutions is lithography simulation like AIMS. An issue with AIMS, however, is the low throughput of measurement, analysis etc.
For the mask making community, maintaining acceptable dose margin has been recognized as a critical
factor in the mask-making process. This is expected to be more critical for 20nm logic node masks and
beyond. To deal with this issue, model-based mask data preparation (MB-MDP) had been presented as a
useful method to obtain sufficient dose margin for these complex masks, in addition to reducing shot
count.
When the MB-MDP approach is applied in the actual mask production, the prediction of the dose margin
and the CD in the finished mask is essential.
This paper describes an improved model of mask process which predicts dose margin and CD in finished
masks better compared with the single Gaussian model presented in previous work. The better predictions
of this simple numerical model are confirmed with simulation by D2S and actual mask written by HOYA
using JEOL JBX-3200MV.
The detection and management of mask defects which are transferred onto wafer becomes more important day by day.
As the photomask patterns becomes smaller and more complicated, using Inverse Lithography Technology (ILT) and
Source Mask Optimization (SMO) with Optical Proximity Correction (OPC).
To evaluate photomask quality, the current method uses aerial imaging by optical inspection tools. This technique at
1Xnm node has a resolution limit because small defects will be difficult to detect.
We already reported the MEEF influence of high-end photomask using wide FOV SEM contour data of "E3630
MVM-SEM®" and lithography simulator "TrueMask® DS" of D2S Inc. in the prior paper [1].
In this paper we evaluate the correlation between our evaluation method and optical inspection tools as ongoing
assessment.
Also in order to reduce the defect classification work, we can compose the 3 Dimensional (3D) information of defects
and can judge whether repairs of defects would be required.
Moreover, we confirm the possibility of wafer plane CD measurement based on the combination between E3630
MVM-SEM® and 3D lithography simulation.
To evaluate photomask quality, the current method uses spatial imaging by optical inspection tools. This technique at 1Xnm node has a resolution limit because small defects will be difficult to extract. To simulate the mask error-enhancement factor (MEEF) influence for aggressive OPC in 1Xnm node, wide FOV contour data and tone information are derived from high precision SEM images. For this purpose we have developed a new contour data extraction algorithm with sub-nanometer accuracy resulting in a wide Field of View (FOV) SEM image: (for example, more than 10um x 10um square). We evaluated MEEF influence of high-end photomask pattern using the wide FOV contour data of "E3630 MVM-SEMTM" and lithography simulator "TrueMaskTM DS" of D2S, Inc. As a result, we can detect the "invisible defect" as the MEEF influence using the wide FOV contour data and lithography simulator.
Dose Margin has always been known to be a critical factor in mask making. This paper describes why the issue is far more critical than ever before with the 20-nm logic node and beyond using ArF Immersion lithography. Model-Based Mask Data Preparation (MB-MDP) had been presented [references] to show shot count improvements for these complex masks. This paper describes that MBMDP also improves the dose margin. The improvement predicted with theoretical simulation with D2S is confirmed by the results of real mask written by JBX-3200MV (JEOL) by HOYA.
KEYWORDS: Photomasks, SRAF, Semiconducting wafers, Scanning electron microscopy, Vestigial sideband modulation, Printing, Data modeling, Manufacturing, Error analysis, System on a chip
In writing 22nm logic contacts with 193nm immersion, curvilinear sub-resolution assist features will be desirable on
masks. Curvilinear sub-resolution assist features are good for high volume chips where the wafer volume outweighs
considerations for mask write times. For those chips, even 40 hour write times are tolerated for mask writing. For
lower-volume production of SOC designs, such write times are economically unacceptable. 8 to 12 hours of write times
are feasible for these designs. Previous papers at 2010 Photomask Japan described model-based mask data preparation
(MB-MDP) techniques using circular apertures on production e-beam writers writing curvilinear ideal ILT patterns that
reduced e-beam write-times by nearly a factor of two over conventional approach writing Manhattanized ILT patterns.
This puts the curvilinear assist features within the realm of high-volume production. However, the write times are still
too long for SOC designs. This paper describes a new technique that reduces mask write time further. Resist-exposed
SEM images will be shown, written by JEOL JBX-3200MV. E-beam shot count comparisons for an ideal ILT mask
pattern will be made with the conventional methods, demonstrating a 44% decrease in blanking time. In addition, a
comparison study is shown indicating that an ideal ILT mask pattern that would take 63 hours with conventional
fracturing can be written in about 14 hours using MB-MDP. AIMS projected images demonstrate the pattern fidelity on
the wafer.
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