As a photomask feature size shrinks, chrome (Cr) dry etching process is one of the most critical steps which define the
performance of critical dimensions (CDs). In consequence, plasma conditions should be maintained stable in a etch
chamber.
In this work, advanced methodologies using plasma monitoring tools are introduced; Optical Emission Spectroscopy
(OES) and the Self-Excited Electron Resonance Spectroscopy (SEERS). After an etch chamber was monitored with these
tools, plasma conditions could be categorized with respect to the three parameters; the spectra, the electron collision rate,
and the electron density distributions.
Finally, it is possible to predict the CD performance of the chamber by checking the specific plasma parameters.
Recent Low k1 era requires aggressive OPC technology with advanced lithography technology. The aggressive OPC
contains the rounded pattern and a lot of assistant pattern which are the main source to increase the shot division. We
have defined the shot complexity, which is defined by the ratio of number of shot between the interested pattern and the
1:1 L/S pattern. Based on shot complexity parameter, we have estimated the writing time as the device node decreases.
We expect that the aggressive OPC and the high dose could generate severely the writing time issue in 32nm node era.
As semiconductor features shrink in size and pitch, the image placement error at photomask has been interested as an
important factor to be reduced. Especially, by the development of double exposure technique (DET) or double
patterning technique (DPT) for sub-45 nm node the image placement error is required to be controlled tightly.
Following ITRS roadmap, when DET or DPT is used the registration for sub-45 nm node is required to be less than 4
nm but this specification still corresponds to the challengeable goal. Among various sources of image placement errors,
here, we focus on the error occurring at patterning process of photomask and discuss its effect on the photomask
overlay. We name the image placement error occurred at patterning process due to e-beam charging effect, absorber
etching effect, and so on as the pattern loading effect. We quantify the amount of pattern loading effect on registration
error, analyze it with the help of simulation and experiment, and discuss the character of each error and correction
method.
According to device shrinkage, pattern load, layout geometry and process induced critical dimension (CD) trend are the
most important factors deciding mask CD uniformity in a mask manufacturing process. The CD distribution is generally
divided by two categories - contribution of pattern load and process induced CD distribution. Etch bias uniformity on a
mask is one of the decisive contributors at a standpoint of pattern load. The signature of etch bias uniformity totally
depends on the pattern load in a mask. In a low pattern load, etch bias uniformity shows a radial signature which is
geometrically distributed regardless of pattern position. In a high pattern load, etch loading effect becomes dominant.
The pattern load, however, can have various definitions, which means that a criterion of low and high pattern load can be
obscure. Specific layouts which have same pattern load over mask but separated region of low and high load pattern in
one mask was designed to specify the effect of pattern load. The radial CD signature is mitigated as pattern load
increases locally. At the same time, etch loading trend grows and dominates total CD uniformity. The radial signature and
etch loading trend have inverse signs on central region which enables to compensate each signature. Therefore a specific
pattern load which can make etch bias uniformity minimized can exist. "Transition pattern load" is detected here. One
can use this specific pattern load as an indicator to specify design categories for mass production. In addition, geometry
of layout should be considered to achieve uniformity number required in 45nm node technology. In high pattern load
over transition pattern load, etch bias shows saddle shape uniformity. Since the saddle shape uniformity is uncorrectable
with conventional etch loading kernel, new correction model should be considered to meet the confined CD specification
in future device nodes.
KEYWORDS: Mask making, Photomasks, Electron beam lithography, Monte Carlo methods, Control systems, Optical proximity correction, Electron beams, Laser scattering, Scattering, Backscatter
The tight MTT control is required for the mask process of sub-50nm design node due to the complex OPC and
insufficient process margin. The MTT below 5nm is already required for the critical layers. Below 4nm is required for
sub-50nm node. In the viewpoint of this requirement, the MTT control is important for the mask fabrication.
According to the shrinking design node, the linearity is the main issue to satisfy MTT required. In the electron beam (ebeam)
lithography, the linearity results are strongly related to the resolution of the mask process. Isolated and dense
patterns have the different linearity behaviors due to the different contrast mainly caused by the backward scattering
contribution and develop process. Because of this reason, the conventional method of proximity effect correction (PEC)
optimization is unlikely to satisfy the MTT requirement. New PEC optimization is necessary for sub-50nm node.
In this report, new PEC optimization method is proposed. This method reduces the PEC error of conventional
optimization method known as a few nm. Because of the linearity, the error of conventional PEC optimization is
amplified according to the shrinking design. Therefore, the PEC error of conventional method is larger than the MTT
requirement for sub-50nm node. This new method is designed to overcome this problem. It takes into account for the
properties of each layer. Based on the analysis of composition of each layer, the different PEC optimization to fit the
each layer and design node is applied. It is able to be applied for the mask fabrication of sub-50nm memory device. The
improvement of MTT is achieved by the reduction of the PEC error with new PEC optimization.
In the photo-lithography process, a mask is one of the most important items because CD error from its imperfection is
transferred to the CD error on the wafer. And the CD error amplification from the mask CD to the wafer CD is denoted
by Mask Error Enhancement Factor (MEEF).
As the device shrinks so fast, MEEF increases conspicuously and massive OPC is necessary to secure the target
pattern CD and the proper process margin on the wafer. Therefore the mask CD uniformity and the just mean-to-target
(MTT) are very important to minimize the CD variation on the wafer level.
In most cases, MTT and CD uniformity for a certain device are not defined exactly. What we know is that the smaller,
the better. Because just small value of MTT and CD uniformity is not the reasonable guideline for the mask fabrication
and inducing high mask cost, defining the logical MTT and CD uniformity prospect for a certain device or layer is very
important.
As the necessity of the low k1 process increases, MTT and CD uniformity specifications become tighter and tighter.
However the proper mask specification for sub-65nm real device has not been defined yet and not been studied
considering the mask fabrication and MEEF.
In this study, MTT and CD uniformity specification of the sub-65nm real device patterns are discussed with respect to
the mask pattern linearity and MEEFs. Mask linearity is one of the typical items for the mask fabrication and strongly
related to MTT and CD uniformity. MTT and CD uniformity tolerance also follows OPC tolerance, and OPC tolerance is
directly related to the pattern layouts and MEEF. To define the mask specification for the sub-65nm device, an example
of mask linearity effect is shown; MEEFs of the critical pattern designs are calculated and compared with each other;
MTT, CD uniformity and MEEF relationship is commented.
In order to make the mask for the photolithography, e-beam direct writing system has been used because e-beam source is most controllable among the direct systems. However, the development of the new e-beam system is scheduled slowly and there is no conspicuous breakthrough technology to improve the quality of the mask comparing to the wafer exposure tool development. Lately, a new laser writing system, Sigma7300 is introduced and shows 200x reduction projection system and very high throughput relative to the e-beam direct writing system. Because it can write the full layout in a mask less than 4
hours, the high reproducibility is expected. Although the current tool is using KrF light source and 0.82NA reduction projection lens column, the higher resolution tool using the ArF light source can be expected in the future. In this paper the possible resolution limit of the Sigma7300 is discussed and the application example for the mask fabrication. To estimate the process capability, the optical simulation is performed and compared with the experimental results. Because its patterned image is not so clear like the e-beam writer, the pattern rounding, the line-end shortening, and the minimum assist feature are discussed with the patterns of the e-beam writer. At the end the important qualities of the mask like defects are compared with the results of the e-beam system.
Downscaling of microchip production technology continually increases requirements to precision of process control, and demands improvement of critical dimension (CD) measurement and control tools. In this paper we discuss the application of in situ method of critical dimension measurement for improvement of photomask development process. For this purpose scatterometry and fitting methods are applied to the CD end point detector system (CD EPD). The CD EPD system is different from the commonly used EPD system, which mainly detects the thickness of remaining resist. Measurement can be performed directly during development process, thus there is an advantage of measurement time decreasing in comparison with the ex situ method. In situ method allows one to control development precisely, and gives possibility to meet the requirements of process control. For the application of scatterometry to the CD measurement, diffraction analysis is carried out by using of rigorous coupled wave analysis (RCWA). We calculate the library of reflected spectra with various CD and heights of the pattern. These spectra are used for fitting with an experimentally measured one to get the CD and height. To increase precision and speed of measurements interpolation of spectra and various fitting methods are used.
Since numerical aperture (NA) becomes greater than 1.0 in immersion lithography, polarization effect will be one of the critical issues in imaging performance. In patterning 40nm or smaller node with 193nm wavelength, transverse magnetic (TM) polarized beam does not contribute to image contrast. Hence most layers will require polarization controlled illumination to prevent the contrast degradation. For this reason, polarization controllability of illumination becomes one of considerable budget of critical dimension (CD) variation. For CD uniformity control of exposure tool and CD budget analysis, it is necessary to measure the polarization performance of illumination system. In-situ or special measurement tools are currently being developed to measure the polarization state of illumination and projection optics. However, each tool maker has its own measurement tool, and consequently in order to compare the polarization performance across different tools, a common measurement method is required. In this paper, a special mask pattern for monitoring polarization state of illumination has been designed. The polarization degrees have been measured for polarized illuminations of 193nm high NA tool. The pattern shape has been designed based on electric magnetic field (EMF) simulation utilizing the diffraction efficiency difference. The actual mask pattern sizes are measured to correct the measurement error. Differences between the EMF simulation and the real exposure results have been investigated for several illumination shapes and for different polarization status.
KEYWORDS: Etching, Critical dimension metrology, Modulation, Dry etching, Photomasks, System on a chip, Backscatter, Data modeling, Electron beams, Electron beam lithography
The correction of fogging effect from an electron beam writer and loading effect from a dry etcher are known as the important factors of non-uniformity of mask CD. To achieve the improvement of CD uniformity, the fogging and loading effect are modeled as a function of pattern density. Taking into account the different behavior of fogging and loading effect on the pattern density, the amount of correction is able to be extracted using the promising modeling and dose modulation technique. In this work, we report the evaluation of correction method with improved model using the linear combination of fogging and loading effect. We compared the various cases and presented the best result of the improvement of CD uniformity.
In the photo-lithography process, a mask is one of the most important items because its imperfection induces the variation of critical dimension (CD) and becomes the source of the CD error on the wafer. The CD error amplification is denoted by using Mask Error Enhancement Factor (MEEF)(1,2) and related to the photo-lithography process. Nowadays MEEF increases conspicuously as the device shrinks so fast. Therefore the mean-to-target (MTT) and the uniformity of the mask CD are very important factors to reduce the effect of high MEEF. In general, the process constant k1 factor has been cited to denote the capability of the photo process for a certain resolution. However MEEF can describe the process difficulty well because it depends on the layout design and the process conditions although the designed patterns have the same design rule.
In this study the MEEFs of sub-80nm DRAM patterns(3) are discussed with the process constant k1, MTT and the mask CD uniformity. And then the results are compared with the simulation and the wafer process data. Considering the mask specification calculated from the wafer specification and MEEF, the photo tool and process upgrade is necessary to reduce MEEF and to have the mask fabrication tolerance.
There are several next generation technologies for high resolution lithography, such as ArF wet immersion, F2, EUV, etc. However, these technologies are very expensive because of projection lens and mask costs. Near-field optics using a solid immersion lens (SIL) can meet the requirement of high resolution in a cost-effective way. In this paper, a very compact and inexpensive high resolution system using a SIL is introduced and preliminary experimental results are presented using a 405nm laser diode system. The SIL is used with a modified conventional inverted microscope. The air gap between the SIL flat bottom surface and the wafer is kept less than 50nm. Optical reflected power from SIL bottom and wafer interface is used to control the gap. A high resolution experiment with 405nm wavelength is discussed.
ArF technology is currently being used for 80nm resolution in the photo-lithography field, and ArF wet immersion technology is expected to be used for high resolution systems down to 50nm. Between ArF wet immersion technology and EUV technology, there is no proper technology that can cover the resolution range from 50nm to 30nm. In this paper, a new lithography technology using a Solid Immersion Lens (SIL) is introduced as an idea for very high resolution, and its resolution achievement is estimated through simulation. SIL technology is a near-field optics technology that achieves high resolution. A SIL is a hemispherical lens, and the incident beam is normal with respect to the surface of the lens. Because a high refractive index material is used for the SIL, very high numerical aperture provides high resolution. The resolution limit is estimated by calculating the vector irradiance inside the thin-film stack composed of the SIL, air gap, photoresist, anti-reflection layer and substrate. Feature size is estimated over reasonable exposure latitude at 20nm depth in the resist. Results show that, using a 365nm wavelength source, 70nm resolution is expected, and 50nm resolution is expected with a 248nm wavelength source. With a shorter wavelength light source and a proper SIL material of high refractive index for the wavelength, higher resolution can be achieved.
The International Technology Roadmap for Semiconductors (ITRS) shows that 45 nm and lower feature sizes are required in lithographic production before the year 2007. Both immersion lithography and EUV lithography can play major roles in realizing this goal. However, a maskless lithography system capable of producing 45 nm features is an attractive option for small-volume semiconductor fabrication, such as with ASIC manufactures. Compared with a conventional lithography system, the maskless feature of the system allows the chip designer to be free of the very expensive process of mask fabrication and to shortcut development time. In this paper, we discuss a new maskless lithography concept employing an array of solid immersion lens (SIL) nano-probes. The nano-probes are efficient near-field transducers. Each transducer is the combination a SIL, a dielectric probe tip and an antenna structure. The nano-probes are fabricated in arrays that dramatically improve throughput. By combining these technologies, it should be possible to fabricate an efficient array of near-field transducers with optical spot dimensions of around 20 nm when illuminated by a 405 nm laser diode source. This paper plans to address, for the first time, the efficient generation of an array of light spots with dimensions of λ/20 or less that couple efficiently into dielectric films, like photoresist.
Stray light is analyzed by scattering range. For the short range, stray light distributes as 1/r4 and comes from aberration. For the mid range and the long range, in the assumption of Gaussian distribution, characteristic scattering length of specific tools is estimated. EOR is proposed which contains information of layer geometry and scattering range characteristic of flare. To minimize CD errors from OPC, flare level and EOR should be considered in the OPC procedure.
The optical resolution of photolithography is limited by the numerical aperture (NA) of lens, wavelength of light source, and k1 factor. Nowadays, the low k1 process is necessary, since the tool development is delayed due to technology difficulties. In order to enhance the process latitude in the low k1 region, special illumination design for specific patterns has been studied. Although illumination optimization is one of the promising solutions to develop the low k1 process, specific design for each pattern has not been applied since the case-by-case illumination design is not easy. The specific layer oriented illumination design is generated using our in-house tool. A DRAM cell is composed of periodic or semi-periodic patterns, and the design of layer specific illumination is made for those patterns with the target of enlarged depth of focus (DOF). It is observed that the DOF and exposure latitude of a DRAM isolated pattern using the optimized illumination are increased in comparison with the conventional annular illumination. It is expected that the lifetime of low-grade exposure tools can be extended by this illumination optimization technique.
Process windows, MEEF (Mask Error Enhancement Factor), flare, aberration effect of the CLM (Cr-less PSM) were measured by the simulations and experiments for the various DRAM cell patterns compared with 6% transmittance HTPSM in the ArF lithography. We designed CLM layouts of sub 100nm node DRAM cells concerning the mask manufacturability, maximizing the NILS (Normalized Image Log Slope) and minimizing the MEEF with a semi-automatic OPC tool. Isolation, line and space and various contact patterns showed increasing process windows compared with HTPSM and this strongly depended on the layout design. Using a 0.75 NA ArF Scanner, CLM showed NILS reduction by about 10% in the presence of lens aberration and flare, which reduced DoF margin by about 0.1~0.2μm depending on the layer. So the critical layers in sub 100 nm node DRAM satisfied 10% of EL (Exposure Latitude) and 0.1 μm of DoF (Depth of Focus) margin. Also 3D mask topographic effect of CLM in the specific layer was discussed.
Layer specific illumination has merits of enhancement of resolution, widening DOF and image fitness. For dense patterns like DRAM cell, layer specific illumination is a major candidate to drive low k1 lithography. To find out the best illumination for a specific pattern, diffracted image of the pattern and the ratio of captured first order to 0th order diffracted beam should be considered. By spectrum analysis, the best illumination is obtained for simple patterns like dense lines, brick wall, and dense contacts. In this paper, the procedure of obtaining the best illumination for specific patterns is presented. Comparing general illuminations such as annular, the resultant illumination is proved to have wider DOF and enhancement of resolution. The best illumination can also be found by Monte Carlo simulation. For simple one-dimensional case, its validity is proved. From the exposure results, wide DOF and enhancement of resolution is confirmed.
As the design rule shrinks, intra-field CD control becomes more difficult. Flare induced by lens contamination is one of CD variation sources across the exposed field and its distributions are different from tool to tool. To use the exposure tool with the contaminated lens, CD correction method is to be specified to improve the wafer CD uniformity. In this paper, the local flare values are measured using dose-to-clear method and CD measurement method in order to confirm the exposure tool condition. Then we design a mask whose transmittance is controlled locally for CD uniformity enhancement. The mask has several phase-out holes in the quartz side. By distributing the holes with respect to the local area flare, we can make the intensity distribution opposite to the lens local flare.
Improvement of process latitude is tested in typical DRAM patterns by using the optimized illumination for each layer pattern. The optimized illumination for a specific layer is generated by modifying the Fourier transformed image of the layer and by using in-house illumination optimization program, which can simulate the maximum process latitude. These illumination shapes are compared with each other, and it is confirmed that both illuminations are similar in shape. The typical DRAM patterns are exposed using the optimized illuminations, and the process latitude is compared with typical annular illumination cases. It is certain that the process latitude using the optimized illumination is greater than the high sigma annular illumination. By using the optimized illumination, the enlarged process latitude makes it possible to use lower grade tools for a critical layer. It is expected that the lifetime of low-grade exposure tools can be extended by this illumination optimization technique.
Process windows, MEEF (Mask Error Enhancement Factor), flare, aberration effect of the CLM (Cr-less PSM) were measured by the simulations and experiments for the various DRAM cell patterns compared with 6% transmittance HTPSM in the ArF lithography. We designed CLM layouts of sub 100nm node DRAM cells concerning the mask manufacturability, maximizing the NILS (Normalized Image Log Slope) and minimizing the MEEF with a semi-automatic OPC tool. Isolation, line and space and various contact patterns showed increasing process windows compared with HTPSM and this strongly depended on the layout design. Using 0.75 NA ArF Scanner, CLM showed NILS reduction by about 10% in the presence of lens aberration and flare, which reduced DoF margin by about 0.1~0.2 μm depending on the layer. So the critical layers in sub 100 nm node DRAM satisified 10% of EL (Exposure Latitude) and 0.4 μm of DoF (Depth of Focus) margin.
It is well known that flare, which increases the background intensity and loses the image contrast, degrades the pattern fidelity and CD uniformity. Usually there is little mid and long-range flare at the initial exposure tool introduction except the short-range flare, so called, aberration. However, flare effect is observed in used exposure tools. To estimate the influence of flare, both lens quality of the exposure tool and mask pattern layout with various open ratios are important parameters to be considered. So it is very crucial to make a standard mask layout to measure the flare value as a tool specification. So far, CD variation of the long-range flare has been measured and reported. The long-range flare includes the average influence of the short and mid-range flare and affects more than several hundred- micron distances. Recently it is observed that lens contamination is a dominant component among sources of flare and induced by the pattern layout with its different open ratio. Being contaminated, the lens malfunctions with various types of scattering sources. These scattering sources make the mid and long range flare. This type of flare source has time dependence. If there are proper monitoring methods for the flare measurement, it is possible to maintain the lens quality within the limit of mid range flare. In addition, matching the flare value to CD distribution is not easy because there is no standard measurement method to distinguish the short and mid-range flare from the long-range one. In this paper a LOcal Area Flare Evaluation Reticle (LOAFER) method is suggested. The LOAFER is designed to measure the local area flare of the lens, that is, the short and mid-range flare and the local flare distribution of the exposure tool lens can be characterized. Then matching the result to the real device pattern will be introduced.
It is expected that ArF lithography will be introduced for device manufacturing for sub-100 nm nodes, as high NA ArF step and scan systems (NA=0.75) become available. We previously reported on a platform, based on a vinyl ether- maleic anhydride (VEMA) alternating polymer system. This platform demonstrated both good resolution and high dry etch resistance in comparison to other platforms based on acrylate and cyclic-olefin-maleic anhydride (COMA) polymer systems. The VEMA platform has been continuously improved to meet the increasing requirements, such as resolution, depth of focus (DOF) iso-dense bias, and post-etch roughness for real device manufacturing. This VEMA system is being implemented for sub-100 nm device with high NA (NA=0.75) ArF exposure systems. In this paper, recent experimental results are reviewed.
The trend of critical dimension (CD) asymmetry due to coma aberration of exposure tool and the effectiveness of assist pattern (AP) to minimize the CD asymmetry are investigated in line and space patterns by simulation and experiment. The optimum space of AP form main bar pattern to correct the CD asymmetry is about 0.3-0.4 um and seems to be insensitive to the target CD of main bar, NA and degree of coherence of lithography tool, and AP size. The results, in case of the application of AP with optical proximity correction rules achieved by simulation and experiment to logic device with 0.18 micrometers gate length, show the CD asymmetry of metrology error level and about 50 percent in-field CD uniformity improvement, as compared with those obtained before Ap application. Therefore, it is evident that the use of AP is very effective and useful to correct the CD uniformity and the CD asymmetry simultaneously.
The acceleration of the design rule shrinkage and delayed ArF technology currently put pressure upon KrF technology for device development difficulties, so that the extension of KrF lithography to 220nm pitch patterning is under test carefully without using ArF technology.
Optical lithography is the most fundamental technology for the development of 1 Gbit DRAM device. As a current status, KrF lithography is a powerful candidate for 180 nm generation because of relatively high cost of ArF lithography and its untimely applicability to mass production. In this paper, we showed that the optimized OAI system with large quadrupole offset and small opening could improve the resolution and process margin in the photo process of 180 nm level DRAM devices. We also demonstrated what the effect of CD amplification factor ((alpha) ) was related to the mask CD control and resist tone under the optimized OAI system. The result shows that the combination of the optimized OAI system and positive tone resist can give rise to the reduction of (alpha) from 4.5 to almost 1 and provide a reasonable margin.
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