Mr. Douglas J. Van Den Broeke Profile

Douglas J. Van Den Broeke

Senior Director at ASML

SPIE Involvement:

Author

Publications (73)

Proceedings Article | 27 May 2010 Paper

Paper

Performance and stability of mask process correction for EBM-7000

Yasuko Saito, George Chen, Jen-Shiang Wang, Shufeng Bai, Rafael Howell, Jiangwei Li, Jun Tao, Doug VanDenBroeke, Jim Wiley, Tadahiro Takigawa, Takayuki Ohnishi, Takashi Kamikubo, Shigehiro Hara, Hirohito Anze, Yoshiaki Hattori, Shuichi Tamamushi

Proceedings Volume 7748, 774814 (2010) https://doi.org/10.1117/12.867969

KEYWORDS: Photomasks, Critical dimension metrology, Extreme ultraviolet, Manufacturing, Metrology, Time metrology, EUV optics, Computational lithography, Scattering, Optical lithography

Read Abstract +

Proceedings Article | 4 April 2007 Paper

Paper

Quantification of two-dimensional structures generalized for OPC model verification

Xuelong Shi, J. Fung Chen, Doug Van Den Broeke, Stephen Hsu, Michael Hsu

Proceedings Volume 6518, 65180A (2007) https://doi.org/10.1117/12.713867

KEYWORDS: Calibration, Optical proximity correction, Data modeling, Photomasks, Imaging systems, Mathematical modeling, Design for manufacturing, Statistical modeling, Lithography, Image processing

Read Abstract +

Model based optical proximity correction (OPC) today has become a necessity in advanced lithography for 65nm and 45nm design rules in order to achieve production-worthy pattern fidelity. The typical practice is to use a limited set of test structures to calibrate and determine the OPC model parameters. The guide for the selection of test structures for OPC model calibration has been mainly relied on experience and physical intuition. To date, there is no known quantification methodology to ensure that the calibrated model from a limited set of test structures can reliably "cover" a full-chip OPC application without any ambiguity under a known set of design rule constraints. Doubts from this ambiguity demand an extra design for manufacturing (DFM) verification step in addition to the already lengthy OPC application process. This is since semiconductor manufacturing requires that the post-OPC mask data contains no errors, or at least no catastrophic errors induced by OPC treatment, e.g., bridging or short. However, such DFM verification tools are again based on a perilous assumption that either one can use the same or yet another "calibrated" model from a limited set of test structures to check the OPC treated full-chip data for all possible trouble spots. In reality, a "calibrated" model may never be able to apply adequately to those of random two-dimensional (2-D) pattern structures on a full-chip that are lithographically unrelated to the limited set of test structures used for the model calibration. To ensure a more comprehensive coverage of the OPC model, we need a methodology that can quantify generalized 2-D test structures suitable for model calibration. In this paper, we propose a method to quantify generalized, 2-D patterns by representing them in "imaging signal space". The method that translates geometrical design rules into the boundary in "imaging signal space" is elaborated. We propose several critical quantities to characterize OPC model on a quantitative foundation to assess model from a statistical point of view.

Proceedings Article | 20 October 2006 Paper

Paper

Application challenges with double patterning technology (DPT) beyond 45 nm

Jungchul Park, Stephen Hsu, Douglas Van Den Broeke, J. Fung Chen, Mircea Dusa, Robert Socha, Jo Finders, Bert Vleeming, Anton van Oosten, Peter Nikolsky, Vincent Wiaux, Eric Hendrickx, Joost Bekaert, Geert Vandenberghe

Proceedings Volume 6349, 634922 (2006) https://doi.org/10.1117/12.692921

KEYWORDS: Photomasks, Optical lithography, Optical proximity correction, Double patterning technology, Etching, Model-based design, Printing, Manufacturing, Critical dimension metrology, Photoresist processing

Read Abstract +

Proceedings Article | 20 May 2006 Paper

Paper

Manufacturing implementation of IML technology for 45 nm node contact masks

Douglas Van Den Broeke, Michael Hsu, J. Fung Chen, Stephen Hsu, Uwe Hollerbach, Tom Laidig

Proceedings Volume 6283, 62831C (2006) https://doi.org/10.1117/12.681811

KEYWORDS: Reticles, Printing, Resolution enhancement technologies, Manufacturing, Algorithm development, Photomasks, Scattering, Binary data, Optical lithography, Detection and tracking algorithms

Read Abstract +

For advance semiconductor manufacturing, patterning contact and via mask layers continue to be major challenge. As a result, RET's beyond the current standard 6% attPSM technology are being pursued with a goal of reducing the k₁ for hole patterning to the range of 0.35 - 0.40. IML Technology has shown promising results as a possible solution which employs strong off axis illumination (OAI) to achieve the resolution for the dense pitch contacts and the use of sub-resolution scattering bars (SB) for the semi dense to isolated contacts. At the 45nm node, placing SB by simply applying a set of rules is not sufficient for deriving the correct assist feature placements for the entire range of pitches and for the complex, randomly placed contacts that occur in actual device patterns. IML Technology utilizes modeling to locate where SB should be placed and in the case of high transmission ternary PSM (HTPSM) and CPL, defines the phase of the SB relative to the contacts being imaged. To generate such reticle designs, highly complex interference maps are calculated and from this optical interference behavior, the reticle pattern is derived. Previously, the reticle pattern derived in such a manner was extremely complex raising a question as to how feasible such an approach would be in a manufacturing environment. New algorithms which simplify the mask pattern while maintaining the resolution enhancement capability of IML have been developed. The objective of this work is to demonstrate a manufacturing methodology that utilizes IML Technology and is capable of meeting the requirements for the 45nm node designs. We will explore the application of this method 6% attPSM and CPL reticle designs which containing contact patterns that are representative of production devices. To define the SB for what are effectively randomly placed contacts over a wide range of pitches from dense to isolated, IML Technology is used. This modeling algorithm is based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern. This technique provides a model-based approach for placing all types of assist features on both clear field and dark field patterns for the purpose of enhancing the printing resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. By implementing newly developed algorithms, simplified reticle patterns are generated which maintain the optimum SB placements determined by the IML process.

Proceedings Article | 20 May 2006 Paper

Paper

RET masks for patterning 45nm node contact hole using ArF immersion lithography

Michael Hsu, J. Fung Chen, Doug Van Den Broeke, Shih En Tszng, Jason Shieh, Stephen Hsu, Xuelong Shi

Proceedings Volume 6283, 628317 (2006) https://doi.org/10.1117/12.681868

KEYWORDS: Photomasks, Resolution enhancement technologies, Printing, Etching, Optical proximity correction, Optical lithography, Imaging systems, Mask making, Quartz, Semiconducting wafers

Read Abstract +

Immersion exposure system with the numerical aperture (NA) greater than unity effectively extends the printing resolution limit without the need of shrinking the exposure wavelength. From the perspective of imaging contact hole mask, we are convinced that a mature ArF immersion exposure system will be able to meet 45nm node manufacturing requirement. However, from a full-chip mask data processing point of view, a more challenging question could be: how to ensure the intended RET mask to best achieve a production worthy solution? At 45nm, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For full-chip, especially for contact hole mask, we need a robust RET mask strategy to ensure sufficient CD control. A production-worthy RET mask technology should have good imaging performance with advanced exposure system; and, it should base on currently available mask blank material and be compatible with the existing mask making process. In this work, we propose a new type of contact hole RET masks that is capable of 45nm node full-chip manufacturing. Three types of potential RET masks are studied. The 1st type is the conventional 6% attenuated PSM (attPSM) with 0-phase Scattering Bars (SB). The 2nd type is to use CPL mask with both 0- and π-phase SB, and their relative placements are based on interference mapping lithography (IML) under optimized illumination. The 3rd type, here named as 6% CPL, can be thought of as a CPL mask type with 6% transmission on the background but with π-phase SB only. Of those three RET masks, 6% CPL mask has the best performance for printing 45nm contact and via masks. To implement 6% CPL for contact and via mask design, we study several critical process steps starting from the illumination optimization, model-based SB OPC, 3D mask effect, quartz etch depth optimization, side-lobe printability verification, and then to the mask making flow. Additionally, we investigate printability for through-pitch contact array, and random contact design. To characterize the printing performance, we use MEEF, and process window (PW) to analyze the simulation data. We conclude that the 45nm node contact hole imaging is well within reach using a mature ArF immersion exposure tool with a robust and well integrated RET mask scheme.

Proceedings Article | 20 May 2006 Paper

Paper

Unifying the RET design flow with portable modeling information

Jason Sweis, Wolf Staud, Bob Naber, Tom Laidig, Doug Van Denbroeke

Proceedings Volume 6283, 62832V (2006) https://doi.org/10.1117/12.681812

KEYWORDS: Resolution enhancement technologies, Process modeling, Data modeling, Lithography, Calibration, Manufacturing, Optical proximity correction, Photomasks, Design for manufacturing, Scanners

Read Abstract +

Proceedings Article | 20 May 2006 Paper

Paper

Dark field double dipole lithography (DDL) for 45 nm node and beyond

Stephen Hsu, Martin Burkhardt, Jungchul Park, Douglas Van Den Broeke, J. Fung Chen

Proceedings Volume 6283, 62830U (2006) https://doi.org/10.1117/12.681854

KEYWORDS: Photomasks, Nanoimprint lithography, Diffraction, Lithography, Printing, Optical proximity correction, Resolution enhancement technologies, Optical lithography, Manufacturing, Metals

Read Abstract +

Proceedings Article | 20 May 2006 Paper

Paper

A single-exposure approach for patterning 45nm flash/DRAM contact hole mask

Ting Chen, Doug Van Den Broeke, Edita Tejnil, Stephen Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep De Vocht, Noel Corcoran, J. Fung Chen, Eddy van der Heijden, Jo Finders, Andre Engelen, Robert Socha

Proceedings Volume 6283, 62831A (2006) https://doi.org/10.1117/12.681873

KEYWORDS: Optical proximity correction, Electroluminescence, Optical lithography, Printing, Photomasks, Lithographic illumination, Semiconducting wafers, Diffractive optical elements, Manufacturing, Nanoimprint lithography

Read Abstract +

Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k₁ conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k₁<0.31, both resolution and imaging contrast can become severely limited at NA<0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond. In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IML^TM technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150nm to >250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners. Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.

Proceedings Article | 15 March 2006 Paper

Paper

Patterning 45nm flash/DRAM contact hole mask with hyper-NA immersion lithography and optimized illumination

Ting Chen, Doug Van Den Broeke, Stephen Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Noel Corcoran, Fung Chen, Eddy van der Heijden, Jo Finders, Andre Engelen, Robert Socha

Proceedings Volume 6154, 61541O (2006) https://doi.org/10.1117/12.656982

KEYWORDS: Electroluminescence, Semiconducting wafers, Photomasks, Diffractive optical elements, Optical lithography, Printing, Nanoimprint lithography, Optical proximity correction, Polarization, Finite element methods

Read Abstract +

Patterning contact-hole mask for Flash/DRAM is probably one of the most challenging tasks for design rule below 50nm due to the extreme low-k₁ printing conditions common in the memory designs. When combined with optical proximity corrections (OPC) to the mask, using optimized illumination has become a viable part of the production lithography process for 65nm node. At k₁<0.31, both resolution and imaging contrast can become severely limited by some of the current imaging tools with NA<0.85 and using standard illumination sources. Hyper-NA immersion lithography increases the process latitude and is therefore expected to become more indispensable for manufacturing under extreme low-k₁ conditions for sub-50nm design rule. In this work, we describe our process optimization approach for patterning Flash/DRAM contact-hole patterns with 130nm, 120nm, and smaller minimum pitch design rules. Here we use 6% attPSM mask for simulation and actual exposure in ASML XT 1400i (NA=0.93) and 1700i (NA=1.2) respectively. We begin with the illumination source optimization using full vector high-NA calculation (VHNA) with production resist stack and all manufacturability requirements for the source shaping diffractive optical element (DOE) are accounted for during the source optimization. Using the optimized source, IML^TM technology based scattering bars (SB) placement together with model based OPC (MOPC) are applied to the original contact-hole design. In-focus printing and process latitude simulations are used to gauge the performance and manufacturability of the final optimized process, which includes the optimized mask, optimized source and required imaging settings. Our results show that for the 130nm pitch Flash contact-hole patterns, on ASML XT 1400i at NA=0.93, both optimized illumination source and immersion lithography are necessary in order to achieve manufacturability. The worst-case depth of focus (DOF) before SB and MOPC is 100-130nm at 6% EL, without common process window (PW) and with MOPC, the worst-case DOF is >200nm at 6% EL. The latter is in excellent agreement with the wafer results from ASML XT 1400i, and the predicated CDs match well with the measured at isolated, medium and dense pitch contact-holes to within 5nm. For the 120nm pitch Flash contact patterns, ASML XT 1700i at NA=1.2 must be used, together with optimized illumination source, to achieve the same or better process latitude (worst-case DOF at 6% EL), and for the Flash pattern used, further enhancements of >20% in DOF @ 6% EL using Y linear polarization can be achieved, before SB and MOPC. With preliminary SB and MOPC, the worst-case DOF @ 6% EL is increased from 100nm to 150nm and with common PW for all critical CDs, from isolated to dense contact-holes. Two examples of customized polarizations are considered in the above simulations to demonstrate the effects of polarizations on imaging and process latitude for pattern specific contact-holes. The pros and cons of the current patterning solution are discussed and compared with alternatives.

Proceedings Article | 9 November 2005 Paper

Paper

Implementation of random contact hole design with CPL mask by using IML technology

Michael Hsu, Doug Van Den Broeke, Stephen Hsu, J. Fung Chen, Xuelong Shi, Noel Corcoran, Linda Yu

Proceedings Volume 5992, 599237 (2005) https://doi.org/10.1117/12.633286

KEYWORDS: Photomasks, Optical proximity correction, Semiconducting wafers, Model-based design, 3D modeling, Printing, Resolution enhancement technologies, Optical lithography, Lithographic illumination, Lithography

Read Abstract +

Proceedings Article | 8 November 2005 Paper

Paper

Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations

Ting Chen, Doug Van Den Broeke, Stephen Hsu, Michael Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Fung Chen, Robert Socha, JungChul Park, Keith Gronlund

Proceedings Volume 5992, 599239 (2005) https://doi.org/10.1117/12.633465

KEYWORDS: Electroluminescence, Printing, Nanoimprint lithography, Lithographic illumination, Cerium, Fiber optic illuminators, Manufacturing, Optical proximity correction, Optical lithography, Photomasks

Read Abstract +

Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k₁, e.g. k₁<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k₁<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.

Proceedings Article | 5 November 2005 Paper

Paper

Double exposure technique for 45nm node and beyond

Stephen Hsu, Jungchul Park, Douglas Van Den Broeke, J. Fung Chen

Proceedings Volume 5992, 59921Q (2005) https://doi.org/10.1117/12.633231

KEYWORDS: Photomasks, Polarization, Lithography, Printing, Dysprosium, Reticles, Optical proximity correction, Semiconducting wafers, Double patterning technology, Nanoimprint lithography

Read Abstract +

The technical challenges in using F2 lithography for the 45nm node, along with the insurmountable difficulties in EUV lithography, has driven the semiconductor chipmaker into the low k₁ lithography era under the pressure of ever decreasing feature sizes. Extending lithography towards lower k₁ puts heavy demand on the resolution enhancement technique (RET), exposure tool, and the need for litho friendly design. Hyper numerical aperture (NA) exposure tools, immersion, and double exposure techniques (DET's) are the promising methods to extend lithography manufacturing to the 45nm node at k₁ factors below 0.3. Scattering bars (SB's) have become an integral part of the lithography process as chipmakers move to production at ever lower k₁ factors. To achieve better critical dimension (CD) control, polarization is applied to enhance the image contrast in the preferential imaging orientation, which increases the risk of SB printability. The optimum SB width is approximately (0.20 ~ 0.25)*(λ/NA). When the SB width becomes less than the exposure wavelength on the 4X mask, Kirchhoff's scalar theory under predicts the SB intensity. The optical weighting factor of the SB increases (Figure 1b) and the SB's become more susceptible to printing. Meanwhile, under hyper NA conditions, the effectiveness of "subresolution" SB's is significantly diminished. A full-sized scattering bars (FSB) scheme becomes necessary. Double exposure methods, such as using ternary 6% attenuated PSM (attPSM) for DDL, are good imaging solutions that can reach and likely go beyond the 45nm node. Today DDL, using binary chrome masks, is capable of printing 65 nm device patterns. In this work, we investigate the use of DET with 6% attPSM masks to target 45nm node device. The SB scalability and printability issues can be taken cared of by using "mutual trimming", i.e., with the combined energy from the two exposures. In this study, we share our findings of using DET to pattern a 45nm node device design with polarization and immersion. We also explore other double patterning methods which in addition to having two exposures, incorporates double coat/developing/etch processing to break the 0.25 k₁ barrier.

Proceedings Article | 5 November 2005 Paper

Paper

Compensating mask topography effects in CPL through-pitch solutions toward the 45nm node

Joost Bekaert, Vicky Philipsen, Geert Vandenberghe, Doug van den Broeke, Wolfgang Degel, Axel Zibold

Proceedings Volume 5992, 59921O (2005) https://doi.org/10.1117/12.632084

KEYWORDS: Etching, Photomasks, Reticles, Electroluminescence, Semiconducting wafers, Lithography, Phase shifts, Diffraction, Immersion lithography, Scanners

Read Abstract +

Proceedings Article | 28 June 2005 Paper

Paper

Feasibility study of double exposure lithography for 65nm and 45nm node

Stephen Hsu, Douglas Van Den Broeke, J. Chen, Jungchul Park, Michael Hsu

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617451

KEYWORDS: Photomasks, Polarization, Printing, Lithography, Dysprosium, Reticles, Binary data, Semiconducting wafers, Manufacturing, Diffraction

Read Abstract +

There are many challenges ahead to use ArF for printing 45nm node device. High numerical aperture (NA) exposure tool and double exposure technique (DET) are the promising methods to extend ArF lithography manufacturing to 45nm node at k₁ factor below 0.35. Scattering bars (SB) have already become indispensable as chipmakers move to production in low k₁ factor. The optimum SB width is approximately (0.20 to 0.25)*(λ/NA). When SB width becomes less than the exposure wavelength, the Kirchhoff scalar theory is no longer accurate. When the optical weight of the SB increases, they become more easily printable. In order to ensure more robust lithography, both foundry and IDM prefer to choose higher NA exposure tool to maintain higher k₁ (>0.35). The chipmaker is currently using 0.85 NA, ArF, scanners for 65nm development and early device qualification. With immersion, the NA can be greater than 1.0. Under such a hyper NA (>1) condition, SB scalability and optical weight control are becoming even more challenging. Double exposure methods using either ternary 6% attenuated PSM (AttPSM) for DDL, or applying CPL mask with DDL, are good imaging solutions that can go beyond 45nm node. Today DDL with binary chrome mask is capable of printing 65 nm device patterns. Transmission tuning combined with OAI can achieve best-known imaging contrast for low k₁ lithography. In this work, we investigate the use of DDL with 6% ternary AttPSM to target 45nm node features. SB scalability issue can be addressed in both schemes since the SB can be exposed away using the combined dose from double exposures. Dipole with linearly polarized light can significantly improve the image contrast. The key to take advantage of polarization is to convert the layout into the corresponding x y patterns. We have developed model-based layout conversion method to generate both 6% AttPSM that can consider polarization effect. In this study, we share our initial findings through simulation and to report the initial binary mask printing result of DDL with linearly polarization.

Proceedings Article | 28 June 2005 Paper

Paper

Precision process calibration and CD predictions for low-k1 lithography

Ting Chen, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Fung Chen, Linda Yu, Stephen Hsu, Doug van den Broeke, Robert Socha, Jungchul Park, Keith Gronlund, Todd Davis, Vince Plachecki, Tom Harris, Steve Hansen, Chuck Lambson

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617218

KEYWORDS: Calibration, 3D modeling, Process modeling, Data modeling, Diffusion, Photoresist processing, Lithography, Critical dimension metrology, Photomasks, Semiconducting wafers

Read Abstract +

Leading resist calibration for sub-0.3 k₁ lithography demands accuracy <2nm for CD through pitch. An accurately calibrated resist process is the prerequisite for establishing production-worthy manufacturing under extreme low k₁. From an integrated imaging point of view, the following key components must be simultaneously considered during the calibration - high numerical aperture (NA>0.8) imaging characteristics, customized illuminations (measured vs. modeled pupil profiles), resolution enhancement technology (RET) mask with OPC, reticle metrology, and resist thin film substrate. For imaging at NA approaching unity, polarized illumination can impact significantly the contrast formation in the resist film stack, and therefore it is an important factor to consider in the CD-based resist calibration. For aggressive DRAM memory core designs at k₁<0.3, pattern-specific illumination optimization has proven to be critical for achieving the required imaging performance. Various optimization techniques from source profile optimization with fixed mask design to the combined source and mask optimization have been considered for customer designs and available imaging capabilities. For successful low-k₁ process development, verification of the optimization results can only be made with a sufficiently tunable resist model that can predicate the wafer printing accurately under various optimized process settings. We have developed, for resist patterning under aggressive low-k₁ conditions, a novel 3D diffusion model equipped with double-Gaussian convolution in each dimension. Resist calibration with the new diffusion model has demonstrated a fitness and CD predication accuracy that rival or outperform the traditional 3D physical resist models. In this work, we describe our empirical approach to achieving the nm-scale precision for advanced lithography process calibrations, using either measured 1D CD through-pitch or 2D memory core patterns. We show that for ArF imaging, the current resist development and diffusion modeling can readily achieve ~1-2nm max CD errors for common 1D through-pitch and aggressive 2D memory core resist patterns. Sensitivities of the calibrated models to various process parameters are analyzed, including the comparison between the measured and modeled (Gaussian or GRAIL) pupil profiles. We also report our preliminary calibration results under selected polarized illumination conditions.

Proceedings Article | 28 June 2005 Paper

Paper

Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology

Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt Wampler, Uwe Hollerbach, Robert Socha, J. Chen, Stephen Hsu, Xuelong Shi

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617165

KEYWORDS: Photomasks, Optical proximity correction, Model-based design, Performance modeling, Manufacturing, Scattering, Lithography, Semiconducting wafers, Printing, Diffractive optical elements

Read Abstract +

Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁ lithography manufacturing. The manufacturing implementation of SB so far has been mainly based on rule-based approach. While this has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML Technology from ASML MaskTools. In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Proceedings Article | 28 June 2005 Paper

Paper

RET masks for the final frontier of optical lithography

J. Chen, Douglas van den Broeke, Stephen Hsu, Michael Hsu, Tom Laidig, Xuelong Shi, Ting Chen, Robert Socha, Uwe Hollerbach, Kurt Wampler, Jungchul Park, Sangbong Park, Keith Gronlund

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617430

KEYWORDS: Photomasks, Printing, Optical proximity correction, Lithography, Resolution enhancement technologies, Optical lithography, Manufacturing, Calibration, Optics manufacturing, Model-based design

Read Abstract +

With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Today’s advanced lithography for DRAM/Flash is operating at k₁ close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k₁=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k₁ lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k₁ factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OAI). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k₁ barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution

Proceedings Article | 12 May 2005 Paper

Paper

Applications of CPL mask technology for sub-65nm gate imaging

Lloyd Litt, Will Conley, Wei Wu, Richie Peters, Colita Parker, Jonathan Cobb, Bryan Kasprowicz, Doug van den Broeke, J. Park, Ramkumar Karur-Shanmugam

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600912

KEYWORDS: Reticles, Photomasks, Manufacturing, Inspection, Critical dimension metrology, Semiconducting wafers, Optical proximity correction, Lithography, Logic, Etching

Read Abstract +

The requirements for critical dimension control on gate layer for high performance products are increasingly demanding. Phase shift techniques provide aerial image enhancement, which can translate into improved process window performance and greater critical dimension (CD) control if properly applied. Unfortunately, the application of hard shifter technology to production requires significant effort in layout and optical proximity correction (OPC) application. Chromeless Phase Lithography (CPL) has several advantages over complementary phase mask (c:PSM) such as use of a single mask, and lack of phase placement 'coloring' conflicts and phase imbalance issues. CPL does have implementation issues that must be resolved before it can be used in full-scale production. CPL mask designs can be approached by separating features into three zones based on several parameters, including size relative to the lithographic resolution of the stepper lens, wavelength, and illumination conditions defined. Features are placed into buckets for different treatment zones. Zone 1 features are constructed with 100% transmission phase shifted structures and Zone 3 features are chrome (binary) structures. Features that fall into Zone 2, which are too wide to be defined using the 100% transmission of pure CPL (i.e. have negative mask error factor, MEEF) are the most troublesome and can be approached in several ways. The authors have investigated the application of zebra structures of various sizes to product type layouts. Previous work to investigate CPL using test structures set the groundwork for the more difficult task of applying CPL rules to actual random logic design layouts, which include many zone transitions. Mask making limitations have been identified that play a role in the zebra sizing that can be applied to Zone 2 features. The elimination of Zone 2 regions was also investigated in an effort to simplify the application of CPL and improve manufacturability of reticle through data enhancements.

Proceedings Article | 12 May 2005 Paper

Paper

The impact of illumination on feature fidelity for CPL mask technology

Jan Kuijten, Arjan Verhappen, Will Conley, Stephan van de Goor, Lloyd Litt, Wei Wu, Kevin Lucas, Bernie Roman, Bryan Kasprowicz, Chris Progler, Robert Socha, Doug van den Broeke, Kurt Wampler, Tom Laidig, Stephen Hsu

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.605481

KEYWORDS: Chromium, Photomasks, Nanoimprint lithography, Phase shifts, Resolution enhancement technologies, Optical proximity correction, Mask making, Semiconductors, Photoresist materials, Manufacturing

Read Abstract +

Proceedings Article | 12 May 2005 Paper

Paper

Lithography manufacturing implementation for 65 nm and 45 nm nodes with model-based scattering bars using IML technology

Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt Wampler, Uwe Hollerbach, Robert Socha, J. Chen, Stephen Hsu, Xuelong Shi

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.598589

KEYWORDS: Photomasks, Optical proximity correction, Model-based design, Manufacturing, Lithography, Performance modeling, Scattering, Printing, Diffractive optical elements, Design for manufacturing

Read Abstract +

Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁lithography manufacturing. ⁽¹⁾ The manufacturing implementation of SB so far has been mainly based on rule-based approach. While thiis has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML. Technology from ASML MaskTools.^(2,3) In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible for MaskWeaver to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

SPIE Journal Paper | 1 April 2005

Extending aggressive low-k1 design rule requirements for 90 and 65 nm nodes via simultaneous optimization of numerical aperture, illumination and optical proximity correction

Sabita Roy, Douglas Van Den Broeke, J. Fung Chen, Armin Liebchen, Ting Chen, Stephen Hsu, Xuelong Shi, Robert Socha

JM3, Vol. 4, Issue 02, 023003, (April 2005) https://doi.org/10.1117/12.10.1117/1.1898244

KEYWORDS: Optical proximity correction, Diffractive optical elements, Critical dimension metrology, Calibration, Photomasks, Stanford Linear Collider, Fiber optic illuminators, Lithography, Printing, Logic

Read Abstract +

Proceedings Article | 6 December 2004 Paper

Paper

Double dipole lithography for 65-nm node and beyond: defect sensitivity characterization and reticle inspection

Stephen Hsu, Tsann-bin Chu, Douglas Van Den Broeke, J. Fung Chen, Michael Hsu, Noel Corcoran, William Volk, Wayne Ruch, Jean-Paul Sier, Carl Hess, Benjamin Lin, Chun-Chi Yu, George Huang

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569367

KEYWORDS: Inspection, Reticles, Photomasks, Lithography, Resolution enhancement technologies, Defect inspection, Semiconducting wafers, Model-based design, Optical proximity correction, Scattering

Read Abstract +

Proceedings Article | 6 December 2004 Paper

Paper

Mask topography effect in chromeless phase lithography

Vicky Philipsen, Joost Bekaert, Geert Vandenberghe, Rik Jonckheere, Douglas Van Den Broeke, Robert Socha

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568694

KEYWORDS: Photomasks, Etching, Chromium, Quartz, Lithography, Semiconducting wafers, Lithographic illumination, 193nm lithography, Reticles, Mask making

Read Abstract +

Proceedings Article | 6 December 2004 Paper

Paper

Chromeless phase lithography reticle defect inspection challenges and solutions

Larry Zurbrick, Anthony Vacca, Byran Reese, Douglas Van Den Broeke, Stephen Hsu, Darren Taylor, Bryan Kasprowicz

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569287

KEYWORDS: Inspection, Reticles, Manufacturing, Photomasks, Etching, Defect detection, Lithography, Quartz, Sensors, Resolution enhancement technologies

Read Abstract +

Proceedings Article | 6 December 2004 Paper

Paper

Full-chip manufacturing reliability check and correction (MRC2): a first step toward design for manufacturability with low k1 lithography

Michael Hsu, Tom Laidig, Kurt Wampler, Stephen Hsu, Xuelong Shi, J. Fung Chen, Douglas Van Den Broeke

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568670

KEYWORDS: Photomasks, Manufacturing, Critical dimension metrology, Resolution enhancement technologies, Printing, Computer aided design, Lithography, Semiconducting wafers, Design for manufacturing, Reliability

Read Abstract +

Proceedings Article | 6 December 2004 Paper

Paper

Contact and via hole mask design optimization for 65-nm technology node

Douglas Van Den Broeke, Xuelong Shi, Robert Socha, Tom Laidig, Uwe Hollerbach, Kurt Wampler, Stephen Hsu, J. Fung Chen, Noel Corcoran, Mircea Dusa, Jung Chul Park

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568692

KEYWORDS: Reticles, Resolution enhancement technologies, Printing, Scattering, Binary data, Manufacturing, Optical proximity correction, Photomasks, Model-based design, Algorithm development

Read Abstract +

For advance semiconductor manufacturing, imaging contact and via layers continues to be a major challenge for 65nm node lithography and beyond. As a result, much effort is being placed on reducing the k₁ for hole patterning to the range of 0.35 - 0.40. However, the consequences of operating at such low k₁ values are a small DOF, reduced exposure latitude, and high MEF. To achieve this level of k₁, it is necessary to employ resolution enhancement techniques that require phase shifting reticles and/or strong off axis illumination. Recent results show that by using strong off axis illumination to achieve resolution for the dense pitch contacts and by adding subresolution scattering bars for the semi dense to isolated, it is possible to achieve contact hole imaging through the entire pitch range.[1] To generate such reticle designs, the current technique commonly used is to apply a set of rules to define the assist features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) through pitch, whether for binary or attenuated phase shifting reticles. But this approach is not capable of deriving correct assist feature placement for the entire range of pitches and for the randomly placed contact holes that occur in actual device patterns. The objective of this work is to define the necessary methodology for creating binary, attPSM, ternary HTPSM, and CPL^TM reticle designs containing assist features for contact patterns that are representative of actual device patterns that will be used in production at the 65nm node and contain effectively randomly placed contacts over a wide range of pitches from dense to isolated. To overcome the problem of deriving assist features for randomly placed contacts at pitches from semi-dense to isolated, IML^TM Technology was used which is a modeling algorithm based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern.[2,3] This technique provides a model-based approach for placing all types of assist features for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. Using reticle designs created from implementing automated algorithms based on IML, wafer printing results are measured and we examine the critical issues related to contact layer RET's including through pitch process windows, overlapping process window, controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, printing of the assist features, MEF, and reticle manufacturing constraints.

Proceedings Article | 6 December 2004 Paper

Paper

Resist model calibration using 2D developed patterns for low-k1 process optimization and wafer printing predictions

Ting Chen, Douglas Van Den Broeke, Sean Park, Armin Liebchen, J. Fung Chen, Stephen Hsu, Jung Chul Park, Linda Yu, Keith Gronlund

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568671

KEYWORDS: Calibration, Cadmium, Photoresist processing, Diffusion, Scanning electron microscopy, Semiconducting wafers, Printing, Absorption, Optimization (mathematics), Lithography

Read Abstract +

Proceedings Article | 6 December 2004 Paper

Paper

High-resolution actinic imaging and phase metrology of 193-nm CPL reticles

Andrew Merriam, James Jacob, Douglas Van Den Broeke, Stephen Hsu, J. Fung Chen, Bryan Kasprowicz

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569274

KEYWORDS: Photomasks, Metrology, Fringe analysis, Phase shifts, Phase measurement, Etching, Interferometers, Reticles, Microscopes, Quartz

Read Abstract +

Proceedings Article | 6 December 2004 Paper

Paper

OPC model calibration for CPL patterning at extreme low k1

Xuelong Shi, Tom Laidig, J. Fung Chen, Douglas Van Den Broeke, Stephen Hsu, Michael Hsu, Kurt Wampler, Uwe Hollerbach, Jung Chul Park, Linda Yu

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569655

KEYWORDS: Calibration, Optical proximity correction, Photomasks, 3D modeling, Mathematical modeling, Imaging systems, Image processing, Lithography, Scanning electron microscopy, Critical dimension metrology

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Paper

Contact hole reticle optimization by using interference mapping lithography (IML)

Robert Socha, Douglas Van Den Broeke, Stephen Hsu, J. Fung Chen, Thomas Laidig, Noel Corcoran, Uwe Hollerbach, Kurt Wampler, Xuelong Shi, Willard Conley

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557747

KEYWORDS: Photomasks, Atrial fibrillation, Binary data, Electroluminescence, Point spread functions, Lithography, Fresnel lenses, Semiconducting wafers, Phase shifts, Reticles

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Paper

Application of CPL with Interference Mapping Lithography to generate random contact reticle designs for the 65-nm node

Douglas Van Den Broeke, Thomas Laidig, J. Fung Chen, Kurt Wampler, Stephen Hsu, Xuelong Shi, Robert Socha, Mircea Dusa, Noel Corcoran

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557751

KEYWORDS: Reticles, Lithography, Resolution enhancement technologies, Manufacturing, Phase shifts, Photomasks, Printing, Lithographic illumination, Phase shifting, Semiconducting wafers

Read Abstract +

Imaging contact and via layers continues to be one of the major challenges to be overcome for 65nm node lithography. Initial results of using ASML MaskTools' CPL Technology to print contact arrays through pitch have demonstrated the potential to further extend contact imaging to a k1 near 0.30. While there are advantages and disadvantages for any potential RET, the benefits of not having to solve the phase assignment problem (which can lead to unresolvable phase conflicts), of it being a single reticle - single exposure technique, and its application to multiple layers within a device (clear field and dark field) make CPL an attractive, cost effective solution to low k1 imaging. However, real semiconductor circuit designs consist of much more than regular arrays of contact holes and a method to define the CPL reticle design for a full chip circuit pattern is required in order for this technique to be feasible in volume manufacturing. Interference Mapping Lithography (IML) is a novel approach for defining optimum reticle patterns based on the imaging conditions that will be used when the wafer is exposed. Figure 1 shows an interference map for an isolated contact simulated using ASML /1150 settings of 0.75NA and 0.92/0.72/30deg Quasar illumination. This technique provides a model-based approach for placing all types features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary (COG), attenuated phase shifting mask (attPSM), alternating aperture phase shifting mask (altPSM), and CPL. In this work, we investigate the application of IML to generate CPL reticle designs for random contact patterns that are typical for 65nm node logic devices. We examine the critical issues related to using CPL with Interference Mapping Lithography including controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, and reticle manufacturing constraints. Multiple methods for deriving the interference map used to define reticle patterns for various RET's will be discussed. CPL reticle designs that were created from implementing automated algorithms for contact pattern decomposition using MaskWeaver will also be presented.

Proceedings Article | 20 August 2004 Paper

Paper

Through-pitch low-k₁ contact hole imaging with CPL technology

Vincent Wiaux, Joost Bekaert, J. Fung Chen, Stephen Hsu, Kurt Ronse, Robert Socha, Geert Vandenberghe, Douglas Van Den Broeke

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557803

KEYWORDS: Reticles, Resolution enhancement technologies, Printing, Lithography, Immersion lithography, Chromium, Electroluminescence, Semiconducting wafers, Photomasks, Critical dimension metrology

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Paper

CPL reticle technology for advanced device applications

Willard Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Bernard Roman, Richard Peters, Colita Parker, J. Fung Chen, Kurt Wampler, Thomas Laidig, Erika Schaefer, Jan-Pieter Kuijten, Arjan Verhappen, Stephan van de Goor, Martin Chaplin, Bryan Kasprowicz, Christopher Progler, Emilien Robert, Philippe Thony, Michael Hathorn

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557802

KEYWORDS: Photomasks, Optical proximity correction, Image processing, Reticles, Resolution enhancement technologies, Phase shifts, Mask making, Scanning electron microscopy, Quartz, Binary data

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Paper

CPL mask technology for sub-100-nm contact hole imaging

Bryan Kasprowicz, Willard Conley, Lloyd Litt, Douglas Van Den Broeke, Patrick Montgomery, Robert Socha, Wei Wu, Kevin Lucas, Bernard Roman, J. Fung Chen, Kurt Wampler, Thomas Laidig, Christopher Progler, Michael Hathorn

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557755

KEYWORDS: Photomasks, Reticles, Manufacturing, Inspection, Lithography, Image processing, Semiconducting wafers, Quartz, Metrology, Optical lithography

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Paper

Eigen-decomposition-based models for model OPC

Xuelong Shi, Thomas Laidig, J. Fung Chen, Douglas Van Den Broeke, Stephen Hsu, Michael Hsu, Kurt Wampler, Uwe Hollerbach

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557794

KEYWORDS: Calibration, Optical proximity correction, Mathematical modeling, Lithography, Photomasks, Data modeling, Scanning electron microscopy, Image processing, Critical dimension metrology, Binary data

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Paper

Double dipole lithography for 65-nm node and beyond: a technology readiness review

Stephen Hsu, Mark Eurlings, Eric Hendrickx, Douglas Van Den Broeke, Tsann-Bim Chiou, J. Fung Chen, Thomas Laidig, Xuelong Shi, Jo Finders

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557797

KEYWORDS: Reticles, Photomasks, Optical proximity correction, Line width roughness, Nanoimprint lithography, Semiconducting wafers, Printing, Stray light, Model-based design, Resolution enhancement technologies

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Paper

Full-chip manufacturing reliability check implementation for 90-nm and 65-nm nodes using CPL and DDL

Michael Hsu, Thomas Laidig, Kurt Wampler, Stephen Hsu, Xuelong Shi, J. Fung Chen, Douglas Van Den Broeke, Frank Hsieh

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557792

KEYWORDS: Photomasks, Manufacturing, Optical proximity correction, Semiconducting wafers, Printing, Critical dimension metrology, Computer aided design, Reliability, Mask making, Resolution enhancement technologies

Read Abstract +

Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.

Proceedings Article | 28 May 2004 Paper

Paper

The application of CPL reticle technology for the 0.045-mm node

Will Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Bernard Roman, Richard Peters, Colita Parker, Fung Chen, Kurt Wampler, Thomas Laidig, Erika Schaefer, Jan-Pieter Kuijten, Arjan Verhappen, Stephan van de Goor, Martin Chaplin, Bryan Kasprowicz, Christopher Progler, Emilien Robert, Philippe Thony

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537613

KEYWORDS: Photomasks, Optical proximity correction, Reticles, Image processing, Resolution enhancement technologies, Phase shifts, Mask making, Scanning electron microscopy, Manufacturing, Quartz

Read Abstract +

Proceedings Article | 28 May 2004 Paper

Paper

Defect printability in CPL mask technology

Jan-Pieter Kuijten, Arjan Verhappen, Wil Pijnenburg, Will Conley, Lloyd Litt, Wei Wu, Patrick Montgomery, Bernard Roman, Bryan Kasprowicz, Christopher Progler, Robert Socha, Douglas Van Den Broeke, Erika Schaefer, Pat Cook

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537619

KEYWORDS: Photomasks, Resolution enhancement technologies, Reticles, Manufacturing, Scanning electron microscopy, Semiconductors, Phase shifts, Binary data, Lithography, Semiconducting wafers

Read Abstract +

Proceedings Article | 28 May 2004 Paper

Paper

Contact hole reticle optimization by using interference mapping lithography (IML)

Robert Socha, Douglas Van Den Broeke, Stephen Hsu, J. Fung Chen, Thomas Laidig, Noel Corcoran, Uwe Hollerbach, Kurt Wampler, Xuelong Shi, Will Conley

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.536581

KEYWORDS: Photomasks, Atrial fibrillation, Binary data, Electroluminescence, Point spread functions, Lithography, Fresnel lenses, Semiconducting wafers, Phase shifts, Reticles

Read Abstract +

Proceedings Article | 28 May 2004 Paper

Paper

RET integration of CPL technology for random logic

Stephen Hsu, Douglas Van Den Broeke, J. Fung Chen, Xuelong Shi, Michael Hsu, Thomas Laidig, Will Conley, Lloyd Litt, Wei Wu

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537414

KEYWORDS: Photomasks, Nanoimprint lithography, Image transmission, Manufacturing, Optical proximity correction, Diffraction, Transmittance, Resolution enhancement technologies, Semiconducting wafers, Phase shifts

Read Abstract +

Proceedings Article | 3 May 2004 Paper

Paper

Extending aggressive low-k1 design rule requirements for 90-nm and 65-nm nodes via simultaneous optimization of NA, illumination, and OPC

Sabita Roy, Douglas Van Den Broeke, J. Chen, Armin Liebchen, Ting Chen, Stephen Hsu, Xuelong Shi, Robert Socha

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.536982

KEYWORDS: Diffractive optical elements, Optical proximity correction, Calibration, Critical dimension metrology, Stanford Linear Collider, Photomasks, Fiber optic illuminators, Printing, Logic, Lithography

Read Abstract +

Under low-k₁ patterning constraints, it has been a challenge for the lithography process to meet the aggressive IC design rule requirements for the 90nm and the upcoming 65nm nodes. From the imaging perspective, we see the geometric design rules are largely governed by numerical aperture (NA), illumination settings, and OPC for any resolution enhancement technique (RET) applied mask. We report a case study of exploring a set of process feasible design rule criteria based on a state-of-the-art μProcessor chip that contains three different styles of circuit design - standard library cell (SLC), random logic (RML), and SRAM. To keep the packing density higher for SRAM, the critical criteria for design rules involve achievable minimum pitch, sufficient area of contact-landing pad, minimum line end shortening (LES) to ensure poly endcap, and preferably to have optimum pitch for the placement of Scattering Bars (SB). For RML, the goal is to achieve the printing of ever smaller critical dimension (CD) with a greater CD uniformity control. The SLC should be designed to be comparable with both RML and SRAM devices. Hence, the design rule constraints for CD, space, line end, minimum pitch, and SB placement for SLC cell is critically confined. Unlike the traditional method of assuming a linear scaling for the design rule set, we explore achievable design rule criteria for very low k₁ imaging by simultaneously optimizing NA, illumination settings, and OPC (for the optimum placement of SB) for a calibrated process. This is done by analyzing the CD control and the maximum overlapped process window for critical lines, spaces, line ends, and with the respective k₁ factor for the three types of circuits. For 90nm node with k₁ as low as 0.36, a feasible set of design rules for the μProcessor chip can be obtained using 6% attPSM with 6% exposure latitude at 400nm of overlapped depth of focus. Using the similar approach for the scaled down 65nm 6% attPSM, it resulted inadequate process latitude under a set of desired design rule constraints for critical pitch, CD, line end, minimum space, and SB placement. Hence for 65nm case, a CPL mask was used instead, as CPL (100% transmission) has the inherent capability of printing very thin line. The critical design rule criteria for SRAM, RML and SLC were revisited to ensure a large enough process margin.

Proceedings Article | 17 December 2003 Paper

Paper

Full-chip application for SRAM gate at 100-nm node and beyond using chromeless phase lithography

Ji-Soong Park, Sung-Hyuck Kim, In-Kyun Shin, Sung-Woon Choi, Jung-Min Sohn, Jae-Han Lee, Hye-soo Shin, Thomas Laidig, Douglas Van Den Broeke, J. Fung Chen

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518014

KEYWORDS: Photomasks, Scattering, Semiconducting wafers, Neodymium, Lithography, Optical proximity correction, Camera shutters, Optics manufacturing, Wafer-level optics, Phase shifting

Read Abstract +

Proceedings Article | 17 December 2003 Paper

Paper

Study of dry etching pattern profile of chromeless phase lithography (CPL) mask

Jimmy Lin, Michael Hsu, Tony Hsu, Stephen Hsu, Xuelong Shi, Douglas Van Den Broeke, J. Fung Chen, F. Tang, W. Hsieh, C. Huang

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518021

KEYWORDS: Etching, Photomasks, Dry etching, Quartz, Semiconducting wafers, Lithography, Diffractive optical elements, Scanning electron microscopy, Metrology, Printing

Read Abstract +

Proceedings Article | 17 December 2003 Paper

Paper

Near-0.3 k1 full pitch range contact hole patterning using chromeless phase lithography (CPL)

Douglas Van Den Broeke, Robert Socha, Stephen Hsu, J. Fung Chen, Thomas Laidig, Noel Corcoran, Uwe Hollerbach, Kurt Wampler, Xuelong Shi

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518308

KEYWORDS: Reticles, Printing, Resolution enhancement technologies, Manufacturing, Lithography, Semiconducting wafers, Lithographic illumination, Optical lithography, Phase shifts, Scanners

Read Abstract +

Proceedings Article | 28 August 2003 Paper

Paper

Investigation of phase variation impact on CPL PSM for low k1 imaging

Chun-hung Lin, Michael Hsu, Frank Hsieh, Shu Yi Lin, Stephen Hsu, Xuelong Shi, Douglas Van Den Broeke, J. Fung Chen, F. Tang, W. Hsieh, C. Huang

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504176

KEYWORDS: Etching, Photomasks, Critical dimension metrology, Semiconducting wafers, Quartz, Printing, Image processing, Metrology, Process control, Phase shifting

Read Abstract +

Proceedings Article | 28 August 2003 Paper

Paper

Low k1 lithography patterning option for the 90-nm and 65-nm nodes

Stephen Hsu, Douglas Van Den Broeke, Xuelong Shi, Michael Hsu, Kurt Wampler, J. Fung Chen, Annie Yu, Samuel Yang, Frank Hsieh

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504394

KEYWORDS: Photomasks, Reticles, Manufacturing, Phase shifts, Lithography, Nanoimprint lithography, Etching, Quartz, Image transmission, Transmittance

Read Abstract +

Proceedings Article | 26 June 2003 Paper

Paper

65-nm full-chip implementation using double dipole lithography

Stephen Hsu, J. Fung Chen, Noel Cororan, William Knose, Douglas Van Den Broeke, Thomas Laidig, Kurt Wampler, Xuelong Shi, Michael Hsu, Mark Eurlings, Jo Finders, Tsann-Bim Chiou, Robert Socha, Will Conley, Yen Hsieh, Steve Tuan, Frank Hsieh

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485445

KEYWORDS: Reticles, Photomasks, Model-based design, Scattering, Optical proximity correction, Stray light, Resolution enhancement technologies, 3D modeling, Logic, Binary data

Read Abstract +

Proceedings Article | 26 June 2003 Paper

Paper

ArF solutions for low-k₁ back-end imaging

Vincent Wiaux, Patrick Montgomery, Geert Vandenberghe, Philippe Monnoyer, Kurt Ronse, Will Conley, Lloyd Litt, Kevin Lucas, Jo Finders, Robert Socha, Douglas Van Den Broeke

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485502

KEYWORDS: Electroluminescence, Printing, Resolution enhancement technologies, Photomasks, Lithography, Reticles, Optical lithography, Phase shifts, Lithographic illumination, Metrology

Read Abstract +

The requirements stated in the ITRS roadmap for back-end-of-line imaging of current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will be necessary for the imaging of contacts and trenches, pushing optical lithography into the low-k₁ regime. In this paper, we focus more specifically on imaging solutions for contact holes beyond the 90 nm node using high NA ArF lithography, as this is currently seen as one of the major challenges in optical lithography. We investigate the performance of various existing enhancement techniques in order to provide contact holes imaging solutions in a k₁ range from 0.35 to 0.45, using the ASML PAS5500/1100 0.75NA ArF scanner installed at IMEC. For various resolution enhancement techniques (RET), the proof of concept has been demonstrated in literature. In this paper, we propose an experimental one-to-one comparison of these RET’s with fixed CD target, exposure tool, lithographic process, and metrology. A single exposure through pitch (dense through isolated) printing solution is preferred and is the largest challenge. The common approach using a 6% attenuated phase-shifted mask (attPSM) with a conventional illumination fails. The advantages and drawbacks of other techniques are discussed. High transmission (17%) attenuated phase shift, potentially beneficial for part of the pitch range, requires conflicting trade-offs when looking for a single exposure through pitch solution. More promising results are obtained combining a BIM or a 6% attPSM with assist slots and off-axis illumination, yielding a depth of focus (DOF) at 8% exposure latitude (EL) greater than 0.31 μm from 200 nm pitch through isolated. Chromeless phase lithography (CPL) is also discussed with promising results obtained at the densest pitch. At a 0.4 k₁, an experimental extrapolation to 0.85NA demonstrates that a pitch of 180 nm can be resolved with 0.4 μm DOF at 8% EL. For all of these imaging solutions, various metrics are studied to compare printing performance. In addition to process latitude, we consider forbidden pitches, sidelobes printability, and mask error enhancement factor (MEEF).

Proceedings Article | 26 June 2003 Paper

Paper

Application of CPL reticle technology for the 65- and 50-nm node

Will Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Carla Nelson-Thomas, Bernard Roman, J. Fung Chen, Kurt Wampler, Thomas Laidig, Stephen Hsu, Erika Schaefer, Shawn Cassel, Linda Yu, Bryan Kasprowicz, Christopher Progler, John Petersen, David Gerold, Mark John Maslow

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485515

KEYWORDS: Photomasks, Reticles, Optical proximity correction, Image processing, Resolution enhancement technologies, Manufacturing, Phase shifts, Mask making, Quartz, Lithography

Read Abstract +

Proceedings Article | 27 December 2002 Paper

Paper

Mesa or trench type for chromeless phase-shift lithography from photolithographic performance point of view

Xuelong Shi, J. Fung Chen, Stephen Hsu, Michael Hsu, Douglas Van Den Broeke, Robert Socha, Chun Hong Chang, Chang Min Dai

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467393

KEYWORDS: Photomasks, Phase shifts, Optical lithography, Diffraction, Lithography, 3D image processing, Quartz, Etching, Electromagnetism, Optical proximity correction

Read Abstract +

Proceedings Article | 27 December 2002 Paper

Paper

Phase defect repair for the chromeless phase lithography (CPL) mask

Steven Fan, Michael Hsu, Alex Tseng, J. Fung Chen, Douglas Van Den Broeke, Henrry Lei, Stephen Hsu, Xuelong Shi

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467486

KEYWORDS: Photomasks, Quartz, Etching, Inspection, Lithography, Scanning electron microscopy, Printing, Semiconducting wafers, Mask making, Image processing

Read Abstract +

Proceedings Article | 27 December 2002 Paper

Paper

Application of chromeless phase lithography (CPL) masks in ArF lithography

Bryan Kasprowicz, Christopher Progler, Wei Wu, Will Conley, Lloyd Litt, Douglas Van Den Broeke, Kurt Wampler, Robert Socha

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468107

KEYWORDS: Photomasks, Lithography, Quartz, Etching, Manufacturing, Reticles, Inspection, Antireflective coatings, Optical proximity correction, Binary data

Read Abstract +

Proceedings Article | 27 December 2002 Paper

Paper

Application of Cr-less mask technology for sub-100-nm gate with single exposure

Sung-Hyuck Kim, Dong-Hoon Chung, Ji-Soong Park, In-Kyun Shin, Seong-woon Choi, Jung-Min Sohn, Jae-Han Lee, Hye-Soo Shin, J. Fung Chen, Douglas Van Den Broeke

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468097

KEYWORDS: Photomasks, Camera shutters, Semiconducting wafers, Critical dimension metrology, Optical proximity correction, Chromium, Lithography, Wafer-level optics, Phase shifts, Printing

Read Abstract +

Proceedings Article | 27 December 2002 Paper

Paper

Tuning MEEF for CD control at 65-nm node based on chromeless phase lithography (CPL)

Douglas Van Den Broeke, Thomas Laidig, Kurt Wampler, Stephen Hsu, Xuelong Shi, Michael Hsu, Paul Burchard, J. Fung Chen

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467508

KEYWORDS: Reticles, Semiconducting wafers, Photomasks, Critical dimension metrology, Manufacturing, Lithography, Image processing, Scanners, Imaging systems, Wafer-level optics

Read Abstract +

The application of Chromeless Phase Lithography, or 100% transmission attenuated PSM, has been used to demonstrate the potential for achieving quarter-wavelength optical lithography (0.2k₁). As the demand to image sub-100nm features reaches to the semiconductor fabrication lines, the need for a robust lithography process capable of meeting high volume requirements is becoming more and more critical. The requirements for high-volume, low-k₁ semiconductor manufacturing go beyond wafer imaging technology capable of the process latitude needed for lithography, but also includes data prep software that is capable of applying the details of the imaging technology to the design data, correcting for optical proximity effects, and outputting the necessary mask pattern data. It is also necessary to have a reticle manufacturing infrastructure capable of supporting large volume production with reliability and reasonable turn around time. CPL technology has, by its nature, many elements that make it a strong candidate to meet mass production requirements for 65nm semiconductor technology products. Most important, CPL achieves the resolution enhancement by using a single reticle and does not require a second exposure with a trim mask. The CPL reticle is a variation of the attenuated phase shifting mask, and data preparation for the reticle manufacturing is very similar to what is needed for high-transmission attenuated PSM. It will be shown that as a result of the 100% transmission, the MEEF for CPL masks is very small and in some cases approaches zero. This allows for much larger CD tolerances for the reticle but results in significant limitations on correcting optical proximity effects by using CD bias alone. Methods for correcting through-pitch CD variations with the use of novel CPL pattern designs, bias, and scattering bars will be presented and correlated to wafer imaging results. These results will demonstrate the ability to control through-pitch CD's while maintaining the beneficial MEEF characteristics of CPL. Experimental results using a CPL reticle designed and manufactured for 65nm lithography exposed on an advanced 193nm ASML /1100 wafer scanner will be presented and discussed.

SPIE Journal Paper | 1 October 2002

Complex two dimensional pattern lithography using chromeless phase lithography (CPL)

Douglas Van Den Broeke, J. Fung Chen, Thomas Laidig, Stephen Hsu, Kurt Wampler, Robert Socha, John Petersen

JM3, Vol. 1, Issue 03, (October 2002) https://doi.org/10.1117/12.10.1117/1.1504458

KEYWORDS: Reticles, Lithography, Semiconducting wafers, Manufacturing, Optical lithography, Lithographic illumination, Resolution enhancement technologies, Opacity, Printing, Scanning electron microscopy

Read Abstract +

Proceedings Article | 1 August 2002 Paper

Paper

Development of mask-making process for CLM manufacturing technology

Jin-Hyung Park, Dong-Hoon Chung, Man-Ki Lee, In-Kyun Shin, Seong-Woon Choi, Hee-Sun Yoon, Jung-Min Sohn, J. Fung Chen, Douglas Van Den Broeke

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476959

KEYWORDS: Photomasks, Quartz, Etching, Inspection, Manufacturing, Dry etching, Binary data, Resolution enhancement technologies, Optics manufacturing, Lithography

Read Abstract +

Proceedings Article | 1 August 2002 Paper

Paper

Reticle defect printability for sub-0.3k1 chromeless phase lithography (CPL) technology

Stephen Hsu, Douglas Van Den Broeke, Xuelong Shi, J. Fung Chen, William Knose, Noel Corcoran, Srinivas Vedula, Craig MacNaughton, Michael Richie

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476983

KEYWORDS: Quartz, Photomasks, Reticles, Chromium, Scattering, Critical dimension metrology, Printing, Etching, Lithography, Semiconducting wafers

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Paper

Patterning half-wavelength DRAM cell using chromelessp phase lithography (CPL)

Chungwei Michael Hsu, Ronfu Chu, J. Fung Chen, Douglas Van Den Broeke, Xuelong Shi, Stephen Hsu, Troy Wang

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474629

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Optical lithography, Manufacturing, Printing, Computer aided design, Phase shifts, Resolution enhancement technologies, Lithographic illumination

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Paper

Complex 2D pattern lithography at lambda/4 resolution using chromeless phase lithography (CPL)

Douglas Van Den Broeke, J. Fung Chen, Thomas Laidig, Stephen Hsu, Kurt Wampler, Robert Socha, John Petersen

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474555

KEYWORDS: Reticles, Lithography, Semiconducting wafers, Manufacturing, Phase shifts, Optical lithography, Resolution enhancement technologies, Printing, Opacity, Photomasks

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Paper

Extending KrF to 100-nm imaging with high-NA- and chromeless phase lithography technology

Robert Socha, Douglas Van Den Broeke, Linda Yu, Will Conley, Wei Wu, J. Fung Chen, John Petersen, David Gerold, Judith van Praagh, Richard Droste, Donis Flagello, Stephen Hsu

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474594

KEYWORDS: Reticles, Lithography, Scanning electron microscopy, Nanoimprint lithography, Diffraction, Quartz, Photomasks, Capacitors, Phase shifts, Lithographic illumination

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Paper

New resolution enhancement technology for manufacturing sub-100-nm technology

Dong-Hoon Chung, Jean-Young Park, Man-Ki Lee, In-Gyun Shin, Seong-Woon Choi, Hee-Sun Yoon, Jung-Min Sohn, J. Fung Chen, Douglas Van Den Broeke

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474534

KEYWORDS: Etching, Photomasks, Quartz, Inspection, Dry etching, Resolution enhancement technologies, Manufacturing, Mask making, Optical lithography, Lithography

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Paper

Inspection of chromeless AAPSM

Darren Taylor, Matthew Lassiter, Benjamin Eynon, Douglas Van Den Broeke, J. Fung Chen

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474513

KEYWORDS: Photomasks, Inspection, Phase shifts, Quartz, Manufacturing, Lithography, Silica, Semiconducting wafers, Optical lithography, Defect detection

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Paper

Development of a sub-100-nm integrated imaging system using chromeless phase-shifting imaging with very high NA KrF exposure and off-axis illumination

John Petersen, Will Conley, Bernard Roman, Lloyd Litt, Kevin Lucas, Wei Wu, Douglas Van Den Broeke, J. Fung Chen, Thomas Laidig, Kurt Wampler, David Gerold, Robert Socha, Judith van Praagh, Richard Droste

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474599

KEYWORDS: Diffraction, Phase shifts, Photomasks, Image processing, Halftones, Imaging systems, Transmittance, Opacity, Scattering, Photoresist materials

Read Abstract +

Proceedings Article | 12 July 2002 Paper

Paper

Development of a sub-100nm integrated imaging system using chromeless phase-shifting imaging with very high NA KrF exposure and off-axis illumination

John Petersen, Will Conley, Bernard Roman, Lloyd Litt, Kevin Lucas, Wei Wu, Douglas Van Den Broeke, J. Fung Chen, Thomas Laidig, Kurt Wampler, David Gerold, Mark Maslow, Robert Socha, Judith van Praagh, Richard Droste

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475692

KEYWORDS: Diffraction, Phase shifts, Photomasks, Image processing, Imaging systems, Opacity, Halftones, Tolerancing, Scattering, Lithography

Read Abstract +

Examining features of varying pitch imaged using phase- shifting masks shows a pitch dependence eon the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180- degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. chromeless Phase-Shift Lithography (CPL) deals with using half-toning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase- shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These half toning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0 percent to 100 percent and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi- transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.

Proceedings Article | 23 April 2002 Paper

Paper

Mask design optimization for 70-nm technology node using chromeless phase lithography (CPL) based on 100% transmission phase shifting mask

J. Fung Chen, Douglas Van Den Broeke, Michael Hsu, Thomas Laidig, Kurt Wampler, Xuelong Shi, Stephen Hsu, Ted Shafer

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476927

KEYWORDS: Photomasks, Phase shifts, Lithography, Optical proximity correction, Optical lithography, Semiconducting wafers, Phase shifting, Printing, Image acquisition, Reticles

Read Abstract +

Proceedings Article | 30 December 1999 Paper

Paper

CD error sensitivity to "sub-killer" defects at k1 near 0.4: II

Kent Nakagawa, J. Fung Chen, Robert Socha, Mircea Dusa, Thomas Laidig, Kurt Wampler, Roger Caldwell, Douglas Van Den Broeke

Proceedings Volume 3873, (1999) https://doi.org/10.1117/12.373382

KEYWORDS: Reticles, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Photomasks, Defect detection, Scattering, Inspection, Photoresist processing

Read Abstract +

Proceedings Article | 25 August 1999 Paper

Paper

Halftone biasing OPC technology: an approach for achieving fine bias control on raster-scan systems

Kent Nakagawa, J. Fung Chen, Robert Socha, Thomas Laidig, Kurt Wampler, Douglas Van Den Broeke, Mircea Dusa, Roger Caldwell

Proceedings Volume 3748, (1999) https://doi.org/10.1117/12.360237

KEYWORDS: Halftones, Reticles, Semiconducting wafers, Inspection, Optical proximity correction, Scanning electron microscopy, Teeth, Control systems, Manufacturing, Semiconductors

Read Abstract +

Proceedings Article | 14 June 1999 Paper

Paper

CD error sensitivity to "sub-killer" defects at k1 near 0.4

J. Fung Chen, Nathan Diachun, Kent Nakagawa, Robert Socha, Mircea Dusa, Thomas Laidig, Kurt Wampler, Roger Caldwell, Douglas Van Den Broeke

Proceedings Volume 3677, (1999) https://doi.org/10.1117/12.350858

KEYWORDS: Reticles, Optical proximity correction, Critical dimension metrology, Scanning electron microscopy, Semiconducting wafers, Cadmium, Scattering, Photoresist processing, Silicon, Defect inspection

Read Abstract +

Proceedings Article | 23 April 1999 Paper

Paper

Manufacturing an advanced process characterization reticle incorporating halftone biasing

Kent Nakagawa, Douglas Van Den Broeke, J. Fung Chen, Thomas Laidig, Kurt Wampler, Roger Caldwell

Proceedings Volume 3665, (1999) https://doi.org/10.1117/12.346215

KEYWORDS: Halftones, Reticles, Optical proximity correction, Inspection, Semiconducting wafers, Scanning electron microscopy, Manufacturing, Teeth, Scattering, Semiconductors

Read Abstract +

As the semiconductor roadmap continues to require imaging of smaller feature son wafers, we continue to explore new approaches in OPC strategies to extend the lifespan of existing technology. In this paper, we study a new OPC technology, called halftone biasing, and its application on an OPC characterization reticle, designed by MicroUnity Systems Engineering, Inc. The RTP9 test reticle is the latest in a series of 'LineSweeper' characterization reticles. Each reticle contains a wide range of line width sand pitches, each with several alternative OPC treatments, including references cases, scattering bars, and fine biasing. One of RTP9's design requirements was to support very fine, incremental biases for densely-pitched lines. Ordinarily, this would dictate a reduced address unit and with it the costly penalty of a square-law increase in e- beam write time. RTP9 incorporates a new OPC strategy, called halftone biasing, which has been proposed to address this problem. Taking advantage of optical reduction printing, this technique applies a sub-resolution halftone screen to the edges of figures to accomplish fine biasing equivalent to using an address unit one-fourth of the size of the actual e-beam writing grid. The resulting edge structure has some of the characteristics of aggressive OPC structures, but can be used in areas where traditional scattering bars cannot be placed. The trade-off between the faster write times achieved and the inflation of pattern file size is examined. The manufacturability and inspectability of halftone-biased lines on the RTP9 test reticle are explored. Pattern fidelity is examined using both optical and SEM tools. Printed 0.18 micrometers DUV resist line edge profiles are compared for both halftone and non- halftone feature edges. The CD uniformity of the OPC features, and result of die-to-database inspection are reported. The application of halftone biasing to real circuits, including the impact of data volume and saved write time, is also discussed.

Proceedings Article | 1 September 1998 Paper

Paper

Designing dual-trench alternating phase-shift masks for 140-nm and smaller features using 248-nm KrF and 193-nm ArF lithography

John Petersen, Robert Socha, Alex Naderi, Catherine Baker, Syed Rizvi, Douglas Van Den Broeke, Nishrin Kachwala, J. Fung Chen, Thomas Laidig, Kurt Wampler, Roger Caldwell, Susumu Takeuchi, Yoshiro Yamada, Takashi Senoh, Martin McCallum

Proceedings Volume 3412, (1998) https://doi.org/10.1117/12.328861

KEYWORDS: Etching, Optical proximity correction, Diffraction, Photomasks, Reticles, Phase shifts, Quartz, Anisotropic etching, Lithography, Phase measurement

Read Abstract +

Proceedings Article | 12 February 1997 Paper

Paper

OPC technology road map to 0.14-um design rules

J. Fung Chen, Thomas Laidig, Kurt Wampler, Roger Caldwell, Alex Naderi, Douglas Van Den Broeke

Proceedings Volume 3236, (1997) https://doi.org/10.1117/12.301210

KEYWORDS: Optical proximity correction, Reticles, Inspection, Scattering, Computer aided design, Semiconducting wafers, Photomasks, Manufacturing, Scanning electron microscopy, Antimony

Read Abstract +

Proceedings Article | 27 December 1996 Paper

Paper

Improved PBS process for e-beam photomask lithography

Wayne Shen, James Marra, Douglas Van Den Broeke

Proceedings Volume 2884, (1996) https://doi.org/10.1117/12.262846

KEYWORDS: Etching, Photomasks, Photoresist processing, Optical proximity correction, Electron beam lithography, Lithography, Line edge roughness, Switches, Isotropic etching, Standards development

Read Abstract +

Showing 5 of 73 publications

SIGN IN TO:

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Advertisement

Advertisement