Dr. Dunja Radisic Profile

Dr. Dunja Radisic

at imec

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Publications (7)

Proceedings Article | 9 April 2024 Presentation + Paper

Dry etch challenges for patterning middle-of-line (MOL) contact trench in monolithic CFET (complementary FET)

T. Sarkar, D. Radisic, V. Vega Gonzalez, K. Stiers, C. Sheng, D. Montero, H. Jenkins, M. Demand, P. Wang, F. Lazzarino, N. Horiguchi

Proceedings Volume 12958, 129580B (2024) https://doi.org/10.1117/12.3014213

KEYWORDS: Etching, Optical lithography, Polymers, Semiconducting wafers, Plasma etching, Passivation, Lithography, Plasma, Dry etching, Wafer testing

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Proceedings Article | 1 May 2023 Presentation + Paper

Middle-of-line plasma dry etch challenges for CFET integration

D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12499, 1249909 (2023) https://doi.org/10.1117/12.2659095

KEYWORDS: Etching, Optical lithography, Lithography, Plasma etching, Plasma, Dry etching, Critical dimension metrology, Dielectrics

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In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO₂ dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO₂ is developed. This patterning sequence consists of SiO₂ etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)

Proceedings Article | 25 May 2022 Presentation + Paper

Middle-of-line plasma dry etch challenges for buried power rail integration

Dunja Radisic, A. Veloso, A. Gupta, M. Hosseini, S. Wang, H. Mertens, B. Chan, D. Batuk, G. Martinez, F. Lazzarino, E. Litta, N. Horiguchi

Proceedings Volume 12056, 120560C (2022) https://doi.org/10.1117/12.2616731

KEYWORDS: Etching, Metals, Plasma etching, Optical lithography, Ruthenium, Plasma, Tin, Dielectrics, Dry etching, Molybdenum

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Proceedings Article | 25 May 2022 Presentation + Paper

Buried power rail integration for CMOS scaling beyond the 3 nm node

A. Gupta, Z. Tao, D. Radisic, H. Mertens, O. Varela Pedreira, S. Demuynck, J. Bömmels, K. Devriendt, N. Heylen, S. Wang, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, S. Subramanian, F. Schleicher, A. Peter, N. Rassoul, Y. Siew, B. Briggs, D. Zhou, E. Rosseel, E. Capogreco, G. Mannaert, A. Sepúlveda, E. Dupuy, K. Vandersmissen, B. Chehab, G. Murdoch, E. Altamirano Sanchez, S. Biesemans, Zs. Tőkei, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12056, 120560B (2022) https://doi.org/10.1117/12.2615641

KEYWORDS: Ruthenium, Metals, Molybdenum, Etching, Tungsten, Front end of line, Chemical mechanical planarization, Silicon

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Proceedings Article | 20 March 2019 Paper

Plasma etch selectivity study and material screening for self-aligned gate contact (SAGC)

Dunja Radisic, Marc Demand, Shihsheng Chang, Steven Demuynck, Kaushik Kumar, Andrew Metz, Lieve Teugels, Junling Sun, Jeffrey Smith, Farid Sebaai, Toby Hopf, Efrain Altamirano Sánchez

Proceedings Volume 10963, 109630P (2019) https://doi.org/10.1117/12.2505129

KEYWORDS: Etching, Silicon carbide, Plasma etching, Silicon, Plasma, Fluorine, Polymers, Dielectrics, Polymer thin films, Optical lithography

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Self-Aligned Gate Contact (SAGC) integration is design based on formation of the two separate contacts to the source/drain (S/D) and to the gate (G), which are realized in two separate plasma etch steps. Essentially, the first one is the contact plug (CP) etch over S/D contact selective to the gate plug (GP) and sidewall spacer (SWS), and the second one is the gate plug (GP) etch selective to the contact plug (CP) and the sidewall spacer (SWS). Therefore, the high selectivity plasma etch processing for the CP and GP towards the other two relevant, neighboring films is a key requirement for successful SAGC integration. In this paper we present plasma etch process development required for SAGC implementation, primarily focusing on the multi-color selectivity studies, i.e., selective CP (towards GP and SWS) as well as selective GP (towards CP and SWS) at contacted poly pitch (CPP) 42nm. The primary (‘standard’) integration scheme uses SiO₂ CP, Si₃N₄ GP and SiCO SWS. Furthermore, we investigate the “alternative’ integration scheme with SiCxNy films as replacement of the traditionally used SiO₂ CP material aiming to simplify the patterning sequence and ease high selectivity requirements. We report the selectivity values obtained on the CP/GP/SWS multi-color stack for the CP plasma processing (SiO₂ or SiC_xN_y) towards Si₃N₄ and SiCO; as well as for GP (Si₃N₄) plasma dry etch process towards SiO₂ or SiC_xN_y and SiCO. Using a Quasi-ALE (Q-ALE) approach for selective SiO₂ etch process is developed with a selectivity of 8 to 1 towards Si³N₄ and SiCO. For the selective Si₃N₄ etch continuous wave plasma CH₃F-based process is developed and selectivity of 9 to 1 towards SiO₂ and SiCO achieved. In the case of the integration scheme with SiC_xN_y CP, the selectivity for SiC_xN_y etch towards Si₃N₄ GP and SiCO SWS higher than 20 to 1 is accomplished using continuous RF source NF₃/O₂- based process. As for the Si₃N₄ plasma etch in the ‘alternative’ scheme using CH₃F/O₂-based process, the selectivity towards SiC_xN_y of higher than 20 to 1 and selectivity to SiCO of around 10 to 1 is achieved.

Proceedings Article | 28 August 2014 Paper

Status and outlook of STT-MRAM development

T. Min, G. Kar, J. Swerts, S. Mertens, S. Coseman, J. Bekaert, K. Xu, L. Souriau, D. Radisic, H. Okuyama, K. Nishimura, T. Seino, K. Tsunekawa

Proceedings Volume 9167, 91671B (2014) https://doi.org/10.1117/12.2063079

KEYWORDS: Resistance, Annealing, Lithography, Electrodes, Switching, Magnetism, Optical lithography, Deposition processes, Extreme ultraviolet, Ferromagnetics

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Proceedings Article | 29 March 2013 Paper

STT MRAM patterning challenges

Werner Boullart, Dunja Radisic , Vasile Paraschiv, Sven Cornelissen, Mauricio Manfrini, Koichi Yatsuda, Eiichi Nishimura, Tetsuya Ohishi, Shigeru Tahara

Proceedings Volume 8685, 86850F (2013) https://doi.org/10.1117/12.2013602

KEYWORDS: Etching, Plasma, Plasma etching, Optical lithography, Ions, Wet etching, Ion beams, Magnetism, Chemistry, Tantalum

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