In this paper we performed 2D and 3D device simulations to analyze the impact of technology scaling on the lattice heating in n-channel bulk silicon and silicon-on-insulator MOS transistors with gate lengths from 0.5 to 0.1 um. Maximum lattice temperatures and transistor thermal resistances for different gate lengths and bias voltages were calculated. The increase in device temperature and thermal resistance with transistor scaling was shown.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.