KEYWORDS: Transistors, Amplifiers, Very large scale integration, Power supplies, Molybdenum, Manufacturing, Telecommunications, Logic, Capacitance, Electronics
Aggressive CMOS scaling results in significant increase of leakage current in MOS transistors manufactured in deep
submicron regime. Consequently low power SRAM design becomes an important criteria in design of VLSI circuits. In
this work, a new six transistor (6T) SRAM cell based on dual threshold voltage and dual power supply techniques, has
been proposed for low leakage SRAM design. The proposed cell has been compared to the conventional 6T-SRAM,
using the 65 nm technology. Compared to conventional six transistor (6T) SRAM cell, new 6T SRAM cell reduces
leakage power consumption by 72.6%. Furthermore, the proposed SRAM cell shows no area overhead and comparable
read/ writes speed as compared to conventional 6T SRAM cell.
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