In this work, we investigate non-optimized QKD links between arbitrary pairs of Alices and Bobs using off-the-shelf Toshiba QKD devices. Performance variation is observed when connecting unmatched Alices and Bobs, resulting in significantly lower average secret key rates compared to matched pairs. To address this, a novel algorithm is proposed to dynamically balance key consumption rates and optimize the weighted sum of key generation rates while considering system constraints. The evaluation highlights the potential for reducing the required number of QKD pairs from ~N^2 to ~N by utilizing a dynamically switched QKD network.
In this experiment, a commercial Quantum-Key-Distribution (QKD) system from Toshiba was integrated into a carrier-grade Fiber to the Home (FTTH) optical access network. The setup replicated real-life FTTH deployments with a 1:16 user GPON configuration. The QKD transmission occurred over a total of 4km consisting of two spitting stages. By optimizing transmission powers, a QKD link with 17 kbps Secure Key Rate (SKR) and 4.63% Quantum Bit Error Rate (QBER) was achieved, while maintaining 9 operational ONTs providing high-speed internet services. This successful demonstration showcases the feasibility of QKD over a GPON, enhancing access network security.
In this study a feasibility analysis of a satellite-to-ground QKD link employing the Decoy-State BB84 protocol for both LEO and MEO satellite constellations is presented. Considering realistic atmospheric conditions and system assumptions, a comparison of the QKD performance between low and medium satellite orbits over an existing OGS network is reported.
Quantum networks have been shown to connect users with full-mesh topologies without trusted nodes. We present advancements on our scalable polarisation entanglement-based quantum network testbed, which has the ability to perform protocols beyond simple quantum key distribution. Our approach utilises wavelength multiplexing, which is ideal for quantum networks across local metropolitan areas due to the ease of connecting additional users to the network without increasing the resource requirements per user. We show a 10 user fully connected quantum network with metropolitan scale deployed fibre links, demonstrating polarisation stability and the ability to generate secret keys over a period of 10.8 days with a network wide average-effective secret key rate of 3.38 bps.
The performance of quantum key distribution (QKD) is heavily dependent on the physical properties of the channel over which it is executed. Propagation losses and perturbations in the encoded photons’ degrees of freedom, such as polarisation or phase, limit both the QKD range and key rate. The maintenance of phase coherence over optical fibres has lately received considerable attention as it enables QKD over long distances, e.g., through phase-based protocols like Twin-Field (TF) QKD. While optical single mode fibres (SMFs) are the current standard type of fibre, recent hollow core fibres (HCFs) could become a superior alternative in the future. Whereas the co-existence of quantum and classical signals in HCF has already been demonstrated, the phase noise resilience required for phase-based QKD protocols is yet to be established. This work explores the behaviour of HCF with respect to phase noise for the purpose of TF-QKD-like protocols. To achieve this, two experiments are performed. The first, is a set of concurrent measurements on 2 km of HCF and SMF in a double asymmetric Mach-Zehnder interferometer configuration. The second, uses a TF-QKD interferometer consisting of HCF and SMF channels. These initial results indicate that HCF is suitable for use in TF-QKD and other phase-based QKD protocols.
As optical interconnects data rates increases, the Opto–Electro–Optical (OEO) conversion in the ports of the traditional electronic packet switches (EPS) will not be an acceptable solution anymore because of lack of scalability, high cost and excess losses [9]. High speed and scalable optical switches could replace EPS and completely eliminate the need for the OEO conversion. Free–Space Optical (FSO) switches such as Micro ElectroMechanical System switches (MEMS) have high scalability but low switching speed [2]. Whereas, photonic integrated circuit (PIC) switches have shown high switching speed which ranges from some nanoseconds to 10s of microseconds but low scalability with up to 32 ports [6]. The perfect switch would combine the high scalability and high switching speed of the FSO and PIC switches, respectively. In this communication, a novel PIC switch architecture is presented to use grating couplers and their ability to diffract light to the free space. Grating couplers are facing each other and are used as transmitting and receiving nanoantennas. The switch has one input transmitting and four output receiving nanoantennas. The angle of emission of the diffracted beam depends on the wavelength which ranges from 1.3 to 1.55μm. Tuning the wavelength, the beam is steered to one of the receiving nanoantennas. The results monitoring the nanoantennas S parameters reveal satisfactory coupling between the input and output ports with insertion losses in the range between -6 to -8dB, while the interchannel crosstalk isolation from the other ports is less than -9dB from the value of coupling.
Quantum Key Distribution (QKD) technology has been considered as the ultimate physical layer security due to its dependencies on the physical laws of physics to generate quantum keys. However, for QKD to become functional for practical scenarios, it must be integrated with the classical optical networking infrastructure. Coping with optical nonlinearity from the classical represents a major challenge for QKD systems. In this paper, we take the advantage of the ultra-low nonlinearity of Hollow Core Nested Antiresonant Nodeless Fibre (HC-NANF) to demonstrate the coexistence of discrete-variable quantum key distribution channel with carrier-grade classical optical channels over a 2 km HC-NANF.
Silicon nitride (SiNx), has been widely regarded as a CMOS photonics enabling material, facilitating the development of low-cost CMOS compatible waveguides and related photonic components. We have previously developed an NH3-free SiN PECVD platform in which its optical properties can be tailored. Here, we report on a new type of surface-emitting nitrogen-rich silicon nitride waveguide with antenna lengths of L < 5 mm. This is achieved by using a technique called small spot direct ultraviolet writing, capable of creating periodic refractive index changes ranging from -0.01 to -0.04. With this arrangement, a weak antenna radiation strength can be achieved, resulting in far-field beam widths < 0.0150, while maintaining a minimum feature size equal to 300 nm, which is compatible with DUV scanner lithography.
Quantum networks have begun to connect many users together with Quantum Key Distribution links. We present a scalable, full mesh, polarisation entanglement-based quantum network without trusted nodes. We discuss our progress towards building a dynamic quantum network with more users, long distance (≈50 km) links and improved polarisation stability in the optical fibres. Lastly, minimising the resource overhead and optimising the network control based on end-user requirements are important features we are incorporating into our network.
Multi-socket server boards have emerged to increase the processing power density on the board level and further flatten the data center networks beyond leaf-spine architectures. Scaling however the number of processors per board puts current electronic technologies into challenge, as it requires high bandwidth interconnects and high throughput switches with increased number of ports that are currently unavailable. On-board optical interconnection has proved the potential to efficiently satisfy the bandwidth needs, but their use has been limited to parallel links without performing any smart routing functionality. With CWDM optical interconnects already a commodity, cyclical wavelength routing proposed to fit the datacom for rack-to-rack and board-to-board communication now becomes a promising on-board routing platform. ICT-STREAMS is a European research project that aims to combine WDM parallel on-board transceivers with a cyclical AWGR, in order to create a new board-level, chip-to-chip interconnection paradigm that will leverage WDM parallel transmission to a powerful wavelength routing platform capable to interconnect multiple processors with unprecedented bandwidth and throughput capacity. Direct, any-to-any, on-board interconnection of multiple processors will significantly contribute to further flatten the data centers and facilitate east-west communication. In the present communication, we present ICT-STREAMS on-board wavelength routing architecture for multiple chip-to-chip interconnections and evaluate the overall system performance in terms of throughput and latency for several schemes and traffic profiles. We also review recent advances of the ICT-STREAMS platform key-enabling technologies that span from Si in-plane lasers and polymer based electro-optical circuit boards to silicon photonics transceivers and photonic-crystal amplifiers.
As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption.
Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on–chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.
At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.
Hybrid integration on Silicon-on-Insulator (SOI) has emerged as a practical solution for compact and high-performance
Photonic Integrated Circuits (PICs). It aims at combining the cost-effectiveness and CMOS-compatibility benefits of the
low-loss SOI waveguide platform with the versatile active optical functions that can be realized by III-V photonic
materials. The utilization of SOI, as an integration board, with μm-scale dimensions allows for an excellent optical mode
matching between silicon rib waveguides and active chips, allowing for minimal-loss coupling of the pre-fabricated IIIV
components. While dual-facet coupling as well as III-V multi-element array bonding should be employed to enable
enhanced active on-chip functions, so far only single side SOA bonding has been reported. In the present
communication, we present a novel integration scheme that flip-chip bonds a 6-SOA array on 4-μm thick SOI
technology by coupling both lateral SOA facets to the waveguides, and report on the experimental results of wavelength
conversion operation of a dual-element Semiconductor Optical Amplifier – Mach Zehnder Interferometer (SOA-MZI)
circuit. Thermocompression bonding was applied to integrate the pre-fabricated SOAs on SOI, with vertical and
horizontal alignment performed successfully at both SOA facets. The demonstrated device has a footprint of 8.2mm x
0.3mm and experimental evaluation revealed a 12Gb/s wavelength conversion operation capability with only 0.8dB
power penalty for the first SOA-MZI-on-SOI circuit and a 10Gb/s wavelength conversion operation capability with 2 dB
power penalty for the second SOA-MZI circuit. Our experiments show how dual facet integration can significantly
increase the level of optical functionalities achievable by flip-chip hybrid technology and pave the way for more
advanced and more densely PICs.
We present the first characterization results of some cascaded interleavers that we have recently fabricated on 4 μm thick Silicon on Insulator (SOI) wafers. The filters are based on strip waveguides, micron-scale bends and compact MMIs, all components with low loss and high tolerance to fabrication errors, due to the high mode confinement in the silicon region. A thorough comparison of the found results with the theoretical model will be presented, taking into account fabrication limitations. The fabricated filters will be used in the optical RAM circuits of the RAMPLAS project funded by the European Commission.
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.
Towards achieving a functional RAM organization that reaps the advantages offered by optical technology, a complete set of optical peripheral modules, namely the Row (RD) and Column Decoder (CD) units, is required. In this perspective, we demonstrate an all-passive 2×4 optical RAM RD with row access operation and subsequent all-passive column decoding to control the access of WDM-formatted words in optical RAM rows. The 2×4 RD exploits a WDM-formatted 2-bit-long memory WordLine address along with its complementary value, all of them encoded on four different wavelengths and broadcasted to all RAM rows. The RD relies on an all-passive wavelength-selective filtering matrix (λ-matrix) that ensures a logical ‘0’ output only at the selected RAM row. Subsequently, the RD output of each row drives the respective SOA-MZI-based Row Access Gate (AG) to grant/block the entry of the incoming data words to the whole memory row. In case of a selected row, the data word exits the row AG and enters the respective CD that relies on an allpassive wavelength-selective Arrayed Waveguide Grating (AWG) for decoding the word bits into their individual columns. Both RD and CD procedures are carried out without requiring any active devices, assuming that the memory address and data word bits as well as their inverted values will be available in their optical form by the CPU interface. Proof-of-concept experimental verification exploiting cascaded pairs of AWGs as the λ-matrix is demonstrated at 10Gb/s, providing error-free operation with a peak power penalty lower than 0.2dB for all optical word channels.
Semiconductor optical amplifiers (SOAs) are a well-established solution of optical access networks. They could prove an
enabling technology for DataCom by offering extended range of active optical functionalities. However, in such costand
energy-critical applications, high-integration densities increase the operational temperatures and require powerhungry
external cooling. Taking a step further towards improving the cost and energy effectiveness of active optical
components, we report on the development of a GaInNAs/GaAs (dilute nitride) SOA operating at 1.3μm that exhibits a
gain value of 28 dB and combined with excellent temperature stability owing to the large conduction band offset
between GaInNAs quantum well and GaAs barrier. Moreover, the characterization results reveal almost no gain
variation around the 1320 nm region for a temperature range from 20° to 50° C. The gain recovery time attained values as short as 100 ps, allowing implementation of various signal processing functionalities at 10 Gb/s. The combined
parameters are very attractive for application in photonic integrated circuits requiring uncooled operation and thus
minimizing power consumption. Moreover, as a result of the insensitivity to heating issues, a higher number of active
elements can be integrated on chip-scale circuitry, allowing for higher integration densities and more complex optical
on-chip functions. Such component could prove essential for next generation DataCom networks.
We present novel deeply etched functional components, fabricated by multi-step patterning in the frame of our 4 μm
thick Silicon on Insulator (SOI) platform based on singlemode rib-waveguides and on the previously developed rib-tostrip
converter. These novel components include Multi-Mode Interference (MMI) splitters with any desired splitting
ratio, wavelength sensitive 50/50 splitters with pre-filtering capability, multi-stage Mach-Zehnder Interferometer (MZI)
filters for suppression of Amplified Spontaneous Emission (ASE), and MMI resonator filters. These novel building
blocks enable functionalities otherwise not achievable on our SOI platform, and make it possible to integrate optical
RAM cell layouts, by resorting to our technology for hybrid integration of Semiconductor Optical Amplifiers (SOAs).
Typical SOA-based RAM cell layouts require generic splitting ratios, which are not readily achievable by a single MMI
splitter. We present here a novel solution to this problem, which is very compact and versatile and suits perfectly our
technology. Another useful functional element when using SOAs is the pass-band filter to suppress ASE. We pursued
two complimentary approaches: a suitable interleaved cascaded MZI filter, based on a novel suitably designed MMI
coupler with pre-filtering capabilities, and a completely novel MMI resonator concept, to achieve larger free spectral
ranges and narrower pass-band response. Simulation and design principles are presented and compared to preliminary
experimental functional results, together with scaling rules and predictions of achievable RAM cell densities. When
combined with our newly developed ultra-small light-turning concept, these new components are expected to pave the
way for high integration density of RAM cells.
Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.
In the present communication we discuss recent advances in the development of Semiconductor optical amplifier (SOA)-based interferometric optical gates and their use through the implementation of functional high-speed optical systems.
SOA Mach-Zehnder interferometers (SOA-MZI) show great potential for being used as fundamental building blocks in
developing intelligent high speed all-optical sub-systems. In this context we discuss the development of optical systems
that perform diverse and non-trivial network functionalities that find application in Optical Packet/Burst Switching
networks (OPS/OBS). The use of generic building blocks to develop a variety of optical sub-systems is essential, as this
avoids the requirement for custom-made technological solutions and allows for a common fabrication procedure for all
subsystems.
In this context, we discuss latest research on integration of arrays of such optical switches onto the same photonic chip
using hybrid integration technology. The development of such arrays reduces the cost of photonic devices by sharing the
packaging and pigtailing costs. By using an integrated quadruple array of SOA-MZI switches we demonstrate the front-end
unit of an All-optical Label Switched node that performs clock recovery, data recovery and label/payload separation,
and a scalable Time Slot Interchanger (TSI), proving the multi-functionality and processing power of such device. Both
functional systems exhibit comparable performance compared to implementations using single switches with
significantly lower device costs. The cost reduction offered by the integration of multiple switches on the same chip is
also evident in high-speed WDM networks, where multi-wavelength regeneration can be achieved with the use of several
integrated switch arrays.
We report an all-optical module that performs simultaneous header separation and reinsertion in 10-Gbit/s short optical packets of variable payload length and that consists of two subunits. The first uses a Fabry-Perot filter and an ultrafast nonlinear interferometer (UNI) to perform packet clock recovery. The second is a UNI gate configured as a 2×2 exchange bypass switch that is optically controlled by the recovered clock packets. Using fixed delays, the data packets and the locally generated headers are fed into the 2×2 switch, where header replacement is achieved.
An all-optical Boolean XOR gate implemented with a semiconductor-optical-amplifier (SOA)-based Mach-Zehnder interferometer (SOA-MZI) is numerically simulated at 10 Gbits/s to extract simple design rules. If the control and clock energies and the small signal gain are properly selected, the metrics that define the quality of switching can be optimized for high gate performance.
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