Ms. Greet Storms Profile

Greet Storms

Sr. Director High NA EUV Product Management at ASML Netherlands BV

SPIE Involvement:

Author

Publications (14)

Proceedings Article | 13 November 2024 Presentation

High-resolution lithography: latest generation in EUV lithograph with 0.55 NA

Aysegul Cumurcu Gysen, Cheuk-Wah Man, Bas van Meerten, Hilbert van Loo, Eelco van Setten, Stefan Smith-Meerman, Gokay Yegen, Diederik de Bruin, Jan van Schoot, Rudy Peeters, Kaustuve Bhattacharyya, Greet Storms, Peter Vanoppen

Proceedings Volume PC13215, PC1321505 (2024) https://doi.org/10.1117/12.3036955

KEYWORDS: Extreme ultraviolet, Lithography, Metals, Extreme ultraviolet lithography, Design, Chip manufacturing, Overlay metrology, Optical lithography

Read Abstract +

Proceedings Article | 10 April 2024 Presentation + Paper

The next step in Moore’s law: high-NA EUV introduction at the customer

J. Santaclara, Rudy Peeters, Rob van Ballegoij, Sjoerd Lok, Jan van Schoot, Paul Graeupner, Peter Kuerz, Joerg Mallmann, Greet Storms, Peter Vanoppen

Proceedings Volume 12953, 129530P (2024) https://doi.org/10.1117/12.3009070

KEYWORDS: Extreme ultraviolet, Semiconducting wafers, System integration, Reticles, Image sensors, Optical proximity correction, Mirrors, Metrology, Lithography, Ecosystems

Read Abstract +

Proceedings Article | 22 November 2023 Presentation

Enabling the next step for on-product performance with high-NA EUV system

Kaustuve Bhattacharyya, Diederik de Bruin, Rudy Peeters, Jara Santaclara, Herman Heijmerikx, Rob van ballegoij, Eelco van Setten, Jan van Schoot, Sjoerd Lok, Greet Storms

Proceedings Volume PC12750, PC1275003 (2023) https://doi.org/10.1117/12.2687701

KEYWORDS: Extreme ultraviolet, Imaging systems, Semiconductors, Overlay metrology, Industry

Read Abstract +

Proceedings Article | 16 November 2022 Presentation

Evolutionary step in EUV technology with high NA

Kaustuve Bhattacharyya, Rudy Peters, Greet Storms, Diederik de Bruin, Jara Santaclara, Rob van Ballegoij, Eelco van Setten, Teun van Gogh

Proceedings Volume PC12292, PC1229201 (2022) https://doi.org/10.1117/12.2644966

KEYWORDS: Extreme ultraviolet, Semiconductors, New and emerging technologies, Logic, Lithography, EUV optics

Read Abstract +

Proceedings Article | 13 June 2022 Presentation

High NA EUV enabling cost efficient scaling for N+1 technology nodes

Greet Storms, Sjoerd Lok, Rob van Ballegoij, Jan van Schoot, Rudy Peeters, Diederik de Bruin, Kars Troost, Teun van Gogh

Proceedings Volume PC12051, PC1205104 (2022) https://doi.org/10.1117/12.2617240

KEYWORDS: Extreme ultraviolet, Semiconductors, Lithography, Logic, EUV optics

Read Abstract +

Proceedings Article | 24 March 2016 Paper

A study of swing-curve physics in diffraction-based overlay

Kaustuve Bhattacharyya, Arie den Boef, Greet Storms, Joost van Heijst, Marc Noot, Kevin An, Noh-Kyoung Park, Se-Ra Jeon, Nang-Lyeom Oh, Elliott McNamara, Frank van de Mast, SeungHwa Oh, Seung Yoon Lee, Chan Hwang, Kuntack Lee

Proceedings Volume 9778, 97781I (2016) https://doi.org/10.1117/12.2222040

KEYWORDS: Accuracy assessment, Overlay metrology, Physics, Image processing, Process control, Optical properties, Polarization, Metrology, Inspection, Diffraction gratings, Semiconducting wafers, Computer simulations, Diffraction, Detection theory

Read Abstract +

Proceedings Article | 2 April 2014 Paper

Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)

Kai-Hsiung Chen, GT Huang, KS Chen, C. Hsieh, YC Chen, CM Ke, TS Gau, YC Ku, Kaustuve Bhattacharyya, Jacky Huang, Arie den Boef, Maurits v. d. Schaar, Martijn Maassen, Reinder Plug, Youping Zhang, Steffen Meyer, Martijn van Veen, Chris de Ruiter, Jon Wu, Hua Xu, Tatung Chow, Charlie Chen, Eric Verhoeven, Pu Li, Paul Hinnen, Greet Storms, Kelvin Pao, Gary Zhang, Christophe Fouquet, Takuya Mori

Proceedings Volume 9050, 90500S (2014) https://doi.org/10.1117/12.2047098

KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Back end of line, Scanners, Diffraction, Front end of line, Process control, Etching

Read Abstract +

Proceedings Article | 2 April 2014 Paper

CD uniformity optimization at volume ramp up stage for new product introduction

Jin-Soo Kim, Won-Kwang Ma, Young-Sik Kim, Myoung-Soo Kim, Won-Taik Kwon, Sung-Ki Park, Peter Nikolsky, Marian Otter, Maryana Escalante Marun, Roy Anunciado, Kyu-Tae Sun, Greet Storms, Ewould van West

Proceedings Volume 9050, 905037 (2014) https://doi.org/10.1117/12.2057390

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Yield improvement, Semiconductors, Etching, Photoresist processing, Optical lithography, Process control, Overlay metrology, Manufacturing

Read Abstract +

Proceedings Article | 5 April 2007 Paper

Advanced process control for hyper-NA lithography based on CD-SEM measurement

T. Ishimoto, K. Sekiguchi, N. Hasegawa, T. Maeda, K. Watanabe, G. Storms, D. Laidler, S. Cheng

Proceedings Volume 6518, 65182P (2007) https://doi.org/10.1117/12.710814

KEYWORDS: Lithography, Critical dimension metrology, Process control, Precision measurement, Semiconducting wafers, Scanning electron microscopy, Electroluminescence, Metrology, Finite element methods, Resolution enhancement technologies

Read Abstract +

With the recent introduction of immersion lithography, optical systems with numerical aperture (NA) reaching 1.0 or larger can be realized. Various Resolution Enhancement Techniques (RET) such as various phase shift mask approaches have been used to push even further the resolution limit by reducing k₁ scaling factor, including Double Patterning Technology. However, with the improved resolution by Hyper-NA and Low-k₁, lithographers face the problem of decreasing Depth of Focus and in turn reduced process latitude. Throughout the industry, Process Window has been widely used as an analytical tool to evaluate process latitude for a given design feature size; therefore, the ability to accurately and efficiently derive a Process Window within which a process can run on target and in control is fundamental to Low-k₁ lithography. Accuracy of Process Window derivation is based on the ability to accurately measure and model the physical dimension of the design feature and how it changes in response to changes in process parameters. In the case of lithography, the Process Window of a desired critical dimension target is bounded by changes in exposure energy and defocus. To be able to accurately measure the physical dimension of the design feature remains a big challenge for metrologists especially in the presence of other process noise. In this work, it is shown that the precision of PW measurement can be enhanced by using CD-ACD (Average CD) function to measure a FEM (Focus-Exposure matrix) wafer. ACD is a function, which simultaneously measures several points, thus providing higher precision measurement in comparison to the conventional single point measurement. As seen in this work, by using ACD measurements to derive the Process Window, there is a significantly improvement in the stability of the derived Process Window. Also reported is the MPPC (Multiple Parameters Profile Characterization) ^*1), a function which provides the ability to extract pattern shape information from a measured e-beam signal. This function together with the ACD function enables PW measurement with high precision, which also takes into account the actual pattern shape. PW derived from conventionally measured data was compared with PW derived from ACD and MPPC measurement and we were able to demonstrate an improvement of more than 30% in precision of PW determination.

Proceedings Article | 27 March 2007 Paper

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

Mircea Dusa, John Quaedackers, Olaf Larsen, Jeroen Meessen, Eddy van der Heijden, Gerald Dicker, Onno Wismans, Paul de Haas, Koen van Ingen Schenau, Jo Finders, Bert Vleeming, Geert Storms, Patrick Jaenen, Shaunee Cheng, Mireille Maenhoudt

Proceedings Volume 6520, 65200G (2007) https://doi.org/10.1117/12.714278

KEYWORDS: Etching, Semiconducting wafers, Double patterning technology, Optical lithography, Overlay metrology, Critical dimension metrology, Lithography, Neodymium, Photomasks, Manufacturing

Read Abstract +

Proceedings Article | 24 March 2006 Paper

An integrated approach to the determination of a manufacturable process window in advanced microlithography

Marcelo Cusacovich, John Robinson, Shaunee Cheng, Greet Storms, Philippe Leray, Gian Lorusso

Proceedings Volume 6152, 615231 (2006) https://doi.org/10.1117/12.656503

KEYWORDS: Metrology, Scanning electron microscopy, Semiconducting wafers, Manufacturing, Finite element methods, Lithography, Resolution enhancement technologies, Design for manufacturing, Electroluminescence, Process control

Read Abstract +

Proceedings Article | 15 March 2006 Paper

Immersion effects on lithography system performance

Seiji Nagahara, Ivan Pollentier, Takahiro Machida, Sean O'Brien, Eric Jacobs, Charles Schaap, Philippe Leray, Greet Storms, Kathleen Nafus, David Laidler, Shaunee Cheng

Proceedings Volume 6154, 61540U (2006) https://doi.org/10.1117/12.659620

KEYWORDS: Semiconducting wafers, Thin film coatings, Scanners, Temperature metrology, Reticles, Immersion lithography, Scatterometry, Lithography, Overlay metrology, Scatter measurement

Read Abstract +

The immersion effects on lithography-system performance have been investigated using a ASML TWINSCAN XT:1250Di immersion-ArF scanner (NA=0.85) and Tokyo Electron CLEAN TRACK ACT12 at IMEC. Effects of immersion-induced-temperature change and effects of material-top surface are discussed in this paper. The wafer-stage temperature is measured during the leveling-verification tests and compared with the observed residual-focus-error change. The results indicate that stage-temperature change under an immersion environment can induce a focus change. In this paper, it was proved that the improved-temperature-control stage is effective to mitigate the immersion-specific focus change. The immersion effect on overlay is also investigated as a function of material top surface. It was demonstrated that the effect of material-receding-contact angles on the grid-residual errors (non-correctable errors) is small in the latest-immersion-hardware configuration of the scanner. However, there was a tendency that material with a smaller-receding-contact angle has a larger-wafer scaling although it is a correctable parameter. This can be caused by the first-layer wafer shrinkage due to more water evaporation on the more-hydrophilic surface. The immersion effect on scanner-dynamic performance is then investigated by changing the material-top surface and the scan speed of the scanner. It was turned out that the scan synchronization is not much affected by differences of material receding-contact-angles for the new configuration of the scanner. Moving-standard deviation of the synchronization error in scanning direction (y-direction) is slightly more affected by increased scanning speed, although it stays within specification even at a maximum scan speed of 500 mm/sec. Finally the immersion effects on resist-profile uniformity are examined. It was found that lower-leaching-film stacks (with a top coat or a lower leaching resist) seem to mitigate the variation of resist-profile uniformity.

Proceedings Article | 10 May 2005 Paper

90nm technology contact CD performance characterization via ODP scatterometry

Kelly Barry, Shaunee Cheng, Greet Storms

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.600176

KEYWORDS: Critical dimension metrology, Metrology, Scanning electron microscopy, Cadmium, Semiconducting wafers, 3D metrology, Scatterometry, Lithography, Silicon carbide, Silicon

Read Abstract +

Proceedings Article | 24 May 2004 Paper

Electrical linewidth metrology for sub-65-nm applications

Greet Storms, Shaunee Cheng, Ivan Pollentier

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.537346

KEYWORDS: Tin, Metrology, Resistance, Etching, Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Process control, Calibration, Resistors

Read Abstract +

Showing 5 of 14 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years