Modern semiconductor fabrication pushes the limits of chemistry and physics while simultaneously employing largescale, cutting-edge processing techniques. While fab expansion and capital expenditures continue to grow, the human element has become ever more demanding and prone to error. To assist with this issue, computer-aided process engineering, process control, and tool monitoring will continue to rise in the coming years. In this paper, we present an APC-integrated, customizable solution to an in-fab processing segment. Through machine learning, we combine information from design-specific extracted features with processing and metrology data to predict oxide deposition thickness. The result is a design-aware augmentation for current metrology that can recommend accurate process recipe conditions for new layouts. We also present experimental results highlighting the benefits of adding design-aware features with in-fab data to anchor and support each other across layouts and technologies. This result paves the way to decouple, isolate, and quantify the individual influences each processing step imposes on different designs at various stages of the fabrication flow.
Semiconductor foundries typically analyze design layouts for criticality as a precursor to manufacturing flows. Risk assessment is performed on incoming layouts to identify and react to critical patterns at an early stage of the manufacturing cycle, in turn saving time and efforts. In this paper, we describe a new bottom-up approach to layout risk assessment that can rapidly identify unique patterns in layouts, and in combination with techniques like feature filters, location mapping and clustering, can pre-determine their criticality. A massive highly performant pattern database of single and multilayer patterns, along with their features and locations, forms the core of the system. While pattern analyses may be pertaining to the short range of design space, silicon defects and simulations extend to a much larger scope. Therefore, the database is extended to defect data extracted from Silicon inspection tools like Bright Field Inspection (BFI) and Scanning Electron Microscopy (SEM). When stored in an optimized manner, it can aid fast and efficient large data analysis and machine learning within critical tapeout review time which is typically a few days. Machine learning combined with design feature filters can then be used for anomaly detection and failure prediction at layout, layer and pattern levels. As a result, outlier patterns can be visually reviewed and flagged for custom targeted simulations and silicon inspection. Further, adding new layout patterns to the pattern database will make it possible to repeat this exercise for subsequent new layouts.
Lithography process variation as well as etch and topography have always been a stubborn challenge for advanced technology nodes, i.e. 14nm and beyond. This variability usually results in defects aggregating around the edge of the wafer and leading to yield loss. A very tight process control is the logical resolution for such issues, nevertheless it might not be possible, or it may slow down the whole design to silicon cycle time. Another degree of difficulty is detecting these defects in ORC and concluding an OPC fix. In this paper, we show that aerial image ORC checks could provide a very useful insight to these defects ahead of time, and that they correlate well with silicon defects highlighted by CFM scan. This early detection upstream enables us to conclude a generic OPC fix for such issues and also improves the total OPC process-window enhancement and eliminates these defects on silicon.
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