In short channel MOSFETs (metal oxide semiconductor field effect transistors), the effective channel length can be substantially shortened, leading to a slope in the saturated I-V characteristic that is analogous to the Early effect for BJT. These SCE(short channel effect) problems have been solved using the LDD(lightly doped drain) structure, but can't be completely solved at nano scale gate. To complete weakness of LDD, we have designed the MOSFET which has the DG(double gate) structure. For comparing LDD with DG MOSFETs, we have used the TCAD simulator. The structures of LDD and DG MOSFETs have been designed and simulated by the DIOS tool and the electrical characteristics simulated by the DESSIS tool in TCAD. The I-V characteristic is not good in LDD but it is very excellent in DG MOSFET of sub-50nm gate.
In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model (QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll-off characteristics for threshold voltage of MOSFET with decreasing channel length, we know α value must be nearly 1 in the generalized scaling.
In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (MG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 2V in the main gate 50nm. Also, we know that optimum side gate length for each main gate length is 70nm above. DG MOSFET shows a small threshold voltage (Vth) roll-off. From the I-V characteristics, we obtained IDsat=510μA/μm at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86mV/decade, transconductance is 111μA/V and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Also, we have presented that TCAD simulator is suitable for device simulation.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.