Wenli Collison, Yii-Cheng Lin, Shannon Dunn, Hiroaki Takikawa, James Paris, Lucy Chen, Troy Detrick, Jun Belen, George Stojakovic, Michael Goss, Norman Fish, Minjoon Park, Chih-Ming Sun, Mark Kelling, Pinyen Lin
In the Global 450mm Equipment Development Consortium (G450C), a 193i guided directed self-assembly (DSA) pattern has been used to create structures at the 14nm node and below. The first guided DSA patterned wafer was ready for etch process development within a month of the G450C’s first 193i patterned wafer availability with one litho pass. Etch processes were scaled up from 300mm to 450mm for a 28nm pitch STI stack and a 40nm pitch M1 BEOL stack. The effects of various process parameters were investigated to fine tune each process. Overall process window has been checked and compared. Excellent process stability results were shown for current etch chambers.
Double patterning is one of the most promising techniques for sub-30nm half pitch device manufacturing. Several
techniques such as dual-trench process (litho-etch-litho-etch: LELE) and dual-line process (litho-litho-etch : LLE) have
been reported. Between them, the dual-line process attracts a great deal of attention due to its higher throughput. The key
issue in the dual-line process is preventing damage of the first resist pattern during the second lithography process. As a
solution, we have developed a process to alleviate this issue using a chemical material called "freezing agent." More
recently, we have further simplified the process by developing a simple freezing technique called "self-freezing" or
"thermal-freezing." The "self-freezing resist" material can accomplish the freezing process by applying only one bake to
the resulting first pattern. In addition, our self-freezing resist also has added water shedding properties to meet non-topcoat
(non-TC) immersion resist requirements, which further simplifies the process and materials.
In this study, imaging results of Non-TC self-freezing resist including critical dimension uniformity, defectivity and
processing properties of the resulting patterns is shown.
In this paper, alignment and overlay results on processed short-flow wafers are presented. The impact of various mark designs on overlay performance was investigated, using a newly developed phase grating wafer alignment sensor concept. This concept is especially suited to support mark design flexibility, as well as to further improve upon the performance of the alignment sensors currently known. The unique sensor concept allows for alignment to a large variety of marks layouts, thereby complying with customer specific alignment mark design requirements.
Here, we present alignment performance results on Toshiba's new marks. For this purpose, the new alignment sensor was integrated in an ASML proto-type tool. Alignment performance on ASML default mark types was demonstrated to guarantee backward compatibility with known alignment sensors. Alignment repeatability numbers of <3 nm (3sigma) were obtained for the different mark designs investigated. These numbers were measured on marks in resist as well as on processed short flow lots. Short term overlay capability of <6 nm (mean+3sigma) was demonstrated on Toshiba mark types, and on ASML mark types. Long term overlay values were demonstrated to be below 8 nm (mean + 3sigma) for both mark designs.
The alignment and overlay capability, on processed wafers, was demonstrated for two process modules: Gate-to-Active (GC-AA) and Metal1-to-Contact (M1-CS). Typical overlay values measured were 20 to 30 nm, for the GC-AA and the M1-CS process module respectively. Further improvements with respect to alignment performance and overlay capability are anticipated through the use of advanced applications, and by further optimization of alignment mark design. This will be verified in future joint Toshiba/ASML experiments.
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