The measurement of electrostatic discharge (ESD) tolerance for a capacitive fingerprint sensor LSI in which the sensor is stacked on a 0.5-micrometers CMOS LSI is described. To compare the contact discharge method and air discharge method, we investigated the dependence of the ESD failure voltage on the distance between the sensor surface and ESD electrode for a conventional planar-type fingerprint sensor LSI. The ESD failure voltage decreased as the electrode approached to sensor surface and reached its lowest value when the electrode touched the surface. Therefore, we conclude that the contact discharge method is more suitable for evaluating ESD tolerance for fingerprint sensor LSI because the measurement condition is clearly defined and ESD failure value is the most critical. Moreover, we revealed that our proposed sensor LSI with the grounded wall (GND wall) has high ESD tolerance of over +/- 8.0 kV by the contact discharge method.
Thick-gold-multilevel damascene-interconnect technology makes it possible to fabricate >10-micrometers -feature ultrahigh-speed devices on Si. Adding H2O2 to a conventional KIO3-based slurry triples the removal rate of gold in chemical mechanical polishing (CMP). A ratio of H2O2 to slurry of approximately 1:1 is found to be the optimum for obtaining the highest gold removal rate. X-ray photoelectron spectroscopy (XPS) analyses show that gold is oxidized in spite of its chemical stability when the removal rate is high. The gold is oxidized due to the reduction of iodine at the optimum H2O2 mixture ratio. This CMP of gold enabled us to make a thick (>10 micrometers ) gold-multilevel damascene-interconnection structure for the first time. Integration of full-wafer wafer-bonded uni-traveling carrier photodiodes (UTC-PDs) with the gold multilevel interconnections as coplanar waveguides (CPWs) on a Si wafer has been achieved using this gold-CMP process.
This paper gives an overview of the European ACTS project AC329-ACTUAL. This project was carried out during 1998 and 1999. The stated main objective of the project was: TO sue the state-of-the-art technology on widely tunable lasers available within the Consortium, to bring this to full maturity on a subsystem level and to demonstrate that wavelength agile transmitters based on widely tunable lasers can open the way to the next generation WDM and wavelength switching systems. This paper will give a description of the result from the project.
Microfabrication technologies for use as practical methods in > 10-micrometers featured high-speed device fabrication have been developed: the thick polyimide-used damascene process, electroless plating of Ru/Ni on Cu interconnections, the area-restricted chemical mechanical planarization to polish thick polyimide films. Applying their technologies to fabricate RF-components and millimeter-wave components on Si demonstrates excellent characteristics: high-quality factor (Q-factor) in spiral inductor, low transmission loss for sidewall coplanar waveguide (CPW), high-power radiation in CPW-fed sot antenna. The Si-technology-based approach to achieve seamless integration of different kinds of devices, i.e., photonic devices, ULSIs, RF-devices, and millimeter- wave devices are promising ways to fabricate high-speed systems on Si.
Selective W-CVD technology with hydrogenation and hydrogen- termination treatment was developed to reduce source/drain sheet resistance in ultra-thin-film fully-depleted CMOSFET's/SIMOX, and it was applied to 0.25-micrometer-gate gate-array LSIs. It is clarified that this technology ensures single-contact cells, which are vital for higher packing density, with no degradation of device characteristics, circuit performance, and LSI yield. Moreover, recent results for devices with a W-covered gate/source/drain are presented.
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