Radar target recognition technology is the intersection of radar technology and pattern recognition. It is a technique to extract the information and features related to the target characteristic from the High-Resolution Range Profile (HRRP) and to judge the target attribute. Due to the complexity of radar target recognition algorithm and large amount of data, most of the current research is still focused on algorithm, and few can be implemented on hardware. With the development of microelectronics, System on Chip (SoC) has been widely used. Its powerful data processing capability makes it possible to realize the hardware implementation of radar target recognition. This paper mainly introduces the methods of feature extraction and classifier, and then implements a complete radar target recognition system based on the hardware platform of RF-SOC chip. Experiments show that the classification accuracy of ground targets such as tanks, radar stations and armored vehicles is over 80%.
KEYWORDS: Digital signal processing, Field programmable gate arrays, Particles, Control systems, Signal processing, Radar signal processing, Satellites, Reliability, Radar, Switching
FPGA+DSP architecture is widely used in satellite digital processing systems. The satellite is in an environment where there is a lot of particle radiation and collisions. In order to avoid changes in stored code data brought by SEU (Single Event Upset), improve the system reliability, at the same time meet the current requirements of software on-orbit reconfiguration, the FPGA and DSP in the space-borne core processor need to have the ability of error correction and reconfiguration. To do this, FPGA and DSP programs need to be stored in external, writable memory. Nor Flash, with its high capacity and reliability, is often chosen as the memory for storing code. At present, the on-orbit maintenance of FPGA is usually realized by using Actel FPGA to conduct TMR (Triple Modular Redundancy), refresh and other processing on the FPGA code stored in Flash. Based on this idea, a T-shaped structure is constructed among FPGA, DSP and Flash for the architecture of the space-borne processor. As the master, FPGA controls Flash to complete TMR, error correction and on-orbit reconfiguration of DSP code. This method reduces hardware redundancy, gives consideration to autonomous maintenance and on-orbit reconfiguration, and increases system robustness. This method has been applied and fully verified in orbit.
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