3D NAND flash memory stacks cells vertically in multiple layers. One of the critical processes in chip-making is slit trench landing control since the word-line gate replacement of silicon nitride films and the isolation of plural memory blocks are through the means of slit structure. However, during the gate of silicon nitride removal in slit trenches, the architecture of memory blocks may collapse due to the lack of sufficient supporting patterns surrounding the slit trenches. For better silicon nitride removal control, there are various irregular patterns of dummy pillars (PIL) designed in as supporting structures to provide better mechanical property, which can prevent memory blocks from collapsing while removing silicon nitride in gate replacement processing. Hence, an effective measurement is needed to indicate the bottom shifting of PIL during the etching recipe optimization. In this work, we demonstrate the deployment of small angle X-ray scattering (SAXS) technology with global tilt extraction (GTE) that successfully predicts PIL landing location displacement, which matches destructive gauging data. GTE is a modeless method to determine global tilt, i.e., center line shifting (CLS) of the bottom relative to the topmost on the target pattern. GTE is proven to be a reliable method for in-line process monitoring as well as for use in PIL etching recipe optimization for 3D NAND development.
KEYWORDS: X-rays, Semiconducting wafers, Etching, Metrology, 3D metrology, Back end of line, Scattering, 3D modeling, Transmission electron microscopy, Optical alignment
3D NAND has become mainstream storage devices in a past decade and the stacking cell layers now reaches to more than 300 layers. As stack gets higher, more and more etching process challenges are brought into 3D NAND high aspect ratio (HAR) structure patterning. Among the HAR etching processes, the deep contact etches in the back-end-of-line (BEOL) are patterned after other HAR structures such as channel holes, deep trenches or other dummy patterns. Any unexpected overlapping of deep contacts with other patterns would lead to fatal product yield loss due to such wrong circuit connections and leakage currents. Hence, a reliable and fast monitoring methodology for profile tilting is extremely important. In this article, it is first time to demonstrate the employment of the small angle x-ray scattering (SAXS) technology and global tilt extraction (GTE) by using Axion @TM from KLA-Tencor to measure bottom tilting behavior for deep contact structure in 200+ layers of 3D NAND product. As regarding for the necessaries of gathering layout pitch, detail film stacks and hole dimensions by regular model base approach, the GTE is a pure modeless method by using x-ray scattering images to determine the central point shifting of the bottom relative to the topmost on the target pattern. With GTE help, the development cycle time for etch recipe tuning and BEOL process optimization is effectively improved, as well as demonstrating better process control to sustain product yield.
KEYWORDS: Overlay metrology, Single crystal X-ray diffraction, Metrology, Semiconducting wafers, 3D metrology, Control systems, Process modeling, Polishing, Etching, Image processing
As device dimensions continuously shrink in semiconductor manufacturing, even tighter overlay control is indispensable to secure good device yield. Using traditional optical overlay metrology via scribe-lane marks it is challenging to achieve good intra-field high-order process correction (iHOPC) due to the limited mark count and uneven mark distribution. Also the scribe-lane based metrology may not fully represent the in-device behavior in some cases. In order to achieve improved accuracy and precision of in-device overlay control, new metrology methodology solution is required. In this paper, three complementary overlay metrology techniques – high voltage scanning electron microscope (HV-SEM), optical scatterometry critical dimension measurement (SCD), and traditional scribe-lane based optical overlay metrology – were adopted for in-device overlay improvement. In 3D NAND device production, in-device overlay measurement is getting more challenging due to the thicker or complex film stack. Though both HV-SEM and SCD are able to measure in-device patterns via capturing buried structures, their different tool principles make them suitable in different situations. Through applying non-zero offset (NZO) overlay compensation at photo exposure, the in-device overlay performance can be enhanced by iHOPC, which is enabled by incorporating high-density in-device sampling measurements from HV-SEM and SCD into traditional optical scribe-lane optical overlay measurements. The improved overlay performance was demonstrated for different process layers in this study.
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