The use of junction isolation in linear bipolar ICs substantially consumes silicon area. The replacement of junction isolation with trench isolation has the potential to significantly reduce device area while maintaining high voltage operation. Deep trench isolation has been implemented on a conventional non- complementary 40V (NPN BVceo) linear IC process. A fully functional lower power operational amplifier has been fabricated as a technology driver. Device characterization shows that transistor leakage currents (Iceo) and leakage between trench tubs can be made comparable with junction isolated devices. The NPN buried layer can successfully be butted against the trench sidewall without device degradation, although this is currently not possible with the NPN base. An NPN device shrink of 3X has been achieved and further development is underway to increase this towards the 4X level, where the base diffusion front touches the trench sidewall.
This paper examines the relative etching rates of doped and thermal silicon dioxide when using NSSL etchant, comprising of a mixture of ammonium fluoride, water and ammonium dihydrogen phosphate [(NH4)H2PO4] and investigates their dependence on both temperature and mixture composition. The possible reaction mechanism is discussed and compared with the known mechanism for standard buffered oxide etchants (BOE). The observed etch selectivity and mechanisms of BOE and NSSL are also compared with the behavior of a third chemical formulation, referred to as mixed oxide etchant, which comprises of ammonium fluoride (NH4F) solution, diammonium hydrogen phosphate [(NH4)2HPO4] and orthophosphoric acid (H3PO4). It is concluded that no major change in oxide selectivity is observed if either BOE or NSSL etchants are used in the metal pre-clean process.
A uniform TEGAL 903E plasma oxide etch process, has been developed using a novel analytical technique. The process has been implemented successfully in the manufacturing arena. The novel analytical technique involves executing statistically designed experiments, then visually analyzing wafer uniformity topography maps. Modeling uniformity is usually done using a summary metric of standard deviation or normalized max-min values. This work demonstrates a weakness in this approach and presents a new strategy.
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