Turn around time (TAT) of mask qualification is one of the most important factors for high-end mask installation to
LSI production lines. Accurate mask qualification with shorter TAT for mask process updates brings about steep rampup
of LSI volume production. In this paper, an innovative approach is described for mask qualification with a die-todatabase
(D2DB) inspection system that can accomplish both qualification accuracy and short TAT in low k1
lithography. The D2DB inspection system, NGR2100[1], has features satisfying the above requirements owing to larger
field of view (FOV) and higher probe current than those of CD-SEM. Compared with the conventional optical inspection
tool, the system provided higher accuracy in extracting fatal defects called "hotspots". Also, hotspots extracted by the
system covered all killer hotspots extracted by electrical and physical analysis [2]. The contours of hotspots extracted by
NGR2100 are transferred to GDS data format to compare hotspots between conventional mask process and updated
mask process. If the differences between the contours are within an assumed tolerance, the system provides the
qualification for updated mask process. As a result, qualification TAT was reduced by as much as two months compared
with the conventional electrical qualification on wafers.
We have constructed hotspot management flow with a die-to-database (D2DB) inspection system for spacer
patterning technologies (SPTs) which are among the strongest candidates in double patterning technologies below 3x nm
half-pitch generations. At SPIE 2006[1], we reported in "Hotspot management" that extracted hotspot by full-chip
lithography simulation could be quickly fed back to OPC, mask making, etc. Since the SPT includes process complexity
from resist patterning to final device patterning, however, it is difficult to exactly estimate hotspots on final patterned
features on wafers by full-chip lithography simulation. Therefore, experimental full-chip inspection methodologies for
hotspots extraction are necessary in order to construct hotspot management for SPTs. In this work, we applied the D2DB
inspection system with electron beam (EB) to SPTs in hotspot management flow. For the D2DB inspection system, the
NGR-2100 has remarkable features for the full-chip inspection within reasonable operating time. This system provides
accurate hotspot extraction by EB with wider field of view (FOV) than that of SEMs. With the constructed hotspot
management flow, extracted hotspots for SPT involving errors of around 10nm could easily be fed back to fix the wafer
processes and mask data.
We constructed hot spot management flow with a die-to-database inspection system that is required for both hot
spot extraction accuracy and short development turn-around-time (TAT) in low k1 lithography. The die-to-database
inspection system, NGR-2100, has remarkable features for the full chip inspection within reasonable operating time.
The system provided higher hot spot extraction accuracy than the conventional optical inspection tool. Also, hot spots
extracted by the system could cover all killer hot spots extracted by electrical and physical analysis. In addition, the new
hot spot extraction methodology employing the die-to-database inspection system is highly advantageous in that it
shortens development TAT by two to four months. In the application to 65nm node CMOS, we verified yield
improvement with the new hot spot management flow. Also, the die-to-database inspection system demonstrated
excellent interlayer hot spot extraction from the viewpoint of LSI fabrication.
We developed the electron beam inspection system based on projection electron microscopy (EBI-PEM), and then
applied this system to inspection of mask defects. Usually, inspection of mask defects (such as monitoring of growing
defects) is carried out with resist pattern on Si wafer by using an optical inspection tool. In recent years, the shrinking of
the design rule for LSI devices has fueled demand for mask inspection for small defects, which are hard to detect with
the resolution of an optical inspection tool. Therefore, a high-resolution electron beam inspection tool is desired.
However, conventional electron beam inspection systems based on scanning electron microscopy (EBI-SEM) require
very long inspection time (10-100 times longer than in the case of optical inspection tool) and inspection costs are very
high. In addition, it is difficult to inspect resist pattern by using an electron beam inspection tool, because of the charge-
up problem.
In order to solve the problem, we examined a new mask inspection method using an electron beam inspection system
based on EBI-PEM. Although, EBI-PEM have an advantage in terms of inspection speed, it is more difficult to inspect
resist pattern by EBI-PEM than by EBI-SEM, because EBI-PEM is very sensitive to charge-up of a sample surface.
Therefore, we tried a method in which inspection is performed after transferring a pattern to SiO2 thin film formed on Si
wafer.
By optimizing the thickness of SiO2 thin film and the electron beam condition of EBI-PEM, we were able to minimize
the influence of charge-up and obtained a higher contrast image. Using this method, EBI-PEM achieved inspection
sensitivity of 35nm in the case of programmed defect wafer. We confirmed the probability of realizing high-speed and
high-resolution mask inspection by using EBI-PEM.
KEYWORDS: Semiconducting wafers, Inspection, Defect detection, Spatial resolution, Scanning electron microscopy, Distortion, Electron beams, Signal detection, Electron microscopy, Neodymium
Electron beam inspection systems based on a scanning electron microscopy (EBI-SEM) had been developed and used for the yield management in the semiconductor process because of its high resolution. However, they have the restriction of inspection speed due to the space charge effect of the electrons in the focused electron beam.
We have been developing the electron beam inspection system based on the projection electron microscopy (EBI-PEM), and reported the results which revealed the possibilities of detecting the defect size of less than 100nm and the data rate 600MPPS, last year. We have further improved the EBI-PEM on its secondary electron optical system (2'nd EO) for obtaining smaller aberrations and distortion. The aberrations and distortion of the improved EBI-PEM optical system have been estimated by calculation using conventional simulation program. Obtained aberration values were small enough than one necessary for attaining the spatial resolution of the target specification and a resolution has been confirmed by the experiments.
KEYWORDS: Inspection, Semiconducting wafers, Electron beams, Signal detection, Optical inspection, Wafer-level optics, Electron microscopy, Spatial resolution, Yield improvement, Imaging systems
Optical inspection systems and/or electron beam inspection systems are quite useful tools for the yield management in the semiconductor process. However, they have some issues of difficulties for the application to the yield management after 100nm-technology node generation. Optical inspection systems have a resolution limit by diffraction phenomena. On the other hand, electron beam inspection systems based on scanning electron microscopy (EBI-SEM) have the limit of inspection speed. Both limits are serious matter for the application to yield management after 100nm-technology node generation. We have developed the electron beam inspection system based on projection electron microscopy (EBI-PEM), having both performances of inspection speed of optical types and spatial resolution of EBI-SEM. The system has been improved on the signal electron collection efficiency and transmittance of the electron optical system. We also have developed high rate and sensitive signal detection system. Then we considered that the inspection speed of several times faster than the conventional EBI-SEM is feasible at the spatial resolution less than 100nm.
The production prototype of an electron beam inspection system based on projection electron microscopy (EBI-PEM) has been developed. Inspection performances of the EBI-PEM were evaluated using the programmed defect standard wafer delivered by SELETE. We confirmed the EBI-PEM had the same inspection speed, 9 cm2/h, as the conventional electron beam inspection system based on scanning electron microscopy (EBI-SEM) under the following conditions: pixel size of 50 nm and defect capture rate of more than 80%. Furthermore, the EBI-PEM achieved an inspection speed of 36 cm2/h. This inspection speed is four times higher than that of the EBI-SEM.
The EBI-PEM would be an effective tool for inspection subsequent to the 90 nm technology node generation.
We have developed a proof of concept system, utilizing a projection electron microscope for the next generation EB inspection system. In this POC system, the image quality of secondary electrons is quite sensitive to the homogeneity of wafer surface potential. In logic devices with a random pattern layout, both image distortion and inhomogeneous image contrast are serious problems. By homogenizing the wafer surface potential with negative charging of the semiconductor device, we could eliminate image distortion and inhomogeneous image contrast using a pretreatment dosage of 12 mC/cm2. Furthermore, by imaging the reflection electrons with 4000 V, a high image quality can be obtained, even with contact/via layers. By selecting the optimum energy of the imaging electrons, the imaging capability of this EB inspection system could be widely improved. We can also confirm the practicality of this technology for wafer inspection of ULSI devices.
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