Nanoimprint lithography (NIL) has the potential capability of high resolution with critical dimension uniformity that is suited for patterning shrinkage, as well as providing a low cost advantage. However, the defectivity of NIL is an impediment to the practical use of the technology in semiconductor manufacturing. We have evaluated defect levels of NIL and have classified defectivity into three categories; nonfill defects, template defects, and plug defects. New materials for both the template and resist processes reduce these defects to practical levels. Electric yields of NIL are also discussed.
Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking
capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered
having difficulty to be established as mass-production technology, unless the challenge of defectivity control is
overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to
reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment,
material, and template technologies. Recently, the investment to lithography becomes heavier burden for a
semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore,
expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future
NIL patterning innovation such as a desktop lithography.
Nanoimprint lithography has advantages such as good resolution, CD uniformity and LER. However, nanoimprint
lithography involves risks. In particular, defectivity is the most critical issue for nanoimprint lithography. Above all, the
"non-fill defects" dominate such defects for UV nanoimprint.
At the filling process of imprint resist, the capillary force that occurs between an imprint-resist and surface of template
plays an important role. Our experience, suggests there is a relationship between the filling characteristics and pattern
size of template. We also think the resist properties and the environmental conditions such as atmosphere pressure play
important roles in the filling process. This paper explains the filling process dependency on the properties mentioned
above.
We analyzed the filling process using fluid simulation. At first, we assumed several pattern sizes with the same pattern
height. Then, the filling times were estimated for each pattern size with various resist properties and the environmental
conditions. An important attribute of our simulation model is the consideration accorded to the dissolution of gas
between the template and imprint resist.
As a result, the filling time of smaller pattern was found to be shorter than that of larger pattern. The assumed patterns
are space and via on template ranging in size from 22nm width to 1000nm-width. The pattern height is 60nm.
In this paper, we studied characteristics of filling mechanism by using fluid simulation. The relations between CD and
filling time were obtained. We found that the gas dissolution rate is the dominant parameter for filling time.
We have investigated three candidate lithography technologies for 2x nm HP generation and beyond for the
application to LSI, namely, double patterning technology (DPT), EUV lithography (EUVL) and nanoimprint
lithography (NIL). In terms of lithography unit technologies and lithography integration technologies, each technology
has advantages and disadvantages from the viewpoint of difficulty, development resources, extendability, process cost,
and so on. Using a development matrix consisting of development steps and development stages, we clarified the
current development status for each technology. This matrix indicates the items for which technological critical
breakthroughs are necessary to realize LSI production. From this study, we made three lithography development
scenarios for the feasibility stage and the production stage for 2x nm HP generation and beyond.
Nanoimprint lithography is one of the candidates for NGL. Recently, the "S-FIL TM" (Step and Flash Imprint
Lithography) has been developed by MII (Molecular Imprints, Inc.). Accordingly, it is necessary to build next-generation
devices and study unit processes without delay. Because of good resolution, CD uniformity and LER, nanoimprint
lithography is attractive. However, nanoimprint lithography (S-FIL) involves risks. In order to judge whether the S-FIL
is applicable to the study of unit processes and test device fabrication, we had studied the feasibility of S-FIL technology.
As a result of previous work, we obtained the results of basic evaluation and confirmed the applicability of nanoimprint
lithography for unit process study and basic test device fabrication.
However, application of nanoimprint lithography to various test devices requires the template resolution of 22nmHP, OL
accuracy on multilayer resist, and defect density for various patterns. Therefore, in order to judge whether the S-FIL
application is extendable to various test devices, we studied the characteristics of S-FIL.
As a result of this work, we confirmed that the nanoimprint application is extendable to fabrication of various test
devices. And as a result of basic evaluation, improvement of template resolution is confirmed and the value of 22nmHP
is obtained. We confirmed the robustness of the alignment process. The defect density is related in pattern density and
spread time. Thus, reduced DD without throughput loss is required.
To extend the life of photolithography, it has been proceeded the development of the strong PSMs which has no printing 'phase shifter' defects. At PMJ '98 a defect inspection algorithm for phase shifter defects of 60 degrees on i-line multi-phase alternating PSMs was discussed. At BACUS '99, a defect printability and inspection sensitivity of multi-phase shifter defect for KrF exposure had also discussed. It was reported that the inspection tool combing \9MD84SR and STARlight had enough sensitivity for quartz bump defect that caused +/- 10 percent CD-error on 150nm L and S pattern. But, the delay of ArF exposure tool and process required DUV low-k1-lithography for next generation devices. And the, we tried to evaluate defects printability and inspection sensitivity for Logic-Gate pattern mask, that lien width is narrower than the line width evaluated by precede researchers.
Lithographic characteristics of dual-trench type alternating phase-shifting mask (PSM), whose shifters are made of perpendicular trenches with different depth alternately, are evaluated numerically and experimentally. The structure of dual-trench type PSM could reduce the difference of adjacent peak intensities created by topography on the mask. Exposure characteristics of the mask varied with depth of deep and shallow trenches, and depth of both trenches should be controlled so as to have the optimum value. Mainly, the difference in depth of deep and shallow trenches caused varying "effective phase" and depth of shallow trench caused varying "effective transmission". The depth of focus using the mask was sensitive to the effective phase difference controlled by adjusting etched depth difference between both trenches, and insensitive to depth of shallow portion. From analysis of mask process margin, respecting acceptable error of depth of both trenches, it was found that the effective transmission error caused reduction of acceptable depth error.
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